#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/gameport.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/rawmidi.h>
#include <sound/ak4531_codec.h>
#include <sound/initval.h>
#include <sound/asoundef.h>
#include <sound/ac97_codec.h>

Data Structures
struct	ensoniq

Macros
#define	CHIP1370

#define	DRIVER_NAME "ENS1370"

#define	CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */

#define	ES1371REV_ES1373_A 0x04

#define	ES1371REV_ES1373_B 0x06

#define	ES1371REV_CT5880_A 0x07

#define	CT5880REV_CT5880_C 0x02

#define	CT5880REV_CT5880_D 0x03 /* ??? -jk */

#define	CT5880REV_CT5880_E 0x04 /* mw */

#define	ES1371REV_ES1371_B 0x09

#define	EV1938REV_EV1938_A 0x00

#define	ES1371REV_ES1373_8 0x08

#define	ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)

#define	ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */

#define	ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */

#define	ES_1370_XCTL1 (1<<30) /* general purpose output bit */

#define	ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */

#define	ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */

#define	ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */

#define	ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */

#define	ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */

#define	ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */

#define	ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */

#define	ES_1371_JOY_ASELM (0x03<<24) /* mask for above */

#define	ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)

#define	ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */

#define	ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */

#define	ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */

#define	ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */

#define	ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */

#define	ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */

#define	ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */

#define	ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */

#define	ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */

#define	ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */

#define	ES_1370_WTSRSELM (0x03<<12) /* mask for above */

#define	ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */

#define	ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */

#define	ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */

#define	ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */

#define	ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */

#define	ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */

#define	ES_1370_XCTL0 (1<<8) /* generap purpose output bit */

#define	ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */

#define	ES_1371_PDLEVM (0x03<<8) /* mask for above */

#define	ES_BREQ (1<<7) /* memory bus request enable */

#define	ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */

#define	ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */

#define	ES_ADC_EN (1<<4) /* ADC capture channel enable */

#define	ES_UART_EN (1<<3) /* UART enable */

#define	ES_JYSTK_EN (1<<2) /* Joystick module enable */

#define	ES_1370_CDC_EN (1<<1) /* Codec interface enable */

#define	ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */

#define	ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */

#define	ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */

#define	ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */

#define	ES_INTR (1<<31) /* Interrupt is pending */

#define	ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */

#define	ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */

#define	ES_1373_REAR_BIT26 (1<<26)

#define	ES_1373_REAR_BIT24 (1<<24)

#define	ES_1373_GPIO_INT_EN(o) (((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */

#define	ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */

#define	ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */

#define	ES_1371_TEST (1<<16) /* test ASIC */

#define	ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */

#define	ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */

#define	ES_1370_CBUSY (1<<9) /* CODEC is busy */

#define	ES_1370_CWRIP (1<<8) /* CODEC register write in progress */

#define	ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */

#define	ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */

#define	ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */

#define	ES_1371_MPWR (1<<5) /* power level interrupt pending */

#define	ES_MCCB (1<<4) /* CCB interrupt pending */

#define	ES_UART (1<<3) /* UART interrupt pending */

#define	ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */

#define	ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */

#define	ES_ADC (1<<0) /* ADC channel interrupt pending */

#define	ES_REG_UART_DATA 0x08 /* R/W: UART data register */

#define	ES_REG_UART_STATUS 0x09 /* R/O: UART status register */

#define	ES_RXINT (1<<7) /* RX interrupt occurred */

#define	ES_TXINT (1<<2) /* TX interrupt occurred */

#define	ES_TXRDY (1<<1) /* transmitter ready */

#define	ES_RXRDY (1<<0) /* receiver ready */

#define	ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */

#define	ES_RXINTEN (1<<7) /* RX interrupt enable */

#define	ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */

#define	ES_TXINTENM (0x03<<5) /* mask for above */

#define	ES_TXINTENI(i) (((i)>>5)&0x03)

#define	ES_CNTRL(o) (((o)&0x03)<<0) /* control */

#define	ES_CNTRLM (0x03<<0) /* mask for above */

#define	ES_REG_UART_RES 0x0a /* R/W: UART reserver register */

#define	ES_TEST_MODE (1<<0) /* test mode enabled */

#define	ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */

#define	ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */

#define	ES_MEM_PAGEM (0x0f<<0) /* mask for above */

#define	ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */

#define	ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */

#define	ES_1370_CODEC_WRITE(a, d) ((((a)&0xff)<<8)\|(((d)&0xff)<<0))

#define	ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */

#define	ES_1371_CODEC_RDY (1<<31) /* codec ready */

#define	ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */

#define	EV_1938_CODEC_MAGIC (1<<26)

#define	ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */

#define	ES_1371_CODEC_WRITE(a, d) ((((a)&0x7f)<<16)\|(((d)&0xffff)<<0))

#define	ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)\|ES_1371_CODEC_PIRD)

#define	ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)

#define	ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */

#define	ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */

#define	ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */

#define	ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */

#define	ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */

#define	ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */

#define	ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */

#define	ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */

#define	ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */

#define	ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */

#define	ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */

#define	ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */

#define	ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */

#define	ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */

#define	ES_1371_JFAST (1<<31) /* fast joystick timing */

#define	ES_1371_HIB (1<<30) /* host interrupt blocking enable */

#define	ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */

#define	ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */

#define	ES_1371_VMPUM (0x03<<27) /* mask for above */

#define	ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */

#define	ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */

#define	ES_1371_VCDCM (0x03<<25) /* mask for above */

#define	ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */

#define	ES_1371_FIRQ (1<<24) /* force an interrupt */

#define	ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */

#define	ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */

#define	ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */

#define	ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */

#define	ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */

#define	ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */

#define	ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */

#define	ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */

#define	ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */

#define	ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */

#define	ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */

#define	ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */

#define	ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */

#define	ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */

#define	ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */

#define	ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */

#define	ES_P2_END_INCM (0x07<<19) /* mask for above */

#define	ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */

#define	ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */

#define	ES_P2_ST_INCM (0x07<<16) /* mask for above */

#define	ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */

#define	ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */

#define	ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */

#define	ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */

#define	ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */

#define	ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */

#define	ES_R1_INT_EN (1<<10) /* ADC interrupt enable */

#define	ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */

#define	ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */

#define	ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */

#define	ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */

#define	ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */

#define	ES_R1_MODEM (0x03<<4) /* mask for above */

#define	ES_R1_MODEI(i) (((i)>>4)&0x03)

#define	ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */

#define	ES_P2_MODEM (0x03<<2) /* mask for above */

#define	ES_P2_MODEI(i) (((i)>>2)&0x03)

#define	ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */

#define	ES_P1_MODEM (0x03<<0) /* mask for above */

#define	ES_P1_MODEI(i) (((i)>>0)&0x03)

#define	ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */

#define	ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */

#define	ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */

#define	ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)

#define	ES_REG_COUNTO(o) (((o)&0xffff)<<0)

#define	ES_REG_COUNTM (0xffff<<0)

#define	ES_REG_COUNTI(i) (((i)>>0)&0xffff)

#define	ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */

#define	ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */

#define	ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */

#define	ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */

#define	ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */

#define	ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */

#define	ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)

#define	ES_REG_FCURR_COUNTM (0xffff<<16)

#define	ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)

#define	ES_REG_FSIZEO(o) (((o)&0xffff)<<0)

#define	ES_REG_FSIZEM (0xffff<<0)

#define	ES_REG_FSIZEI(i) (((i)>>0)&0xffff)

#define	ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */

#define	ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */

#define	ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */

#define	ES_REG_UF_VALID (1<<8)

#define	ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)

#define	ES_REG_UF_BYTEM (0xff<<0)

#define	ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)

#define	ES_PAGE_DAC 0x0c

#define	ES_PAGE_ADC 0x0d

#define	ES_PAGE_UART 0x0e

#define	ES_PAGE_UART1 0x0f

#define	ES_SMPREG_DAC1 0x70

#define	ES_SMPREG_DAC2 0x74

#define	ES_SMPREG_ADC 0x78

#define	ES_SMPREG_VOL_ADC 0x6c

#define	ES_SMPREG_VOL_DAC1 0x7c

#define	ES_SMPREG_VOL_DAC2 0x7e

#define	ES_SMPREG_TRUNC_N 0x00

#define	ES_SMPREG_INT_REGS 0x01

#define	ES_SMPREG_ACCUM_FRAC 0x02

#define	ES_SMPREG_VFREQ_FRAC 0x03

#define	ES_1370_SRCLOCK 1411200

#define	ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)

#define	ES_MODE_PLAY1 0x0001

#define	ES_MODE_PLAY2 0x0002

#define	ES_MODE_CAPTURE 0x0004

#define	ES_MODE_OUTPUT 0x0001 /* for MIDI */

#define	ES_MODE_INPUT 0x0002 /* for MIDI */

#define	POLL_COUNT 0xa000

#define	ENSONIQ_CONTROL(xname, mask)

#define	snd_ensoniq_control_info snd_ctl_boolean_mono_info

#define	ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)

#define	SND_ENSONIQ_PM_OPS NULL

Functions
	MODULE_AUTHOR ("Jaroslav Kysela <[email protected]>, Thomas Sailer <[email protected]>")

	MODULE_LICENSE ("GPL")

	MODULE_DESCRIPTION ("Ensoniq AudioPCI ES1370")

	MODULE_SUPPORTED_DEVICE ("{{Ensoniq,AudioPCI-97 ES1370},""{Creative Labs,SB PCI64/128 (ES1370)}}")

	module_param_array (index, int, NULL, 0444)

	MODULE_PARM_DESC (index,"Index value for Ensoniq AudioPCI soundcard.")

	module_param_array (id, charp, NULL, 0444)

	MODULE_PARM_DESC (id,"ID string for Ensoniq AudioPCI soundcard.")

	module_param_array (enable, bool, NULL, 0444)

	MODULE_PARM_DESC (enable,"Enable Ensoniq AudioPCI soundcard.")

	MODULE_DEVICE_TABLE (pci, snd_audiopci_ids)

	module_pci_driver (ens137x_driver)

Macro Definition Documentation

#define CHIP1370

Definition at line 53 of file ens1370.c.

#define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */

Definition at line 58 of file ens1370.c.

#define CT5880REV_CT5880_C 0x02

Definition at line 132 of file ens1370.c.

#define CT5880REV_CT5880_D 0x03 /* ??? -jk */

Definition at line 133 of file ens1370.c.

#define CT5880REV_CT5880_E 0x04 /* mw */

Definition at line 134 of file ens1370.c.

#define DRIVER_NAME "ENS1370"

Definition at line 57 of file ens1370.c.

#define ENSONIQ_CONTROL	(	xname,
		mask
	)

Value:

{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
  .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
  .private_value = mask }

Definition at line 1711 of file ens1370.c.

#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)

Definition at line 1757 of file ens1370.c.

#define ES1371REV_CT5880_A 0x07

Definition at line 131 of file ens1370.c.

#define ES1371REV_ES1371_B 0x09

Definition at line 135 of file ens1370.c.

#define ES1371REV_ES1373_8 0x08

Definition at line 137 of file ens1370.c.

#define ES1371REV_ES1373_A 0x04

Definition at line 129 of file ens1370.c.

#define ES1371REV_ES1373_B 0x06

Definition at line 130 of file ens1370.c.

#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */

Definition at line 146 of file ens1370.c.

#define ES_1370_CBUSY (1<<9) /* CODEC is busy */

Definition at line 199 of file ens1370.c.

#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */

Definition at line 183 of file ens1370.c.

#define ES_1370_CODEC_WRITE	(	a,
		d
	)	((((a)&0xff)<<8)\|(((d)&0xff)<<0))

Definition at line 230 of file ens1370.c.

#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */

Definition at line 198 of file ens1370.c.

#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */

Definition at line 200 of file ens1370.c.

#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */

Definition at line 170 of file ens1370.c.

#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */

Definition at line 173 of file ens1370.c.

#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */

Definition at line 164 of file ens1370.c.

#define ES_1370_PCLKDIVI ( i ) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */

Definition at line 160 of file ens1370.c.

#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */

Definition at line 159 of file ens1370.c.

#define ES_1370_PCLKDIVO ( o ) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */

Definition at line 158 of file ens1370.c.

#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */

Definition at line 185 of file ens1370.c.

#define ES_1370_SRCLOCK 1411200

Definition at line 366 of file ens1370.c.

#define ES_1370_SRTODIV ( x ) (ES_1370_SRCLOCK/(x)-2)

Definition at line 367 of file ens1370.c.

#define ES_1370_VC ( i ) (((i)>>5)&0x03) /* voice code from CCB module */

Definition at line 203 of file ens1370.c.

#define ES_1370_WTSRSEL ( o ) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */

Definition at line 166 of file ens1370.c.

#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */

Definition at line 167 of file ens1370.c.

#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */

Definition at line 174 of file ens1370.c.

#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */

Definition at line 147 of file ens1370.c.

#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */

Definition at line 168 of file ens1370.c.

#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */

Definition at line 269 of file ens1370.c.

#define ES_1371_AI ( i ) (((i)>>3)&0x1f) /* event significant I/O address */

Definition at line 274 of file ens1370.c.

#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */

Definition at line 272 of file ens1370.c.

#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */

Definition at line 271 of file ens1370.c.

#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */

Definition at line 235 of file ens1370.c.

#define ES_1371_CODEC_RDY (1<<31) /* codec ready */

Definition at line 232 of file ens1370.c.

#define ES_1371_CODEC_READ ( i ) (((i)>>0)&0xffff)

Definition at line 238 of file ens1370.c.

#define ES_1371_CODEC_READS ( a ) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)

Definition at line 237 of file ens1370.c.

#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */

Definition at line 233 of file ens1370.c.

#define ES_1371_CODEC_WRITE	(	a,
		d
	)	((((a)&0x7f)<<16)\|(((d)&0xffff)<<0))

Definition at line 236 of file ens1370.c.

#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */

Definition at line 281 of file ens1370.c.

#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */

Definition at line 247 of file ens1370.c.

#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */

Definition at line 248 of file ens1370.c.

#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */

Definition at line 249 of file ens1370.c.

#define ES_1371_EXI ( i ) (((i)>>8)&0x07) /* event number */

Definition at line 273 of file ens1370.c.

#define ES_1371_FIRQ (1<<24) /* force an interrupt */

Definition at line 264 of file ens1370.c.

#define ES_1371_GPIO_IN ( i ) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */

Definition at line 157 of file ens1370.c.

#define ES_1371_GPIO_OUT ( o ) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */

Definition at line 161 of file ens1370.c.

#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */

Definition at line 162 of file ens1370.c.

#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */

Definition at line 256 of file ens1370.c.

#define ES_1371_JFAST (1<<31) /* fast joystick timing */

Definition at line 255 of file ens1370.c.

#define ES_1371_JOY_ASEL ( o ) (((o)&0x03)<<24)/* joystick port mapping */

Definition at line 154 of file ens1370.c.

#define ES_1371_JOY_ASELI ( i ) (((i)>>24)&0x03)

Definition at line 156 of file ens1370.c.

#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */

Definition at line 155 of file ens1370.c.

#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */

Definition at line 276 of file ens1370.c.

#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */

Definition at line 171 of file ens1370.c.

#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */

Definition at line 267 of file ens1370.c.

#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */

Definition at line 268 of file ens1370.c.

#define ES_1371_MPWR (1<<5) /* power level interrupt pending */

Definition at line 204 of file ens1370.c.

#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */

Definition at line 186 of file ens1370.c.

#define ES_1371_PDLEV ( o ) (((o)&0x03)<<8) /* current power down level */

Definition at line 175 of file ens1370.c.

#define ES_1371_PDLEVM (0x03<<8) /* mask for above */

Definition at line 176 of file ens1370.c.

#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */

Definition at line 169 of file ens1370.c.

#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */

Definition at line 265 of file ens1370.c.

#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */

Definition at line 266 of file ens1370.c.

#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */

Definition at line 246 of file ens1370.c.

#define ES_1371_SRC_RAM_ADDRI ( i ) (((i)>>25)&0x7f)/* address of the sample rate converter */

Definition at line 243 of file ens1370.c.

#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */

Definition at line 242 of file ens1370.c.

#define ES_1371_SRC_RAM_ADDRO ( o ) (((o)&0x7f)<<25)/* address of the sample rate converter */

Definition at line 241 of file ens1370.c.

#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */

Definition at line 245 of file ens1370.c.

#define ES_1371_SRC_RAM_DATAI ( i ) (((i)>>0)&0xffff)/* current value of the sample rate converter */

Definition at line 252 of file ens1370.c.

#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */

Definition at line 251 of file ens1370.c.

#define ES_1371_SRC_RAM_DATAO ( o ) (((o)&0xffff)<<0)/* current value of the sample rate converter */

Definition at line 250 of file ens1370.c.

#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */

Definition at line 244 of file ens1370.c.

#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */

Definition at line 189 of file ens1370.c.

#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */

Definition at line 270 of file ens1370.c.

#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */

Definition at line 201 of file ens1370.c.

#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */

Definition at line 165 of file ens1370.c.

#define ES_1371_TEST (1<<16) /* test ASIC */

Definition at line 196 of file ens1370.c.

#define ES_1371_VC ( i ) (((i)>>6)&0x03) /* voice code from CCB module */

Definition at line 202 of file ens1370.c.

#define ES_1371_VCDCI ( i ) (((i)>>25)&0x03)/* CODEC address */

Definition at line 263 of file ens1370.c.

#define ES_1371_VCDCM (0x03<<25) /* mask for above */

Definition at line 262 of file ens1370.c.

#define ES_1371_VCDCO ( o ) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */

Definition at line 261 of file ens1370.c.

#define ES_1371_VMPUI ( i ) (((i)>>27)&0x03)/* base register address */

Definition at line 260 of file ens1370.c.

#define ES_1371_VMPUM (0x03<<27) /* mask for above */

Definition at line 259 of file ens1370.c.

#define ES_1371_VMPUO ( o ) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */

Definition at line 258 of file ens1370.c.

#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */

Definition at line 257 of file ens1370.c.

#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */

Definition at line 275 of file ens1370.c.

#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */

Definition at line 184 of file ens1370.c.

#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */

Definition at line 148 of file ens1370.c.

#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */

Definition at line 149 of file ens1370.c.

#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */

Definition at line 150 of file ens1370.c.

#define ES_1373_GPIO_INT ( i ) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */

Definition at line 197 of file ens1370.c.

#define ES_1373_GPIO_INT_EN ( o ) (((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */

Definition at line 193 of file ens1370.c.

#define ES_1373_REAR_BIT24 (1<<24)

Definition at line 192 of file ens1370.c.

#define ES_1373_REAR_BIT26 (1<<26)

Definition at line 191 of file ens1370.c.

#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */

Definition at line 190 of file ens1370.c.

#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */

Definition at line 152 of file ens1370.c.

#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */

Definition at line 194 of file ens1370.c.

#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */

Definition at line 195 of file ens1370.c.

#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */

Definition at line 153 of file ens1370.c.

#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */

Definition at line 151 of file ens1370.c.

#define ES_ADC (1<<0) /* ADC channel interrupt pending */

Definition at line 209 of file ens1370.c.

#define ES_ADC_EN (1<<4) /* ADC capture channel enable */

Definition at line 180 of file ens1370.c.

#define ES_BREQ (1<<7) /* memory bus request enable */

Definition at line 177 of file ens1370.c.

#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */

Definition at line 172 of file ens1370.c.

#define ES_CNTRL ( o ) (((o)&0x03)<<0) /* control */

Definition at line 221 of file ens1370.c.

#define ES_CNTRLM (0x03<<0) /* mask for above */

Definition at line 222 of file ens1370.c.

#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */

Definition at line 207 of file ens1370.c.

#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */

Definition at line 178 of file ens1370.c.

#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */

Definition at line 208 of file ens1370.c.

#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */

Definition at line 179 of file ens1370.c.

#define ES_INTR (1<<31) /* Interrupt is pending */

Definition at line 188 of file ens1370.c.

#define ES_JYSTK_EN (1<<2) /* Joystick module enable */

Definition at line 182 of file ens1370.c.

#define ES_MCCB (1<<4) /* CCB interrupt pending */

Definition at line 205 of file ens1370.c.

#define ES_MEM_PAGEI ( i ) (((i)>>0)&0x0f) /* memory page select - in */

Definition at line 228 of file ens1370.c.

#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */

Definition at line 227 of file ens1370.c.

#define ES_MEM_PAGEO ( o ) (((o)&0x0f)<<0) /* memory page select - out */

Definition at line 226 of file ens1370.c.

#define ES_MODE_CAPTURE 0x0004

Definition at line 375 of file ens1370.c.

#define ES_MODE_INPUT 0x0002 /* for MIDI */

Definition at line 378 of file ens1370.c.

#define ES_MODE_OUTPUT 0x0001 /* for MIDI */

Definition at line 377 of file ens1370.c.

#define ES_MODE_PLAY1 0x0001

Definition at line 373 of file ens1370.c.

#define ES_MODE_PLAY2 0x0002

Definition at line 374 of file ens1370.c.

#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */

Definition at line 163 of file ens1370.c.

#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */

Definition at line 295 of file ens1370.c.

#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */

Definition at line 290 of file ens1370.c.

#define ES_P1_MODEI ( i ) (((i)>>0)&0x03)

Definition at line 306 of file ens1370.c.

#define ES_P1_MODEM (0x03<<0) /* mask for above */

Definition at line 305 of file ens1370.c.

#define ES_P1_MODEO ( o ) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */

Definition at line 304 of file ens1370.c.

#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */

Definition at line 292 of file ens1370.c.

#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */

Definition at line 296 of file ens1370.c.

#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */

Definition at line 297 of file ens1370.c.

#define ES_P2_END_INCI ( i ) (((i)>>16)&0x07)/* binary offset value to increment / loop end */

Definition at line 284 of file ens1370.c.

#define ES_P2_END_INCM (0x07<<19) /* mask for above */

Definition at line 283 of file ens1370.c.

#define ES_P2_END_INCO ( o ) (((o)&0x07)<<19)/* binary offset value to increment / loop end */

Definition at line 282 of file ens1370.c.

#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */

Definition at line 294 of file ens1370.c.

#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */

Definition at line 289 of file ens1370.c.

#define ES_P2_MODEI ( i ) (((i)>>2)&0x03)

Definition at line 303 of file ens1370.c.

#define ES_P2_MODEM (0x03<<2) /* mask for above */

Definition at line 302 of file ens1370.c.

#define ES_P2_MODEO ( o ) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */

Definition at line 301 of file ens1370.c.

#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */

Definition at line 291 of file ens1370.c.

#define ES_P2_ST_INCI ( i ) (((i)<<16)&0x07)/* binary offset value to increment / start */

Definition at line 287 of file ens1370.c.

#define ES_P2_ST_INCM (0x07<<16) /* mask for above */

Definition at line 286 of file ens1370.c.

#define ES_P2_ST_INCO ( o ) (((o)&0x07)<<16)/* binary offset value to increment / start */

Definition at line 285 of file ens1370.c.

#define ES_PAGE_ADC 0x0d

Definition at line 343 of file ens1370.c.

#define ES_PAGE_DAC 0x0c

Definition at line 342 of file ens1370.c.

#define ES_PAGE_UART 0x0e

Definition at line 344 of file ens1370.c.

#define ES_PAGE_UART1 0x0f

Definition at line 345 of file ens1370.c.

#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */

Definition at line 293 of file ens1370.c.

#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */

Definition at line 288 of file ens1370.c.

#define ES_R1_MODEI ( i ) (((i)>>4)&0x03)

Definition at line 300 of file ens1370.c.

#define ES_R1_MODEM (0x03<<4) /* mask for above */

Definition at line 299 of file ens1370.c.

#define ES_R1_MODEO ( o ) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */

Definition at line 298 of file ens1370.c.

#define ES_REG	(	ensoniq,
		x
	)	((ensoniq)->port + ES_REG_##x)

Definition at line 143 of file ens1370.c.

#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */

Definition at line 229 of file ens1370.c.

#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */

Definition at line 231 of file ens1370.c.

#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */

Definition at line 254 of file ens1370.c.

#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */

Definition at line 240 of file ens1370.c.

#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */

Definition at line 310 of file ens1370.c.

#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */

Definition at line 320 of file ens1370.c.

#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */

Definition at line 321 of file ens1370.c.

#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */

Definition at line 278 of file ens1370.c.

#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */

Definition at line 145 of file ens1370.c.

#define ES_REG_COUNTI ( i ) (((i)>>0)&0xffff)

Definition at line 314 of file ens1370.c.

#define ES_REG_COUNTM (0xffff<<0)

Definition at line 313 of file ens1370.c.

#define ES_REG_COUNTO ( o ) (((o)&0xffff)<<0)

Definition at line 312 of file ens1370.c.

#define ES_REG_CURR_COUNT ( i ) (((i)>>16)&0xffff)

Definition at line 311 of file ens1370.c.

#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */

Definition at line 308 of file ens1370.c.

#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */

Definition at line 316 of file ens1370.c.

#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */

Definition at line 317 of file ens1370.c.

#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */

Definition at line 309 of file ens1370.c.

#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */

Definition at line 318 of file ens1370.c.

#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */

Definition at line 319 of file ens1370.c.

#define ES_REG_FCURR_COUNTI ( i ) (((i)>>14)&0x3fffc)

Definition at line 324 of file ens1370.c.

#define ES_REG_FCURR_COUNTM (0xffff<<16)

Definition at line 323 of file ens1370.c.

#define ES_REG_FCURR_COUNTO ( o ) (((o)&0xffff)<<16)

Definition at line 322 of file ens1370.c.

#define ES_REG_FSIZEI ( i ) (((i)>>0)&0xffff)

Definition at line 327 of file ens1370.c.

#define ES_REG_FSIZEM (0xffff<<0)

Definition at line 326 of file ens1370.c.

#define ES_REG_FSIZEO ( o ) (((o)&0xffff)<<0)

Definition at line 325 of file ens1370.c.

#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */

Definition at line 225 of file ens1370.c.

#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */

Definition at line 329 of file ens1370.c.

#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */

Definition at line 328 of file ens1370.c.

#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */

Definition at line 280 of file ens1370.c.

#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */

Definition at line 187 of file ens1370.c.

#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */

Definition at line 216 of file ens1370.c.

#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */

Definition at line 210 of file ens1370.c.

#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */

Definition at line 331 of file ens1370.c.

#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */

Definition at line 223 of file ens1370.c.

#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */

Definition at line 211 of file ens1370.c.

#define ES_REG_UF_BYTEI ( i ) (((i)>>0)&0xff)

Definition at line 335 of file ens1370.c.

#define ES_REG_UF_BYTEM (0xff<<0)

Definition at line 334 of file ens1370.c.

#define ES_REG_UF_BYTEO ( o ) (((o)&0xff)<<0)

Definition at line 333 of file ens1370.c.

#define ES_REG_UF_VALID (1<<8)

Definition at line 332 of file ens1370.c.

#define ES_RXINT (1<<7) /* RX interrupt occurred */

Definition at line 212 of file ens1370.c.

#define ES_RXINTEN (1<<7) /* RX interrupt enable */

Definition at line 217 of file ens1370.c.

#define ES_RXRDY (1<<0) /* receiver ready */

Definition at line 215 of file ens1370.c.

#define ES_SMPREG_ACCUM_FRAC 0x02

Definition at line 359 of file ens1370.c.

#define ES_SMPREG_ADC 0x78

Definition at line 353 of file ens1370.c.

#define ES_SMPREG_DAC1 0x70

Definition at line 351 of file ens1370.c.

#define ES_SMPREG_DAC2 0x74

Definition at line 352 of file ens1370.c.

#define ES_SMPREG_INT_REGS 0x01

Definition at line 358 of file ens1370.c.

#define ES_SMPREG_TRUNC_N 0x00

Definition at line 357 of file ens1370.c.

#define ES_SMPREG_VFREQ_FRAC 0x03

Definition at line 360 of file ens1370.c.

#define ES_SMPREG_VOL_ADC 0x6c

Definition at line 354 of file ens1370.c.

#define ES_SMPREG_VOL_DAC1 0x7c

Definition at line 355 of file ens1370.c.

#define ES_SMPREG_VOL_DAC2 0x7e

Definition at line 356 of file ens1370.c.

#define ES_TEST_MODE (1<<0) /* test mode enabled */

Definition at line 224 of file ens1370.c.

#define ES_TXINT (1<<2) /* TX interrupt occurred */

Definition at line 213 of file ens1370.c.

#define ES_TXINTENI ( i ) (((i)>>5)&0x03)

Definition at line 220 of file ens1370.c.

#define ES_TXINTENM (0x03<<5) /* mask for above */

Definition at line 219 of file ens1370.c.

#define ES_TXINTENO ( o ) (((o)&0x03)<<5) /* TX interrupt enable */

Definition at line 218 of file ens1370.c.

#define ES_TXRDY (1<<1) /* transmitter ready */

Definition at line 214 of file ens1370.c.

#define ES_UART (1<<3) /* UART interrupt pending */

Definition at line 206 of file ens1370.c.

#define ES_UART_EN (1<<3) /* UART enable */

Definition at line 181 of file ens1370.c.

#define EV1938REV_EV1938_A 0x00

Definition at line 136 of file ens1370.c.

#define EV_1938_CODEC_MAGIC (1<<26)

Definition at line 234 of file ens1370.c.

#define POLL_COUNT 0xa000

Definition at line 467 of file ens1370.c.

#define snd_ensoniq_control_info snd_ctl_boolean_mono_info

Definition at line 1716 of file ens1370.c.

#define SND_ENSONIQ_PM_OPS NULL

Definition at line 2106 of file ens1370.c.

Function Documentation

MODULE_AUTHOR	(	"Jaroslav Kysela <[email protected]>	,
		Thomas Sailer< sailer @ife.ee.ethz.ch >"
	)

MODULE_DESCRIPTION ( "Ensoniq AudioPCI ES1370" )

MODULE_DEVICE_TABLE	(	pci	,
		snd_audiopci_ids
	)

MODULE_LICENSE ( "GPL" )

module_param_array	(	index	,
		int	,
		NULL	,
		0444
	)

module_param_array	(	id	,
		charp	,
		NULL	,
		0444
	)

module_param_array	(	enable	,
		bool	,
		NULL	,
		0444
	)

MODULE_PARM_DESC	(	index	,
		"Index value for Ensoniq AudioPCI soundcard."
	)

MODULE_PARM_DESC	(	id	,
		"ID string for Ensoniq AudioPCI soundcard."
	)

MODULE_PARM_DESC	(	enable	,
		"Enable Ensoniq AudioPCI soundcard."
	)

module_pci_driver ( ens137x_driver )

MODULE_SUPPORTED_DEVICE ( "{{Ensoniq,AudioPCI-97 ES1370},""{Creative Labs,SB PCI64/128 (ES1370)}}" )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation