Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
ens1370.c
Go to the documentation of this file.
1 /*
2  * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3  * Copyright (c) by Jaroslav Kysela <[email protected]>,
4  * Thomas Sailer <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19  *
20  */
21 
22 /* Power-Management-Code ( CONFIG_PM )
23  * for ens1371 only ( FIXME )
24  * derived from cs4281.c, atiixp.c and via82xx.c
25  * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/
26  * by Kurt J. Bosch
27  */
28 
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/gameport.h>
36 #include <linux/module.h>
37 #include <linux/mutex.h>
38 
39 #include <sound/core.h>
40 #include <sound/control.h>
41 #include <sound/pcm.h>
42 #include <sound/rawmidi.h>
43 #ifdef CHIP1371
44 #include <sound/ac97_codec.h>
45 #else
46 #include <sound/ak4531_codec.h>
47 #endif
48 #include <sound/initval.h>
49 #include <sound/asoundef.h>
50 
51 #ifndef CHIP1371
52 #undef CHIP1370
53 #define CHIP1370
54 #endif
55 
56 #ifdef CHIP1370
57 #define DRIVER_NAME "ENS1370"
58 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
59 #else
60 #define DRIVER_NAME "ENS1371"
61 #define CHIP_NAME "ES1371"
62 #endif
63 
64 
65 MODULE_AUTHOR("Jaroslav Kysela <[email protected]>, Thomas Sailer <[email protected]>");
66 MODULE_LICENSE("GPL");
67 #ifdef CHIP1370
68 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
69 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
70  "{Creative Labs,SB PCI64/128 (ES1370)}}");
71 #endif
72 #ifdef CHIP1371
73 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
74 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
75  "{Ensoniq,AudioPCI ES1373},"
76  "{Creative Labs,Ectiva EV1938},"
77  "{Creative Labs,SB PCI64/128 (ES1371/73)},"
78  "{Creative Labs,Vibra PCI128},"
79  "{Ectiva,EV1938}}");
80 #endif
81 
82 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
83 #define SUPPORT_JOYSTICK
84 #endif
85 
86 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
87 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
88 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
89 #ifdef SUPPORT_JOYSTICK
90 #ifdef CHIP1371
91 static int joystick_port[SNDRV_CARDS];
92 #else
93 static bool joystick[SNDRV_CARDS];
94 #endif
95 #endif
96 #ifdef CHIP1371
97 static int spdif[SNDRV_CARDS];
98 static int lineio[SNDRV_CARDS];
99 #endif
100 
101 module_param_array(index, int, NULL, 0444);
102 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
103 module_param_array(id, charp, NULL, 0444);
104 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
105 module_param_array(enable, bool, NULL, 0444);
106 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
107 #ifdef SUPPORT_JOYSTICK
108 #ifdef CHIP1371
109 module_param_array(joystick_port, int, NULL, 0444);
110 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
111 #else
112 module_param_array(joystick, bool, NULL, 0444);
113 MODULE_PARM_DESC(joystick, "Enable joystick.");
114 #endif
115 #endif /* SUPPORT_JOYSTICK */
116 #ifdef CHIP1371
117 module_param_array(spdif, int, NULL, 0444);
118 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
119 module_param_array(lineio, int, NULL, 0444);
120 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
121 #endif
122 
123 /* ES1371 chip ID */
124 /* This is a little confusing because all ES1371 compatible chips have the
125  same DEVICE_ID, the only thing differentiating them is the REV_ID field.
126  This is only significant if you want to enable features on the later parts.
127  Yes, I know it's stupid and why didn't we use the sub IDs?
128 */
129 #define ES1371REV_ES1373_A 0x04
130 #define ES1371REV_ES1373_B 0x06
131 #define ES1371REV_CT5880_A 0x07
132 #define CT5880REV_CT5880_C 0x02
133 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
134 #define CT5880REV_CT5880_E 0x04 /* mw */
135 #define ES1371REV_ES1371_B 0x09
136 #define EV1938REV_EV1938_A 0x00
137 #define ES1371REV_ES1373_8 0x08
138 
139 /*
140  * Direct registers
141  */
142 
143 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
144 
145 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
146 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
147 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
148 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
149 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
150 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
151 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
152 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
153 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
154 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
155 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
156 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
157 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
158 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
159 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
160 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
161 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
162 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
163 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
164 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
165 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
166 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
167 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
168 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
169 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
170 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
171 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
172 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
173 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
174 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
175 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
176 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
177 #define ES_BREQ (1<<7) /* memory bus request enable */
178 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
179 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
180 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
181 #define ES_UART_EN (1<<3) /* UART enable */
182 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
183 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
184 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
185 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
186 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
187 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
188 #define ES_INTR (1<<31) /* Interrupt is pending */
189 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
190 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
191 #define ES_1373_REAR_BIT26 (1<<26)
192 #define ES_1373_REAR_BIT24 (1<<24)
193 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
194 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
195 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
196 #define ES_1371_TEST (1<<16) /* test ASIC */
197 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
198 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
199 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
200 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
201 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
202 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
203 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
204 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
205 #define ES_MCCB (1<<4) /* CCB interrupt pending */
206 #define ES_UART (1<<3) /* UART interrupt pending */
207 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
208 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
209 #define ES_ADC (1<<0) /* ADC channel interrupt pending */
210 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
211 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
212 #define ES_RXINT (1<<7) /* RX interrupt occurred */
213 #define ES_TXINT (1<<2) /* TX interrupt occurred */
214 #define ES_TXRDY (1<<1) /* transmitter ready */
215 #define ES_RXRDY (1<<0) /* receiver ready */
216 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
217 #define ES_RXINTEN (1<<7) /* RX interrupt enable */
218 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
219 #define ES_TXINTENM (0x03<<5) /* mask for above */
220 #define ES_TXINTENI(i) (((i)>>5)&0x03)
221 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
222 #define ES_CNTRLM (0x03<<0) /* mask for above */
223 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
224 #define ES_TEST_MODE (1<<0) /* test mode enabled */
225 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
226 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
227 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
228 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
229 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
230 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
231 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
232 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
233 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
234 #define EV_1938_CODEC_MAGIC (1<<26)
235 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
236 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
237 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
238 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
239 
240 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
241 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
242 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
243 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
244 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
245 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
246 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
247 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
248 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
249 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
250 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
251 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
252 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
253 
254 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
255 #define ES_1371_JFAST (1<<31) /* fast joystick timing */
256 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
257 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
258 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
259 #define ES_1371_VMPUM (0x03<<27) /* mask for above */
260 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
261 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
262 #define ES_1371_VCDCM (0x03<<25) /* mask for above */
263 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
264 #define ES_1371_FIRQ (1<<24) /* force an interrupt */
265 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
266 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
267 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
268 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
269 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
270 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
271 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
272 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
273 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
274 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
275 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
276 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
277 
278 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
279 
280 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
281 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
282 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
283 #define ES_P2_END_INCM (0x07<<19) /* mask for above */
284 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
285 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
286 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
287 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
288 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
289 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
290 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
291 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
292 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
293 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
294 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
295 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
296 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
297 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
298 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
299 #define ES_R1_MODEM (0x03<<4) /* mask for above */
300 #define ES_R1_MODEI(i) (((i)>>4)&0x03)
301 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
302 #define ES_P2_MODEM (0x03<<2) /* mask for above */
303 #define ES_P2_MODEI(i) (((i)>>2)&0x03)
304 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
305 #define ES_P1_MODEM (0x03<<0) /* mask for above */
306 #define ES_P1_MODEI(i) (((i)>>0)&0x03)
307 
308 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
309 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
310 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
311 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
312 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
313 #define ES_REG_COUNTM (0xffff<<0)
314 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
315 
316 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
317 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
318 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
319 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
320 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
321 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
322 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
323 #define ES_REG_FCURR_COUNTM (0xffff<<16)
324 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
325 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
326 #define ES_REG_FSIZEM (0xffff<<0)
327 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
328 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
329 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
330 
331 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
332 #define ES_REG_UF_VALID (1<<8)
333 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
334 #define ES_REG_UF_BYTEM (0xff<<0)
335 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
336 
337 
338 /*
339  * Pages
340  */
341 
342 #define ES_PAGE_DAC 0x0c
343 #define ES_PAGE_ADC 0x0d
344 #define ES_PAGE_UART 0x0e
345 #define ES_PAGE_UART1 0x0f
346 
347 /*
348  * Sample rate converter addresses
349  */
350 
351 #define ES_SMPREG_DAC1 0x70
352 #define ES_SMPREG_DAC2 0x74
353 #define ES_SMPREG_ADC 0x78
354 #define ES_SMPREG_VOL_ADC 0x6c
355 #define ES_SMPREG_VOL_DAC1 0x7c
356 #define ES_SMPREG_VOL_DAC2 0x7e
357 #define ES_SMPREG_TRUNC_N 0x00
358 #define ES_SMPREG_INT_REGS 0x01
359 #define ES_SMPREG_ACCUM_FRAC 0x02
360 #define ES_SMPREG_VFREQ_FRAC 0x03
361 
362 /*
363  * Some contants
364  */
365 
366 #define ES_1370_SRCLOCK 1411200
367 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
368 
369 /*
370  * Open modes
371  */
372 
373 #define ES_MODE_PLAY1 0x0001
374 #define ES_MODE_PLAY2 0x0002
375 #define ES_MODE_CAPTURE 0x0004
376 
377 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
378 #define ES_MODE_INPUT 0x0002 /* for MIDI */
379 
380 /*
381 
382  */
383 
384 struct ensoniq {
386  struct mutex src_mutex;
387 
388  int irq;
389 
390  unsigned long playback1size;
391  unsigned long playback2size;
392  unsigned long capture3size;
393 
394  unsigned long port;
395  unsigned int mode;
396  unsigned int uartm; /* UART mode */
397 
398  unsigned int ctrl; /* control register */
399  unsigned int sctrl; /* serial control register */
400  unsigned int cssr; /* control status register */
401  unsigned int uartc; /* uart control register */
402  unsigned int rev; /* chip revision */
403 
404  union {
405 #ifdef CHIP1371
406  struct {
407  struct snd_ac97 *ac97;
408  } es1371;
409 #else
410  struct {
413  } es1370;
414 #endif
415  } u;
416 
417  struct pci_dev *pci;
418  struct snd_card *card;
419  struct snd_pcm *pcm1; /* DAC1/ADC PCM */
420  struct snd_pcm *pcm2; /* DAC2 PCM */
424  unsigned int p1_dma_size;
425  unsigned int p2_dma_size;
426  unsigned int c_dma_size;
427  unsigned int p1_period_size;
428  unsigned int p2_period_size;
429  unsigned int c_period_size;
433 
434  unsigned int spdif;
435  unsigned int spdif_default;
436  unsigned int spdif_stream;
437 
438 #ifdef CHIP1370
440 #endif
441 
442 #ifdef SUPPORT_JOYSTICK
443  struct gameport *gameport;
444 #endif
445 };
446 
447 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
448 
449 static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = {
450 #ifdef CHIP1370
451  { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
452 #endif
453 #ifdef CHIP1371
454  { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
455  { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
456  { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
457 #endif
458  { 0, }
459 };
460 
461 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
462 
463 /*
464  * constants
465  */
466 
467 #define POLL_COUNT 0xa000
468 
469 #ifdef CHIP1370
470 static unsigned int snd_es1370_fixed_rates[] =
471  {5512, 11025, 22050, 44100};
472 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
473  .count = 4,
474  .list = snd_es1370_fixed_rates,
475  .mask = 0,
476 };
477 static struct snd_ratnum es1370_clock = {
478  .num = ES_1370_SRCLOCK,
479  .den_min = 29,
480  .den_max = 353,
481  .den_step = 1,
482 };
483 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
484  .nrats = 1,
485  .rats = &es1370_clock,
486 };
487 #else
488 static struct snd_ratden es1371_dac_clock = {
489  .num_min = 3000 * (1 << 15),
490  .num_max = 48000 * (1 << 15),
491  .num_step = 3000,
492  .den = 1 << 15,
493 };
494 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
495  .nrats = 1,
496  .rats = &es1371_dac_clock,
497 };
498 static struct snd_ratnum es1371_adc_clock = {
499  .num = 48000 << 15,
500  .den_min = 32768,
501  .den_max = 393216,
502  .den_step = 1,
503 };
504 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
505  .nrats = 1,
506  .rats = &es1371_adc_clock,
507 };
508 #endif
509 static const unsigned int snd_ensoniq_sample_shift[] =
510  {0, 1, 1, 2};
511 
512 /*
513  * common I/O routines
514  */
515 
516 #ifdef CHIP1371
517 
518 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
519 {
520  unsigned int t, r = 0;
521 
522  for (t = 0; t < POLL_COUNT; t++) {
523  r = inl(ES_REG(ensoniq, 1371_SMPRATE));
524  if ((r & ES_1371_SRC_RAM_BUSY) == 0)
525  return r;
526  cond_resched();
527  }
528  snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
529  ES_REG(ensoniq, 1371_SMPRATE), r);
530  return 0;
531 }
532 
533 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
534 {
535  unsigned int temp, i, orig, r;
536 
537  /* wait for ready */
538  temp = orig = snd_es1371_wait_src_ready(ensoniq);
539 
540  /* expose the SRC state bits */
541  r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
543  r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
544  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
545 
546  /* now, wait for busy and the correct time to read */
547  temp = snd_es1371_wait_src_ready(ensoniq);
548 
549  if ((temp & 0x00870000) != 0x00010000) {
550  /* wait for the right state */
551  for (i = 0; i < POLL_COUNT; i++) {
552  temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
553  if ((temp & 0x00870000) == 0x00010000)
554  break;
555  }
556  }
557 
558  /* hide the state bits */
559  r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
561  r |= ES_1371_SRC_RAM_ADDRO(reg);
562  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
563 
564  return temp;
565 }
566 
567 static void snd_es1371_src_write(struct ensoniq * ensoniq,
568  unsigned short reg, unsigned short data)
569 {
570  unsigned int r;
571 
572  r = snd_es1371_wait_src_ready(ensoniq) &
576  outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
577 }
578 
579 #endif /* CHIP1371 */
580 
581 #ifdef CHIP1370
582 
583 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
584  unsigned short reg, unsigned short val)
585 {
586  struct ensoniq *ensoniq = ak4531->private_data;
587  unsigned long end_time = jiffies + HZ / 10;
588 
589 #if 0
591  "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
592  reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
593 #endif
594  do {
595  if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
596  outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
597  return;
598  }
600  } while (time_after(end_time, jiffies));
601  snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
602  inl(ES_REG(ensoniq, STATUS)));
603 }
604 
605 #endif /* CHIP1370 */
606 
607 #ifdef CHIP1371
608 
609 static inline bool is_ev1938(struct ensoniq *ensoniq)
610 {
611  return ensoniq->pci->device == 0x8938;
612 }
613 
614 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
615  unsigned short reg, unsigned short val)
616 {
617  struct ensoniq *ensoniq = ac97->private_data;
618  unsigned int t, x, flag;
619 
620  flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
621  mutex_lock(&ensoniq->src_mutex);
622  for (t = 0; t < POLL_COUNT; t++) {
623  if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
624  /* save the current state for latter */
625  x = snd_es1371_wait_src_ready(ensoniq);
627  ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
628  ES_REG(ensoniq, 1371_SMPRATE));
629  /* wait for not busy (state 0) first to avoid
630  transition states */
631  for (t = 0; t < POLL_COUNT; t++) {
632  if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
633  0x00000000)
634  break;
635  }
636  /* wait for a SAFE time to write addr/data and then do it, dammit */
637  for (t = 0; t < POLL_COUNT; t++) {
638  if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
639  0x00010000)
640  break;
641  }
642  outl(ES_1371_CODEC_WRITE(reg, val) | flag,
643  ES_REG(ensoniq, 1371_CODEC));
644  /* restore SRC reg */
645  snd_es1371_wait_src_ready(ensoniq);
646  outl(x, ES_REG(ensoniq, 1371_SMPRATE));
647  mutex_unlock(&ensoniq->src_mutex);
648  return;
649  }
650  }
651  mutex_unlock(&ensoniq->src_mutex);
652  snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
653  ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
654 }
655 
656 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
657  unsigned short reg)
658 {
659  struct ensoniq *ensoniq = ac97->private_data;
660  unsigned int t, x, flag, fail = 0;
661 
662  flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
663  __again:
664  mutex_lock(&ensoniq->src_mutex);
665  for (t = 0; t < POLL_COUNT; t++) {
666  if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
667  /* save the current state for latter */
668  x = snd_es1371_wait_src_ready(ensoniq);
670  ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
671  ES_REG(ensoniq, 1371_SMPRATE));
672  /* wait for not busy (state 0) first to avoid
673  transition states */
674  for (t = 0; t < POLL_COUNT; t++) {
675  if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
676  0x00000000)
677  break;
678  }
679  /* wait for a SAFE time to write addr/data and then do it, dammit */
680  for (t = 0; t < POLL_COUNT; t++) {
681  if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
682  0x00010000)
683  break;
684  }
685  outl(ES_1371_CODEC_READS(reg) | flag,
686  ES_REG(ensoniq, 1371_CODEC));
687  /* restore SRC reg */
688  snd_es1371_wait_src_ready(ensoniq);
689  outl(x, ES_REG(ensoniq, 1371_SMPRATE));
690  /* wait for WIP again */
691  for (t = 0; t < POLL_COUNT; t++) {
692  if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
693  break;
694  }
695  /* now wait for the stinkin' data (RDY) */
696  for (t = 0; t < POLL_COUNT; t++) {
697  if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
698  if (is_ev1938(ensoniq)) {
699  for (t = 0; t < 100; t++)
700  inl(ES_REG(ensoniq, CONTROL));
701  x = inl(ES_REG(ensoniq, 1371_CODEC));
702  }
703  mutex_unlock(&ensoniq->src_mutex);
704  return ES_1371_CODEC_READ(x);
705  }
706  }
707  mutex_unlock(&ensoniq->src_mutex);
708  if (++fail > 10) {
709  snd_printk(KERN_ERR "codec read timeout (final) "
710  "at 0x%lx, reg = 0x%x [0x%x]\n",
711  ES_REG(ensoniq, 1371_CODEC), reg,
712  inl(ES_REG(ensoniq, 1371_CODEC)));
713  return 0;
714  }
715  goto __again;
716  }
717  }
718  mutex_unlock(&ensoniq->src_mutex);
719  snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
720  ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
721  return 0;
722 }
723 
724 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
725 {
726  msleep(750);
727  snd_es1371_codec_read(ac97, AC97_RESET);
728  snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
729  snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
730  msleep(50);
731 }
732 
733 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
734 {
735  unsigned int n, truncm, freq, result;
736 
737  mutex_lock(&ensoniq->src_mutex);
738  n = rate / 3000;
739  if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
740  n--;
741  truncm = (21 * n - 1) | 1;
742  freq = ((48000UL << 15) / rate) * n;
743  result = (48000UL << 15) / (freq / n);
744  if (rate >= 24000) {
745  if (truncm > 239)
746  truncm = 239;
747  snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
748  (((239 - truncm) >> 1) << 9) | (n << 4));
749  } else {
750  if (truncm > 119)
751  truncm = 119;
752  snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
753  0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
754  }
755  snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
756  (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
757  ES_SMPREG_INT_REGS) & 0x00ff) |
758  ((freq >> 5) & 0xfc00));
759  snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
760  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
761  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
762  mutex_unlock(&ensoniq->src_mutex);
763 }
764 
765 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
766 {
767  unsigned int freq, r;
768 
769  mutex_lock(&ensoniq->src_mutex);
770  freq = ((rate << 15) + 1500) / 3000;
771  r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
774  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
775  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
776  (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
777  ES_SMPREG_INT_REGS) & 0x00ff) |
778  ((freq >> 5) & 0xfc00));
779  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
780  r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
782  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
783  mutex_unlock(&ensoniq->src_mutex);
784 }
785 
786 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
787 {
788  unsigned int freq, r;
789 
790  mutex_lock(&ensoniq->src_mutex);
791  freq = ((rate << 15) + 1500) / 3000;
792  r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
795  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
796  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
797  (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
798  ES_SMPREG_INT_REGS) & 0x00ff) |
799  ((freq >> 5) & 0xfc00));
800  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
801  freq & 0x7fff);
802  r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
804  outl(r, ES_REG(ensoniq, 1371_SMPRATE));
805  mutex_unlock(&ensoniq->src_mutex);
806 }
807 
808 #endif /* CHIP1371 */
809 
810 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
811 {
812  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
813  switch (cmd) {
816  {
817  unsigned int what = 0;
818  struct snd_pcm_substream *s;
819  snd_pcm_group_for_each_entry(s, substream) {
820  if (s == ensoniq->playback1_substream) {
821  what |= ES_P1_PAUSE;
822  snd_pcm_trigger_done(s, substream);
823  } else if (s == ensoniq->playback2_substream) {
824  what |= ES_P2_PAUSE;
825  snd_pcm_trigger_done(s, substream);
826  } else if (s == ensoniq->capture_substream)
827  return -EINVAL;
828  }
829  spin_lock(&ensoniq->reg_lock);
830  if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
831  ensoniq->sctrl |= what;
832  else
833  ensoniq->sctrl &= ~what;
834  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
835  spin_unlock(&ensoniq->reg_lock);
836  break;
837  }
840  {
841  unsigned int what = 0;
842  struct snd_pcm_substream *s;
843  snd_pcm_group_for_each_entry(s, substream) {
844  if (s == ensoniq->playback1_substream) {
845  what |= ES_DAC1_EN;
846  snd_pcm_trigger_done(s, substream);
847  } else if (s == ensoniq->playback2_substream) {
848  what |= ES_DAC2_EN;
849  snd_pcm_trigger_done(s, substream);
850  } else if (s == ensoniq->capture_substream) {
851  what |= ES_ADC_EN;
852  snd_pcm_trigger_done(s, substream);
853  }
854  }
855  spin_lock(&ensoniq->reg_lock);
856  if (cmd == SNDRV_PCM_TRIGGER_START)
857  ensoniq->ctrl |= what;
858  else
859  ensoniq->ctrl &= ~what;
860  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
861  spin_unlock(&ensoniq->reg_lock);
862  break;
863  }
864  default:
865  return -EINVAL;
866  }
867  return 0;
868 }
869 
870 /*
871  * PCM part
872  */
873 
874 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
875  struct snd_pcm_hw_params *hw_params)
876 {
877  return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
878 }
879 
880 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
881 {
882  return snd_pcm_lib_free_pages(substream);
883 }
884 
885 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
886 {
887  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
888  struct snd_pcm_runtime *runtime = substream->runtime;
889  unsigned int mode = 0;
890 
891  ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
892  ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
893  if (snd_pcm_format_width(runtime->format) == 16)
894  mode |= 0x02;
895  if (runtime->channels > 1)
896  mode |= 0x01;
897  spin_lock_irq(&ensoniq->reg_lock);
898  ensoniq->ctrl &= ~ES_DAC1_EN;
899 #ifdef CHIP1371
900  /* 48k doesn't need SRC (it breaks AC3-passthru) */
901  if (runtime->rate == 48000)
902  ensoniq->ctrl |= ES_1373_BYPASS_P1;
903  else
904  ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
905 #endif
906  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
907  outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
908  outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
909  outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
911  ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
912  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
913  outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
914  ES_REG(ensoniq, DAC1_COUNT));
915 #ifdef CHIP1370
916  ensoniq->ctrl &= ~ES_1370_WTSRSELM;
917  switch (runtime->rate) {
918  case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
919  case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
920  case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
921  case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
922  default: snd_BUG();
923  }
924 #endif
925  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
926  spin_unlock_irq(&ensoniq->reg_lock);
927 #ifndef CHIP1370
928  snd_es1371_dac1_rate(ensoniq, runtime->rate);
929 #endif
930  return 0;
931 }
932 
933 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
934 {
935  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
936  struct snd_pcm_runtime *runtime = substream->runtime;
937  unsigned int mode = 0;
938 
939  ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
940  ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
941  if (snd_pcm_format_width(runtime->format) == 16)
942  mode |= 0x02;
943  if (runtime->channels > 1)
944  mode |= 0x01;
945  spin_lock_irq(&ensoniq->reg_lock);
946  ensoniq->ctrl &= ~ES_DAC2_EN;
947  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
948  outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
949  outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
950  outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
951  ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
953  ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
954  ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
955  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
956  outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
957  ES_REG(ensoniq, DAC2_COUNT));
958 #ifdef CHIP1370
959  if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
960  ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
961  ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
962  ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
963  }
964 #endif
965  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
966  spin_unlock_irq(&ensoniq->reg_lock);
967 #ifndef CHIP1370
968  snd_es1371_dac2_rate(ensoniq, runtime->rate);
969 #endif
970  return 0;
971 }
972 
973 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
974 {
975  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
976  struct snd_pcm_runtime *runtime = substream->runtime;
977  unsigned int mode = 0;
978 
979  ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
980  ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
981  if (snd_pcm_format_width(runtime->format) == 16)
982  mode |= 0x02;
983  if (runtime->channels > 1)
984  mode |= 0x01;
985  spin_lock_irq(&ensoniq->reg_lock);
986  ensoniq->ctrl &= ~ES_ADC_EN;
987  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
988  outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
989  outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
990  outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
991  ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
992  ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
993  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
994  outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
995  ES_REG(ensoniq, ADC_COUNT));
996 #ifdef CHIP1370
997  if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
998  ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
999  ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
1000  ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
1001  }
1002 #endif
1003  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1004  spin_unlock_irq(&ensoniq->reg_lock);
1005 #ifndef CHIP1370
1006  snd_es1371_adc_rate(ensoniq, runtime->rate);
1007 #endif
1008  return 0;
1009 }
1010 
1011 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1012 {
1013  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014  size_t ptr;
1015 
1016  spin_lock(&ensoniq->reg_lock);
1017  if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1018  outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1019  ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1020  ptr = bytes_to_frames(substream->runtime, ptr);
1021  } else {
1022  ptr = 0;
1023  }
1024  spin_unlock(&ensoniq->reg_lock);
1025  return ptr;
1026 }
1027 
1028 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1029 {
1030  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1031  size_t ptr;
1032 
1033  spin_lock(&ensoniq->reg_lock);
1034  if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1035  outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1036  ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1037  ptr = bytes_to_frames(substream->runtime, ptr);
1038  } else {
1039  ptr = 0;
1040  }
1041  spin_unlock(&ensoniq->reg_lock);
1042  return ptr;
1043 }
1044 
1045 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1046 {
1047  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1048  size_t ptr;
1049 
1050  spin_lock(&ensoniq->reg_lock);
1051  if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1052  outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1053  ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1054  ptr = bytes_to_frames(substream->runtime, ptr);
1055  } else {
1056  ptr = 0;
1057  }
1058  spin_unlock(&ensoniq->reg_lock);
1059  return ptr;
1060 }
1061 
1062 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1063 {
1069  .rates =
1070 #ifndef CHIP1370
1072 #else
1073  (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1076 #endif
1077  .rate_min = 4000,
1078  .rate_max = 48000,
1079  .channels_min = 1,
1080  .channels_max = 2,
1081  .buffer_bytes_max = (128*1024),
1082  .period_bytes_min = 64,
1083  .period_bytes_max = (128*1024),
1084  .periods_min = 1,
1085  .periods_max = 1024,
1086  .fifo_size = 0,
1087 };
1088 
1089 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1090 {
1097  .rate_min = 4000,
1098  .rate_max = 48000,
1099  .channels_min = 1,
1100  .channels_max = 2,
1101  .buffer_bytes_max = (128*1024),
1102  .period_bytes_min = 64,
1103  .period_bytes_max = (128*1024),
1104  .periods_min = 1,
1105  .periods_max = 1024,
1106  .fifo_size = 0,
1107 };
1108 
1109 static struct snd_pcm_hardware snd_ensoniq_capture =
1110 {
1116  .rate_min = 4000,
1117  .rate_max = 48000,
1118  .channels_min = 1,
1119  .channels_max = 2,
1120  .buffer_bytes_max = (128*1024),
1121  .period_bytes_min = 64,
1122  .period_bytes_max = (128*1024),
1123  .periods_min = 1,
1124  .periods_max = 1024,
1125  .fifo_size = 0,
1126 };
1127 
1128 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1129 {
1130  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1131  struct snd_pcm_runtime *runtime = substream->runtime;
1132 
1133  ensoniq->mode |= ES_MODE_PLAY1;
1134  ensoniq->playback1_substream = substream;
1135  runtime->hw = snd_ensoniq_playback1;
1136  snd_pcm_set_sync(substream);
1137  spin_lock_irq(&ensoniq->reg_lock);
1138  if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1139  ensoniq->spdif_stream = ensoniq->spdif_default;
1140  spin_unlock_irq(&ensoniq->reg_lock);
1141 #ifdef CHIP1370
1143  &snd_es1370_hw_constraints_rates);
1144 #else
1146  &snd_es1371_hw_constraints_dac_clock);
1147 #endif
1148  return 0;
1149 }
1150 
1151 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1152 {
1153  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1154  struct snd_pcm_runtime *runtime = substream->runtime;
1155 
1156  ensoniq->mode |= ES_MODE_PLAY2;
1157  ensoniq->playback2_substream = substream;
1158  runtime->hw = snd_ensoniq_playback2;
1159  snd_pcm_set_sync(substream);
1160  spin_lock_irq(&ensoniq->reg_lock);
1161  if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1162  ensoniq->spdif_stream = ensoniq->spdif_default;
1163  spin_unlock_irq(&ensoniq->reg_lock);
1164 #ifdef CHIP1370
1166  &snd_es1370_hw_constraints_clock);
1167 #else
1169  &snd_es1371_hw_constraints_dac_clock);
1170 #endif
1171  return 0;
1172 }
1173 
1174 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1175 {
1176  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1177  struct snd_pcm_runtime *runtime = substream->runtime;
1178 
1179  ensoniq->mode |= ES_MODE_CAPTURE;
1180  ensoniq->capture_substream = substream;
1181  runtime->hw = snd_ensoniq_capture;
1182  snd_pcm_set_sync(substream);
1183 #ifdef CHIP1370
1185  &snd_es1370_hw_constraints_clock);
1186 #else
1188  &snd_es1371_hw_constraints_adc_clock);
1189 #endif
1190  return 0;
1191 }
1192 
1193 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1194 {
1195  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1196 
1197  ensoniq->playback1_substream = NULL;
1198  ensoniq->mode &= ~ES_MODE_PLAY1;
1199  return 0;
1200 }
1201 
1202 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1203 {
1204  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1205 
1206  ensoniq->playback2_substream = NULL;
1207  spin_lock_irq(&ensoniq->reg_lock);
1208 #ifdef CHIP1370
1209  ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1210 #endif
1211  ensoniq->mode &= ~ES_MODE_PLAY2;
1212  spin_unlock_irq(&ensoniq->reg_lock);
1213  return 0;
1214 }
1215 
1216 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1217 {
1218  struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1219 
1220  ensoniq->capture_substream = NULL;
1221  spin_lock_irq(&ensoniq->reg_lock);
1222 #ifdef CHIP1370
1223  ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1224 #endif
1225  ensoniq->mode &= ~ES_MODE_CAPTURE;
1226  spin_unlock_irq(&ensoniq->reg_lock);
1227  return 0;
1228 }
1229 
1230 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1231  .open = snd_ensoniq_playback1_open,
1232  .close = snd_ensoniq_playback1_close,
1233  .ioctl = snd_pcm_lib_ioctl,
1234  .hw_params = snd_ensoniq_hw_params,
1235  .hw_free = snd_ensoniq_hw_free,
1236  .prepare = snd_ensoniq_playback1_prepare,
1237  .trigger = snd_ensoniq_trigger,
1238  .pointer = snd_ensoniq_playback1_pointer,
1239 };
1240 
1241 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1242  .open = snd_ensoniq_playback2_open,
1243  .close = snd_ensoniq_playback2_close,
1244  .ioctl = snd_pcm_lib_ioctl,
1245  .hw_params = snd_ensoniq_hw_params,
1246  .hw_free = snd_ensoniq_hw_free,
1247  .prepare = snd_ensoniq_playback2_prepare,
1248  .trigger = snd_ensoniq_trigger,
1249  .pointer = snd_ensoniq_playback2_pointer,
1250 };
1251 
1252 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1253  .open = snd_ensoniq_capture_open,
1254  .close = snd_ensoniq_capture_close,
1255  .ioctl = snd_pcm_lib_ioctl,
1256  .hw_params = snd_ensoniq_hw_params,
1257  .hw_free = snd_ensoniq_hw_free,
1258  .prepare = snd_ensoniq_capture_prepare,
1259  .trigger = snd_ensoniq_trigger,
1260  .pointer = snd_ensoniq_capture_pointer,
1261 };
1262 
1263 static const struct snd_pcm_chmap_elem surround_map[] = {
1264  { .channels = 1,
1265  .map = { SNDRV_CHMAP_MONO } },
1266  { .channels = 2,
1267  .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1268  { }
1269 };
1270 
1271 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1272  struct snd_pcm ** rpcm)
1273 {
1274  struct snd_pcm *pcm;
1275  int err;
1276 
1277  if (rpcm)
1278  *rpcm = NULL;
1279  err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1280  if (err < 0)
1281  return err;
1282 
1283 #ifdef CHIP1370
1284  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1285 #else
1286  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1287 #endif
1288  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1289 
1290  pcm->private_data = ensoniq;
1291  pcm->info_flags = 0;
1292  strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1293  ensoniq->pcm1 = pcm;
1294 
1296  snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1297 
1298 #ifdef CHIP1370
1300  surround_map, 2, 0, NULL);
1301 #else
1303  snd_pcm_std_chmaps, 2, 0, NULL);
1304 #endif
1305  if (err < 0)
1306  return err;
1307 
1308  if (rpcm)
1309  *rpcm = pcm;
1310  return 0;
1311 }
1312 
1313 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1314  struct snd_pcm ** rpcm)
1315 {
1316  struct snd_pcm *pcm;
1317  int err;
1318 
1319  if (rpcm)
1320  *rpcm = NULL;
1321  err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1322  if (err < 0)
1323  return err;
1324 
1325 #ifdef CHIP1370
1326  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1327 #else
1328  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1329 #endif
1330  pcm->private_data = ensoniq;
1331  pcm->info_flags = 0;
1332  strcpy(pcm->name, CHIP_NAME " DAC1");
1333  ensoniq->pcm2 = pcm;
1334 
1336  snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1337 
1338 #ifdef CHIP1370
1340  snd_pcm_std_chmaps, 2, 0, NULL);
1341 #else
1343  surround_map, 2, 0, NULL);
1344 #endif
1345  if (err < 0)
1346  return err;
1347 
1348  if (rpcm)
1349  *rpcm = pcm;
1350  return 0;
1351 }
1352 
1353 /*
1354  * Mixer section
1355  */
1356 
1357 /*
1358  * ENS1371 mixer (including SPDIF interface)
1359  */
1360 #ifdef CHIP1371
1361 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1362  struct snd_ctl_elem_info *uinfo)
1363 {
1365  uinfo->count = 1;
1366  return 0;
1367 }
1368 
1369 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1370  struct snd_ctl_elem_value *ucontrol)
1371 {
1372  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1373  spin_lock_irq(&ensoniq->reg_lock);
1374  ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1375  ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1376  ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1377  ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1378  spin_unlock_irq(&ensoniq->reg_lock);
1379  return 0;
1380 }
1381 
1382 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1383  struct snd_ctl_elem_value *ucontrol)
1384 {
1385  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1386  unsigned int val;
1387  int change;
1388 
1389  val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1390  ((u32)ucontrol->value.iec958.status[1] << 8) |
1391  ((u32)ucontrol->value.iec958.status[2] << 16) |
1392  ((u32)ucontrol->value.iec958.status[3] << 24);
1393  spin_lock_irq(&ensoniq->reg_lock);
1394  change = ensoniq->spdif_default != val;
1395  ensoniq->spdif_default = val;
1396  if (change && ensoniq->playback1_substream == NULL &&
1397  ensoniq->playback2_substream == NULL)
1398  outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1399  spin_unlock_irq(&ensoniq->reg_lock);
1400  return change;
1401 }
1402 
1403 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1404  struct snd_ctl_elem_value *ucontrol)
1405 {
1406  ucontrol->value.iec958.status[0] = 0xff;
1407  ucontrol->value.iec958.status[1] = 0xff;
1408  ucontrol->value.iec958.status[2] = 0xff;
1409  ucontrol->value.iec958.status[3] = 0xff;
1410  return 0;
1411 }
1412 
1413 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1414  struct snd_ctl_elem_value *ucontrol)
1415 {
1416  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1417  spin_lock_irq(&ensoniq->reg_lock);
1418  ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1419  ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1420  ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1421  ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1422  spin_unlock_irq(&ensoniq->reg_lock);
1423  return 0;
1424 }
1425 
1426 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1427  struct snd_ctl_elem_value *ucontrol)
1428 {
1429  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1430  unsigned int val;
1431  int change;
1432 
1433  val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1434  ((u32)ucontrol->value.iec958.status[1] << 8) |
1435  ((u32)ucontrol->value.iec958.status[2] << 16) |
1436  ((u32)ucontrol->value.iec958.status[3] << 24);
1437  spin_lock_irq(&ensoniq->reg_lock);
1438  change = ensoniq->spdif_stream != val;
1439  ensoniq->spdif_stream = val;
1440  if (change && (ensoniq->playback1_substream != NULL ||
1441  ensoniq->playback2_substream != NULL))
1442  outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1443  spin_unlock_irq(&ensoniq->reg_lock);
1444  return change;
1445 }
1446 
1447 #define ES1371_SPDIF(xname) \
1448 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1449  .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1450 
1451 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1452 
1453 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1454  struct snd_ctl_elem_value *ucontrol)
1455 {
1456  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1457 
1458  spin_lock_irq(&ensoniq->reg_lock);
1459  ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1460  spin_unlock_irq(&ensoniq->reg_lock);
1461  return 0;
1462 }
1463 
1464 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1465  struct snd_ctl_elem_value *ucontrol)
1466 {
1467  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1468  unsigned int nval1, nval2;
1469  int change;
1470 
1471  nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1472  nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1473  spin_lock_irq(&ensoniq->reg_lock);
1474  change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1475  ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1476  ensoniq->ctrl |= nval1;
1477  ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1478  ensoniq->cssr |= nval2;
1479  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1480  outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1481  spin_unlock_irq(&ensoniq->reg_lock);
1482  return change;
1483 }
1484 
1485 
1486 /* spdif controls */
1487 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1488  ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1489  {
1490  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1492  .info = snd_ens1373_spdif_info,
1493  .get = snd_ens1373_spdif_default_get,
1494  .put = snd_ens1373_spdif_default_put,
1495  },
1496  {
1497  .access = SNDRV_CTL_ELEM_ACCESS_READ,
1498  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1499  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1500  .info = snd_ens1373_spdif_info,
1501  .get = snd_ens1373_spdif_mask_get
1502  },
1503  {
1504  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1505  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1506  .info = snd_ens1373_spdif_info,
1507  .get = snd_ens1373_spdif_stream_get,
1508  .put = snd_ens1373_spdif_stream_put
1509  },
1510 };
1511 
1512 
1513 #define snd_es1373_rear_info snd_ctl_boolean_mono_info
1514 
1515 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1516  struct snd_ctl_elem_value *ucontrol)
1517 {
1518  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1519  int val = 0;
1520 
1521  spin_lock_irq(&ensoniq->reg_lock);
1522  if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1524  val = 1;
1525  ucontrol->value.integer.value[0] = val;
1526  spin_unlock_irq(&ensoniq->reg_lock);
1527  return 0;
1528 }
1529 
1530 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1531  struct snd_ctl_elem_value *ucontrol)
1532 {
1533  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1534  unsigned int nval1;
1535  int change;
1536 
1537  nval1 = ucontrol->value.integer.value[0] ?
1539  spin_lock_irq(&ensoniq->reg_lock);
1540  change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1543  ensoniq->cssr |= nval1;
1544  outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1545  spin_unlock_irq(&ensoniq->reg_lock);
1546  return change;
1547 }
1548 
1549 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1550 {
1552  .name = "AC97 2ch->4ch Copy Switch",
1553  .info = snd_es1373_rear_info,
1554  .get = snd_es1373_rear_get,
1555  .put = snd_es1373_rear_put,
1556 };
1557 
1558 #define snd_es1373_line_info snd_ctl_boolean_mono_info
1559 
1560 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1561  struct snd_ctl_elem_value *ucontrol)
1562 {
1563  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1564  int val = 0;
1565 
1566  spin_lock_irq(&ensoniq->reg_lock);
1567  if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1568  val = 1;
1569  ucontrol->value.integer.value[0] = val;
1570  spin_unlock_irq(&ensoniq->reg_lock);
1571  return 0;
1572 }
1573 
1574 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1575  struct snd_ctl_elem_value *ucontrol)
1576 {
1577  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1578  int changed;
1579  unsigned int ctrl;
1580 
1581  spin_lock_irq(&ensoniq->reg_lock);
1582  ctrl = ensoniq->ctrl;
1583  if (ucontrol->value.integer.value[0])
1584  ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1585  else
1586  ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1587  changed = (ctrl != ensoniq->ctrl);
1588  if (changed)
1589  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1590  spin_unlock_irq(&ensoniq->reg_lock);
1591  return changed;
1592 }
1593 
1594 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1595 {
1597  .name = "Line In->Rear Out Switch",
1598  .info = snd_es1373_line_info,
1599  .get = snd_es1373_line_get,
1600  .put = snd_es1373_line_put,
1601 };
1602 
1603 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1604 {
1605  struct ensoniq *ensoniq = ac97->private_data;
1606  ensoniq->u.es1371.ac97 = NULL;
1607 }
1608 
1609 struct es1371_quirk {
1610  unsigned short vid; /* vendor ID */
1611  unsigned short did; /* device ID */
1612  unsigned char rev; /* revision */
1613 };
1614 
1615 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1616  struct es1371_quirk *list)
1617 {
1618  while (list->vid != (unsigned short)PCI_ANY_ID) {
1619  if (ensoniq->pci->vendor == list->vid &&
1620  ensoniq->pci->device == list->did &&
1621  ensoniq->rev == list->rev)
1622  return 1;
1623  list++;
1624  }
1625  return 0;
1626 }
1627 
1628 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1634  { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1635 };
1636 
1637 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1638  SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1639  SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1640  { } /* end */
1641 };
1642 
1643 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1644  int has_spdif, int has_line)
1645 {
1646  struct snd_card *card = ensoniq->card;
1647  struct snd_ac97_bus *pbus;
1648  struct snd_ac97_template ac97;
1649  int err;
1650  static struct snd_ac97_bus_ops ops = {
1651  .write = snd_es1371_codec_write,
1652  .read = snd_es1371_codec_read,
1653  .wait = snd_es1371_codec_wait,
1654  };
1655 
1656  if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1657  return err;
1658 
1659  memset(&ac97, 0, sizeof(ac97));
1660  ac97.private_data = ensoniq;
1661  ac97.private_free = snd_ensoniq_mixer_free_ac97;
1662  ac97.pci = ensoniq->pci;
1663  ac97.scaps = AC97_SCAP_AUDIO;
1664  if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1665  return err;
1666  if (has_spdif > 0 ||
1667  (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1668  struct snd_kcontrol *kctl;
1669  int i, is_spdif = 0;
1670 
1671  ensoniq->spdif_default = ensoniq->spdif_stream =
1673  outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1674 
1675  if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1676  is_spdif++;
1677 
1678  for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1679  kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1680  if (!kctl)
1681  return -ENOMEM;
1682  kctl->id.index = is_spdif;
1683  err = snd_ctl_add(card, kctl);
1684  if (err < 0)
1685  return err;
1686  }
1687  }
1688  if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1689  /* mirror rear to front speakers */
1691  ensoniq->cssr |= ES_1373_REAR_BIT26;
1692  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1693  if (err < 0)
1694  return err;
1695  }
1696  if (has_line > 0 ||
1697  snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1698  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1699  ensoniq));
1700  if (err < 0)
1701  return err;
1702  }
1703 
1704  return 0;
1705 }
1706 
1707 #endif /* CHIP1371 */
1708 
1709 /* generic control callbacks for ens1370 */
1710 #ifdef CHIP1370
1711 #define ENSONIQ_CONTROL(xname, mask) \
1712 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1713  .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1714  .private_value = mask }
1715 
1716 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1717 
1718 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1719  struct snd_ctl_elem_value *ucontrol)
1720 {
1721  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1722  int mask = kcontrol->private_value;
1723 
1724  spin_lock_irq(&ensoniq->reg_lock);
1725  ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1726  spin_unlock_irq(&ensoniq->reg_lock);
1727  return 0;
1728 }
1729 
1730 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1731  struct snd_ctl_elem_value *ucontrol)
1732 {
1733  struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1734  int mask = kcontrol->private_value;
1735  unsigned int nval;
1736  int change;
1737 
1738  nval = ucontrol->value.integer.value[0] ? mask : 0;
1739  spin_lock_irq(&ensoniq->reg_lock);
1740  change = (ensoniq->ctrl & mask) != nval;
1741  ensoniq->ctrl &= ~mask;
1742  ensoniq->ctrl |= nval;
1743  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1744  spin_unlock_irq(&ensoniq->reg_lock);
1745  return change;
1746 }
1747 
1748 /*
1749  * ENS1370 mixer
1750  */
1751 
1752 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1753 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1754 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1755 };
1756 
1757 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1758 
1759 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1760 {
1761  struct ensoniq *ensoniq = ak4531->private_data;
1762  ensoniq->u.es1370.ak4531 = NULL;
1763 }
1764 
1765 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1766 {
1767  struct snd_card *card = ensoniq->card;
1768  struct snd_ak4531 ak4531;
1769  unsigned int idx;
1770  int err;
1771 
1772  /* try reset AK4531 */
1773  outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1774  inw(ES_REG(ensoniq, 1370_CODEC));
1775  udelay(100);
1776  outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1777  inw(ES_REG(ensoniq, 1370_CODEC));
1778  udelay(100);
1779 
1780  memset(&ak4531, 0, sizeof(ak4531));
1781  ak4531.write = snd_es1370_codec_write;
1782  ak4531.private_data = ensoniq;
1783  ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1784  if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1785  return err;
1786  for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1787  err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1788  if (err < 0)
1789  return err;
1790  }
1791  return 0;
1792 }
1793 
1794 #endif /* CHIP1370 */
1795 
1796 #ifdef SUPPORT_JOYSTICK
1797 
1798 #ifdef CHIP1371
1799 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1800 {
1801  switch (joystick_port[dev]) {
1802  case 0: /* disabled */
1803  case 1: /* auto-detect */
1804  case 0x200:
1805  case 0x208:
1806  case 0x210:
1807  case 0x218:
1808  return joystick_port[dev];
1809 
1810  default:
1811  printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1812  return 0;
1813  }
1814 }
1815 #else
1816 static inline int snd_ensoniq_get_joystick_port(int dev)
1817 {
1818  return joystick[dev] ? 0x200 : 0;
1819 }
1820 #endif
1821 
1822 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1823 {
1824  struct gameport *gp;
1825  int io_port;
1826 
1827  io_port = snd_ensoniq_get_joystick_port(dev);
1828 
1829  switch (io_port) {
1830  case 0:
1831  return -ENOSYS;
1832 
1833  case 1: /* auto_detect */
1834  for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1835  if (request_region(io_port, 8, "ens137x: gameport"))
1836  break;
1837  if (io_port > 0x218) {
1838  printk(KERN_WARNING "ens137x: no gameport ports available\n");
1839  return -EBUSY;
1840  }
1841  break;
1842 
1843  default:
1844  if (!request_region(io_port, 8, "ens137x: gameport")) {
1845  printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1846  io_port);
1847  return -EBUSY;
1848  }
1849  break;
1850  }
1851 
1852  ensoniq->gameport = gp = gameport_allocate_port();
1853  if (!gp) {
1854  printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1855  release_region(io_port, 8);
1856  return -ENOMEM;
1857  }
1858 
1859  gameport_set_name(gp, "ES137x");
1860  gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1861  gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1862  gp->io = io_port;
1863 
1864  ensoniq->ctrl |= ES_JYSTK_EN;
1865 #ifdef CHIP1371
1866  ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1867  ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1868 #endif
1869  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1870 
1871  gameport_register_port(ensoniq->gameport);
1872 
1873  return 0;
1874 }
1875 
1876 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1877 {
1878  if (ensoniq->gameport) {
1879  int port = ensoniq->gameport->io;
1880 
1881  gameport_unregister_port(ensoniq->gameport);
1882  ensoniq->gameport = NULL;
1883  ensoniq->ctrl &= ~ES_JYSTK_EN;
1884  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1885  release_region(port, 8);
1886  }
1887 }
1888 #else
1889 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1890 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1891 #endif /* SUPPORT_JOYSTICK */
1892 
1893 /*
1894 
1895  */
1896 
1897 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1898  struct snd_info_buffer *buffer)
1899 {
1900  struct ensoniq *ensoniq = entry->private_data;
1901 
1902  snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1903  snd_iprintf(buffer, "Joystick enable : %s\n",
1904  ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1905 #ifdef CHIP1370
1906  snd_iprintf(buffer, "MIC +5V bias : %s\n",
1907  ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1908  snd_iprintf(buffer, "Line In to AOUT : %s\n",
1909  ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1910 #else
1911  snd_iprintf(buffer, "Joystick port : 0x%x\n",
1912  (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1913 #endif
1914 }
1915 
1916 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1917 {
1918  struct snd_info_entry *entry;
1919 
1920  if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1921  snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1922 }
1923 
1924 /*
1925 
1926  */
1927 
1928 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1929 {
1930  snd_ensoniq_free_gameport(ensoniq);
1931  if (ensoniq->irq < 0)
1932  goto __hw_end;
1933 #ifdef CHIP1370
1934  outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1935  outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1936 #else
1937  outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1938  outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1939 #endif
1940  if (ensoniq->irq >= 0)
1941  synchronize_irq(ensoniq->irq);
1942  pci_set_power_state(ensoniq->pci, 3);
1943  __hw_end:
1944 #ifdef CHIP1370
1945  if (ensoniq->dma_bug.area)
1946  snd_dma_free_pages(&ensoniq->dma_bug);
1947 #endif
1948  if (ensoniq->irq >= 0)
1949  free_irq(ensoniq->irq, ensoniq);
1950  pci_release_regions(ensoniq->pci);
1951  pci_disable_device(ensoniq->pci);
1952  kfree(ensoniq);
1953  return 0;
1954 }
1955 
1956 static int snd_ensoniq_dev_free(struct snd_device *device)
1957 {
1958  struct ensoniq *ensoniq = device->device_data;
1959  return snd_ensoniq_free(ensoniq);
1960 }
1961 
1962 #ifdef CHIP1371
1963 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1964  SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1965  SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1966  SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1967  SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1968  { } /* end */
1969 };
1970 
1971 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1977  { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1978 };
1979 #endif
1980 
1981 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1982 {
1983 #ifdef CHIP1371
1984  int idx;
1985 #endif
1986  /* this code was part of snd_ensoniq_create before intruduction
1987  * of suspend/resume
1988  */
1989 #ifdef CHIP1370
1990  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1991  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1992  outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1993  outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1994  outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1995 #else
1996  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1997  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1998  outl(0, ES_REG(ensoniq, 1371_LEGACY));
1999  if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
2000  outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2001  /* need to delay around 20ms(bleech) to give
2002  some CODECs enough time to wakeup */
2003  msleep(20);
2004  }
2005  /* AC'97 warm reset to start the bitclk */
2006  outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2007  inl(ES_REG(ensoniq, CONTROL));
2008  udelay(20);
2009  outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2010  /* Init the sample rate converter */
2011  snd_es1371_wait_src_ready(ensoniq);
2012  outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2013  for (idx = 0; idx < 0x80; idx++)
2014  snd_es1371_src_write(ensoniq, idx, 0);
2015  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2016  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2017  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2018  snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2019  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2020  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2021  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2022  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2023  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2024  snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2025  snd_es1371_adc_rate(ensoniq, 22050);
2026  snd_es1371_dac1_rate(ensoniq, 22050);
2027  snd_es1371_dac2_rate(ensoniq, 22050);
2028  /* WARNING:
2029  * enabling the sample rate converter without properly programming
2030  * its parameters causes the chip to lock up (the SRC busy bit will
2031  * be stuck high, and I've found no way to rectify this other than
2032  * power cycle) - Thomas Sailer
2033  */
2034  snd_es1371_wait_src_ready(ensoniq);
2035  outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2036  /* try reset codec directly */
2037  outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2038 #endif
2039  outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2040  outb(0x00, ES_REG(ensoniq, UART_RES));
2041  outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2042  synchronize_irq(ensoniq->irq);
2043 }
2044 
2045 #ifdef CONFIG_PM_SLEEP
2046 static int snd_ensoniq_suspend(struct device *dev)
2047 {
2048  struct pci_dev *pci = to_pci_dev(dev);
2049  struct snd_card *card = dev_get_drvdata(dev);
2050  struct ensoniq *ensoniq = card->private_data;
2051 
2053 
2054  snd_pcm_suspend_all(ensoniq->pcm1);
2055  snd_pcm_suspend_all(ensoniq->pcm2);
2056 
2057 #ifdef CHIP1371
2058  snd_ac97_suspend(ensoniq->u.es1371.ac97);
2059 #else
2060  /* try to reset AK4531 */
2061  outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2062  inw(ES_REG(ensoniq, 1370_CODEC));
2063  udelay(100);
2064  outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2065  inw(ES_REG(ensoniq, 1370_CODEC));
2066  udelay(100);
2067  snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2068 #endif
2069 
2070  pci_disable_device(pci);
2071  pci_save_state(pci);
2073  return 0;
2074 }
2075 
2076 static int snd_ensoniq_resume(struct device *dev)
2077 {
2078  struct pci_dev *pci = to_pci_dev(dev);
2079  struct snd_card *card = dev_get_drvdata(dev);
2080  struct ensoniq *ensoniq = card->private_data;
2081 
2083  pci_restore_state(pci);
2084  if (pci_enable_device(pci) < 0) {
2085  printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2086  "disabling device\n");
2087  snd_card_disconnect(card);
2088  return -EIO;
2089  }
2090  pci_set_master(pci);
2091 
2092  snd_ensoniq_chip_init(ensoniq);
2093 
2094 #ifdef CHIP1371
2095  snd_ac97_resume(ensoniq->u.es1371.ac97);
2096 #else
2097  snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2098 #endif
2100  return 0;
2101 }
2102 
2103 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
2104 #define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm
2105 #else
2106 #define SND_ENSONIQ_PM_OPS NULL
2107 #endif /* CONFIG_PM_SLEEP */
2108 
2109 static int __devinit snd_ensoniq_create(struct snd_card *card,
2110  struct pci_dev *pci,
2111  struct ensoniq ** rensoniq)
2112 {
2113  struct ensoniq *ensoniq;
2114  int err;
2115  static struct snd_device_ops ops = {
2116  .dev_free = snd_ensoniq_dev_free,
2117  };
2118 
2119  *rensoniq = NULL;
2120  if ((err = pci_enable_device(pci)) < 0)
2121  return err;
2122  ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2123  if (ensoniq == NULL) {
2124  pci_disable_device(pci);
2125  return -ENOMEM;
2126  }
2127  spin_lock_init(&ensoniq->reg_lock);
2128  mutex_init(&ensoniq->src_mutex);
2129  ensoniq->card = card;
2130  ensoniq->pci = pci;
2131  ensoniq->irq = -1;
2132  if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2133  kfree(ensoniq);
2134  pci_disable_device(pci);
2135  return err;
2136  }
2137  ensoniq->port = pci_resource_start(pci, 0);
2138  if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2139  KBUILD_MODNAME, ensoniq)) {
2140  snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2141  snd_ensoniq_free(ensoniq);
2142  return -EBUSY;
2143  }
2144  ensoniq->irq = pci->irq;
2145 #ifdef CHIP1370
2147  16, &ensoniq->dma_bug) < 0) {
2148  snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2149  snd_ensoniq_free(ensoniq);
2150  return -EBUSY;
2151  }
2152 #endif
2153  pci_set_master(pci);
2154  ensoniq->rev = pci->revision;
2155 #ifdef CHIP1370
2156 #if 0
2159 #else /* get microphone working */
2161 #endif
2162  ensoniq->sctrl = 0;
2163 #else
2164  ensoniq->ctrl = 0;
2165  ensoniq->sctrl = 0;
2166  ensoniq->cssr = 0;
2167  if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2168  ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2169 
2170  if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2171  ensoniq->cssr |= ES_1371_ST_AC97_RST;
2172 #endif
2173 
2174  snd_ensoniq_chip_init(ensoniq);
2175 
2176  if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2177  snd_ensoniq_free(ensoniq);
2178  return err;
2179  }
2180 
2181  snd_ensoniq_proc_init(ensoniq);
2182 
2183  snd_card_set_dev(card, &pci->dev);
2184 
2185  *rensoniq = ensoniq;
2186  return 0;
2187 }
2188 
2189 /*
2190  * MIDI section
2191  */
2192 
2193 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2194 {
2195  struct snd_rawmidi *rmidi = ensoniq->rmidi;
2196  unsigned char status, mask, byte;
2197 
2198  if (rmidi == NULL)
2199  return;
2200  /* do Rx at first */
2201  spin_lock(&ensoniq->reg_lock);
2202  mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2203  while (mask) {
2204  status = inb(ES_REG(ensoniq, UART_STATUS));
2205  if ((status & mask) == 0)
2206  break;
2207  byte = inb(ES_REG(ensoniq, UART_DATA));
2208  snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2209  }
2210  spin_unlock(&ensoniq->reg_lock);
2211 
2212  /* do Tx at second */
2213  spin_lock(&ensoniq->reg_lock);
2214  mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2215  while (mask) {
2216  status = inb(ES_REG(ensoniq, UART_STATUS));
2217  if ((status & mask) == 0)
2218  break;
2219  if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2220  ensoniq->uartc &= ~ES_TXINTENM;
2221  outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2222  mask &= ~ES_TXRDY;
2223  } else {
2224  outb(byte, ES_REG(ensoniq, UART_DATA));
2225  }
2226  }
2227  spin_unlock(&ensoniq->reg_lock);
2228 }
2229 
2230 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2231 {
2232  struct ensoniq *ensoniq = substream->rmidi->private_data;
2233 
2234  spin_lock_irq(&ensoniq->reg_lock);
2235  ensoniq->uartm |= ES_MODE_INPUT;
2236  ensoniq->midi_input = substream;
2237  if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2238  outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2239  outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2240  outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2241  }
2242  spin_unlock_irq(&ensoniq->reg_lock);
2243  return 0;
2244 }
2245 
2246 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2247 {
2248  struct ensoniq *ensoniq = substream->rmidi->private_data;
2249 
2250  spin_lock_irq(&ensoniq->reg_lock);
2251  if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2252  outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2253  outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2254  } else {
2255  outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2256  }
2257  ensoniq->midi_input = NULL;
2258  ensoniq->uartm &= ~ES_MODE_INPUT;
2259  spin_unlock_irq(&ensoniq->reg_lock);
2260  return 0;
2261 }
2262 
2263 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2264 {
2265  struct ensoniq *ensoniq = substream->rmidi->private_data;
2266 
2267  spin_lock_irq(&ensoniq->reg_lock);
2268  ensoniq->uartm |= ES_MODE_OUTPUT;
2269  ensoniq->midi_output = substream;
2270  if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2271  outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2272  outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2273  outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2274  }
2275  spin_unlock_irq(&ensoniq->reg_lock);
2276  return 0;
2277 }
2278 
2279 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2280 {
2281  struct ensoniq *ensoniq = substream->rmidi->private_data;
2282 
2283  spin_lock_irq(&ensoniq->reg_lock);
2284  if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2285  outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2286  outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2287  } else {
2288  outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2289  }
2290  ensoniq->midi_output = NULL;
2291  ensoniq->uartm &= ~ES_MODE_OUTPUT;
2292  spin_unlock_irq(&ensoniq->reg_lock);
2293  return 0;
2294 }
2295 
2296 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2297 {
2298  unsigned long flags;
2299  struct ensoniq *ensoniq = substream->rmidi->private_data;
2300  int idx;
2301 
2302  spin_lock_irqsave(&ensoniq->reg_lock, flags);
2303  if (up) {
2304  if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2305  /* empty input FIFO */
2306  for (idx = 0; idx < 32; idx++)
2307  inb(ES_REG(ensoniq, UART_DATA));
2308  ensoniq->uartc |= ES_RXINTEN;
2309  outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2310  }
2311  } else {
2312  if (ensoniq->uartc & ES_RXINTEN) {
2313  ensoniq->uartc &= ~ES_RXINTEN;
2314  outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2315  }
2316  }
2317  spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2318 }
2319 
2320 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2321 {
2322  unsigned long flags;
2323  struct ensoniq *ensoniq = substream->rmidi->private_data;
2324  unsigned char byte;
2325 
2326  spin_lock_irqsave(&ensoniq->reg_lock, flags);
2327  if (up) {
2328  if (ES_TXINTENI(ensoniq->uartc) == 0) {
2329  ensoniq->uartc |= ES_TXINTENO(1);
2330  /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2331  while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2332  (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2333  if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2334  ensoniq->uartc &= ~ES_TXINTENM;
2335  } else {
2336  outb(byte, ES_REG(ensoniq, UART_DATA));
2337  }
2338  }
2339  outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2340  }
2341  } else {
2342  if (ES_TXINTENI(ensoniq->uartc) == 1) {
2343  ensoniq->uartc &= ~ES_TXINTENM;
2344  outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2345  }
2346  }
2347  spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2348 }
2349 
2350 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2351 {
2352  .open = snd_ensoniq_midi_output_open,
2353  .close = snd_ensoniq_midi_output_close,
2354  .trigger = snd_ensoniq_midi_output_trigger,
2355 };
2356 
2357 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2358 {
2359  .open = snd_ensoniq_midi_input_open,
2360  .close = snd_ensoniq_midi_input_close,
2361  .trigger = snd_ensoniq_midi_input_trigger,
2362 };
2363 
2364 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2365  struct snd_rawmidi **rrawmidi)
2366 {
2367  struct snd_rawmidi *rmidi;
2368  int err;
2369 
2370  if (rrawmidi)
2371  *rrawmidi = NULL;
2372  if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2373  return err;
2374  strcpy(rmidi->name, CHIP_NAME);
2375  snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2376  snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2379  rmidi->private_data = ensoniq;
2380  ensoniq->rmidi = rmidi;
2381  if (rrawmidi)
2382  *rrawmidi = rmidi;
2383  return 0;
2384 }
2385 
2386 /*
2387  * Interrupt handler
2388  */
2389 
2390 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2391 {
2392  struct ensoniq *ensoniq = dev_id;
2393  unsigned int status, sctrl;
2394 
2395  if (ensoniq == NULL)
2396  return IRQ_NONE;
2397 
2398  status = inl(ES_REG(ensoniq, STATUS));
2399  if (!(status & ES_INTR))
2400  return IRQ_NONE;
2401 
2402  spin_lock(&ensoniq->reg_lock);
2403  sctrl = ensoniq->sctrl;
2404  if (status & ES_DAC1)
2405  sctrl &= ~ES_P1_INT_EN;
2406  if (status & ES_DAC2)
2407  sctrl &= ~ES_P2_INT_EN;
2408  if (status & ES_ADC)
2409  sctrl &= ~ES_R1_INT_EN;
2410  outl(sctrl, ES_REG(ensoniq, SERIAL));
2411  outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2412  spin_unlock(&ensoniq->reg_lock);
2413 
2414  if (status & ES_UART)
2415  snd_ensoniq_midi_interrupt(ensoniq);
2416  if ((status & ES_DAC2) && ensoniq->playback2_substream)
2418  if ((status & ES_ADC) && ensoniq->capture_substream)
2420  if ((status & ES_DAC1) && ensoniq->playback1_substream)
2422  return IRQ_HANDLED;
2423 }
2424 
2425 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2426  const struct pci_device_id *pci_id)
2427 {
2428  static int dev;
2429  struct snd_card *card;
2430  struct ensoniq *ensoniq;
2431  int err, pcm_devs[2];
2432 
2433  if (dev >= SNDRV_CARDS)
2434  return -ENODEV;
2435  if (!enable[dev]) {
2436  dev++;
2437  return -ENOENT;
2438  }
2439 
2440  err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2441  if (err < 0)
2442  return err;
2443 
2444  if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2445  snd_card_free(card);
2446  return err;
2447  }
2448  card->private_data = ensoniq;
2449 
2450  pcm_devs[0] = 0; pcm_devs[1] = 1;
2451 #ifdef CHIP1370
2452  if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2453  snd_card_free(card);
2454  return err;
2455  }
2456 #endif
2457 #ifdef CHIP1371
2458  if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2459  snd_card_free(card);
2460  return err;
2461  }
2462 #endif
2463  if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2464  snd_card_free(card);
2465  return err;
2466  }
2467  if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2468  snd_card_free(card);
2469  return err;
2470  }
2471  if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2472  snd_card_free(card);
2473  return err;
2474  }
2475 
2476  snd_ensoniq_create_gameport(ensoniq, dev);
2477 
2478  strcpy(card->driver, DRIVER_NAME);
2479 
2480  strcpy(card->shortname, "Ensoniq AudioPCI");
2481  sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2482  card->shortname,
2483  card->driver,
2484  ensoniq->port,
2485  ensoniq->irq);
2486 
2487  if ((err = snd_card_register(card)) < 0) {
2488  snd_card_free(card);
2489  return err;
2490  }
2491 
2492  pci_set_drvdata(pci, card);
2493  dev++;
2494  return 0;
2495 }
2496 
2497 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2498 {
2499  snd_card_free(pci_get_drvdata(pci));
2500  pci_set_drvdata(pci, NULL);
2501 }
2502 
2503 static struct pci_driver ens137x_driver = {
2504  .name = KBUILD_MODNAME,
2505  .id_table = snd_audiopci_ids,
2506  .probe = snd_audiopci_probe,
2507  .remove = __devexit_p(snd_audiopci_remove),
2508  .driver = {
2509  .pm = SND_ENSONIQ_PM_OPS,
2510  },
2511 };
2512 
2513 module_pci_driver(ens137x_driver);