err_titan.c File Reference

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <asm/io.h>
#include <asm/core_titan.h>
#include <asm/hwrpb.h>
#include <asm/smp.h>
#include <asm/err_common.h>
#include <asm/err_ev6.h>
#include <asm/irq_regs.h>
#include "err_impl.h"
#include "proto.h"

Go to the source code of this file.

Macros
#define	TITAN__CCHIP_MISC__NXM   (1UL << 28)
#define	TITAN__CCHIP_MISC__NXS__S   (29)
#define	TITAN__CCHIP_MISC__NXS__M   (0x7)
#define	TITAN__PCHIP_SERROR__LOST_UECC   (1UL << 0)
#define	TITAN__PCHIP_SERROR__UECC   (1UL << 1)
#define	TITAN__PCHIP_SERROR__CRE   (1UL << 2)
#define	TITAN__PCHIP_SERROR__NXIO   (1UL << 3)
#define	TITAN__PCHIP_SERROR__LOST_CRE   (1UL << 4)
#define	TITAN__PCHIP_SERROR__ECCMASK
#define	TITAN__PCHIP_SERROR__ERRMASK
#define	TITAN__PCHIP_SERROR__SRC__S   (52)
#define	TITAN__PCHIP_SERROR__SRC__M   (0x3)
#define	TITAN__PCHIP_SERROR__CMD__S   (54)
#define	TITAN__PCHIP_SERROR__CMD__M   (0x3)
#define	TITAN__PCHIP_SERROR__SYN__S   (56)
#define	TITAN__PCHIP_SERROR__SYN__M   (0xff)
#define	TITAN__PCHIP_SERROR__ADDR__S   (15)
#define	TITAN__PCHIP_SERROR__ADDR__M   (0xffffffffUL)
#define	TITAN__PCHIP_PERROR__LOST   (1UL << 0)
#define	TITAN__PCHIP_PERROR__SERR   (1UL << 1)
#define	TITAN__PCHIP_PERROR__PERR   (1UL << 2)
#define	TITAN__PCHIP_PERROR__DCRTO   (1UL << 3)
#define	TITAN__PCHIP_PERROR__SGE   (1UL << 4)
#define	TITAN__PCHIP_PERROR__APE   (1UL << 5)
#define	TITAN__PCHIP_PERROR__TA   (1UL << 6)
#define	TITAN__PCHIP_PERROR__DPE   (1UL << 7)
#define	TITAN__PCHIP_PERROR__NDS   (1UL << 8)
#define	TITAN__PCHIP_PERROR__IPTPR   (1UL << 9)
#define	TITAN__PCHIP_PERROR__IPTPW   (1UL << 10)
#define	TITAN__PCHIP_PERROR__ERRMASK
#define	TITAN__PCHIP_PERROR__DAC   (1UL << 47)
#define	TITAN__PCHIP_PERROR__MWIN   (1UL << 48)
#define	TITAN__PCHIP_PERROR__CMD__S   (52)
#define	TITAN__PCHIP_PERROR__CMD__M   (0x0f)
#define	TITAN__PCHIP_PERROR__ADDR__S   (14)
#define	TITAN__PCHIP_PERROR__ADDR__M   (0x1fffffffful)
#define	TITAN__PCHIP_AGPERROR__LOST   (1UL << 0)
#define	TITAN__PCHIP_AGPERROR__LPQFULL   (1UL << 1)
#define	TITAN__PCHIP_AGPERROR__HPQFULL   (1UL << 2)
#define	TITAN__PCHIP_AGPERROR__RESCMD   (1UL << 3)
#define	TITAN__PCHIP_AGPERROR__IPTE   (1UL << 4)
#define	TITAN__PCHIP_AGPERROR__PTP   (1UL << 5)
#define	TITAN__PCHIP_AGPERROR__NOWINDOW   (1UL << 6)
#define	TITAN__PCHIP_AGPERROR__ERRMASK
#define	TITAN__PCHIP_AGPERROR__DAC   (1UL << 48)
#define	TITAN__PCHIP_AGPERROR__MWIN   (1UL << 49)
#define	TITAN__PCHIP_AGPERROR__FENCE   (1UL << 59)
#define	TITAN__PCHIP_AGPERROR__CMD__S   (50)
#define	TITAN__PCHIP_AGPERROR__CMD__M   (0x07)
#define	TITAN__PCHIP_AGPERROR__ADDR__S   (15)
#define	TITAN__PCHIP_AGPERROR__ADDR__M   (0xffffffffUL)
#define	TITAN__PCHIP_AGPERROR__LEN__S   (53)
#define	TITAN__PCHIP_AGPERROR__LEN__M   (0x3f)
#define	TITAN_MCHECK_INTERRUPT_MASK   0xF800000000000000UL
#define	PRIVATEER_MCHK__CORR_ECC   0x86 /* 630 */
#define	PRIVATEER_MCHK__DC_TAG_PERR   0x9E /* 630 */
#define	PRIVATEER_MCHK__PAL_BUGCHECK   0x8E /* 670 */
#define	PRIVATEER_MCHK__OS_BUGCHECK   0x90 /* 670 */
#define	PRIVATEER_MCHK__PROC_HRD_ERR   0x98 /* 670 */
#define	PRIVATEER_MCHK__ISTREAM_CMOV_PRX   0xA0 /* 670 */
#define	PRIVATEER_MCHK__ISTREAM_CMOV_FLT   0xA2 /* 670 */
#define	PRIVATEER_MCHK__SYS_HRD_ERR   0x202 /* 660 */
#define	PRIVATEER_MCHK__SYS_CORR_ERR   0x204 /* 620 */
#define	PRIVATEER_MCHK__SYS_ENVIRON   0x206 /* 680 */
#define	PRIVATEER_680_INTERRUPT_MASK   (0xE00UL)
#define	PRIVATEER_HOTPLUG_INTERRUPT_MASK   (0xE00UL)

Functions
int	titan_process_logout_frame (struct el_common *mchk_header, int print)
void	titan_machine_check (unsigned long vector, unsigned long la_ptr)
void __init	titan_register_error_handlers (void)
int	privateer_process_logout_frame (struct el_common *mchk_header, int print)
void	privateer_machine_check (unsigned long vector, unsigned long la_ptr)

Macro Definition Documentation

#define PRIVATEER_680_INTERRUPT_MASK   (0xE00UL)

#define PRIVATEER_HOTPLUG_INTERRUPT_MASK   (0xE00UL)

#define PRIVATEER_MCHK__CORR_ECC   0x86 /* 630 */

#define PRIVATEER_MCHK__DC_TAG_PERR   0x9E /* 630 */

#define PRIVATEER_MCHK__ISTREAM_CMOV_FLT   0xA2 /* 670 */

#define PRIVATEER_MCHK__ISTREAM_CMOV_PRX   0xA0 /* 670 */

#define PRIVATEER_MCHK__OS_BUGCHECK   0x90 /* 670 */

#define PRIVATEER_MCHK__PAL_BUGCHECK   0x8E /* 670 */

#define PRIVATEER_MCHK__PROC_HRD_ERR   0x98 /* 670 */

#define PRIVATEER_MCHK__SYS_CORR_ERR   0x204 /* 620 */

#define PRIVATEER_MCHK__SYS_ENVIRON   0x206 /* 680 */

#define PRIVATEER_MCHK__SYS_HRD_ERR   0x202 /* 660 */

#define TITAN__CCHIP_MISC__NXM   (1UL << 28)

#define TITAN__CCHIP_MISC__NXS__M   (0x7)

#define TITAN__CCHIP_MISC__NXS__S   (29)

#define TITAN__PCHIP_AGPERROR__ADDR__M   (0xffffffffUL)

#define TITAN__PCHIP_AGPERROR__ADDR__S   (15)

#define TITAN__PCHIP_AGPERROR__CMD__M   (0x07)

#define TITAN__PCHIP_AGPERROR__CMD__S   (50)

#define TITAN__PCHIP_AGPERROR__DAC   (1UL << 48)

#define TITAN__PCHIP_AGPERROR__ERRMASK

Value:

(TITAN__PCHIP_AGPERROR__LOST |    \
                     TITAN__PCHIP_AGPERROR__LPQFULL | \
                     TITAN__PCHIP_AGPERROR__HPQFULL | \
                     TITAN__PCHIP_AGPERROR__RESCMD |  \
                     TITAN__PCHIP_AGPERROR__IPTE |    \
                     TITAN__PCHIP_AGPERROR__PTP |     \
                     TITAN__PCHIP_AGPERROR__NOWINDOW)

#define TITAN__PCHIP_AGPERROR__FENCE   (1UL << 59)

#define TITAN__PCHIP_AGPERROR__HPQFULL   (1UL << 2)

#define TITAN__PCHIP_AGPERROR__IPTE   (1UL << 4)

#define TITAN__PCHIP_AGPERROR__LEN__M   (0x3f)

#define TITAN__PCHIP_AGPERROR__LEN__S   (53)

#define TITAN__PCHIP_AGPERROR__LOST   (1UL << 0)

#define TITAN__PCHIP_AGPERROR__LPQFULL   (1UL << 1)

#define TITAN__PCHIP_AGPERROR__MWIN   (1UL << 49)

#define TITAN__PCHIP_AGPERROR__NOWINDOW   (1UL << 6)

#define TITAN__PCHIP_AGPERROR__PTP   (1UL << 5)

#define TITAN__PCHIP_AGPERROR__RESCMD   (1UL << 3)

#define TITAN__PCHIP_PERROR__ADDR__M   (0x1fffffffful)

#define TITAN__PCHIP_PERROR__ADDR__S   (14)

#define TITAN__PCHIP_PERROR__APE   (1UL << 5)

#define TITAN__PCHIP_PERROR__CMD__M   (0x0f)

#define TITAN__PCHIP_PERROR__CMD__S   (52)

#define TITAN__PCHIP_PERROR__DAC   (1UL << 47)

#define TITAN__PCHIP_PERROR__DCRTO   (1UL << 3)

#define TITAN__PCHIP_PERROR__DPE   (1UL << 7)

#define TITAN__PCHIP_PERROR__ERRMASK

Value:

(TITAN__PCHIP_PERROR__LOST |    \
                     TITAN__PCHIP_PERROR__SERR |    \
                     TITAN__PCHIP_PERROR__PERR |    \
                     TITAN__PCHIP_PERROR__DCRTO |   \
                     TITAN__PCHIP_PERROR__SGE | \
                     TITAN__PCHIP_PERROR__APE | \
                     TITAN__PCHIP_PERROR__TA |  \
                     TITAN__PCHIP_PERROR__DPE | \
                     TITAN__PCHIP_PERROR__NDS | \
                     TITAN__PCHIP_PERROR__IPTPR |   \
                     TITAN__PCHIP_PERROR__IPTPW)

#define TITAN__PCHIP_PERROR__IPTPR   (1UL << 9)

#define TITAN__PCHIP_PERROR__IPTPW   (1UL << 10)

#define TITAN__PCHIP_PERROR__LOST   (1UL << 0)

#define TITAN__PCHIP_PERROR__MWIN   (1UL << 48)

#define TITAN__PCHIP_PERROR__NDS   (1UL << 8)

#define TITAN__PCHIP_PERROR__PERR   (1UL << 2)

#define TITAN__PCHIP_PERROR__SERR   (1UL << 1)

#define TITAN__PCHIP_PERROR__SGE   (1UL << 4)

#define TITAN__PCHIP_PERROR__TA   (1UL << 6)

#define TITAN__PCHIP_SERROR__ADDR__M   (0xffffffffUL)

#define TITAN__PCHIP_SERROR__ADDR__S   (15)

#define TITAN__PCHIP_SERROR__CMD__M   (0x3)

#define TITAN__PCHIP_SERROR__CMD__S   (54)

#define TITAN__PCHIP_SERROR__CRE   (1UL << 2)

#define TITAN__PCHIP_SERROR__ECCMASK

Value:

(TITAN__PCHIP_SERROR__UECC |      \
                     TITAN__PCHIP_SERROR__CRE)

#define TITAN__PCHIP_SERROR__ERRMASK

Value:

(TITAN__PCHIP_SERROR__LOST_UECC | \
                     TITAN__PCHIP_SERROR__UECC |      \
                     TITAN__PCHIP_SERROR__CRE |   \
                     TITAN__PCHIP_SERROR__NXIO |      \
                     TITAN__PCHIP_SERROR__LOST_CRE)

#define TITAN__PCHIP_SERROR__LOST_CRE   (1UL << 4)

#define TITAN__PCHIP_SERROR__LOST_UECC   (1UL << 0)

#define TITAN__PCHIP_SERROR__NXIO   (1UL << 3)

#define TITAN__PCHIP_SERROR__SRC__M   (0x3)

#define TITAN__PCHIP_SERROR__SRC__S   (52)

#define TITAN__PCHIP_SERROR__SYN__M   (0xff)

#define TITAN__PCHIP_SERROR__SYN__S   (56)

#define TITAN__PCHIP_SERROR__UECC   (1UL << 1)

#define TITAN_MCHECK_INTERRUPT_MASK   0xF800000000000000UL

Function Documentation

void privateer_machine_check	(	unsigned long	vector,
		unsigned long	la_ptr
	)

Definition at line 708 of file err_titan.c.

int privateer_process_logout_frame	(	struct el_common *	mchk_header,
		int	print
	)

Definition at line 630 of file err_titan.c.

void titan_machine_check	(	unsigned long	vector,
		unsigned long	la_ptr
	)

Definition at line 388 of file err_titan.c.

int titan_process_logout_frame	(	struct el_common *	mchk_header,
		int	print
	)

Definition at line 369 of file err_titan.c.

void __init titan_register_error_handlers

(

void

)

Definition at line 571 of file err_titan.c.