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fsl_ifc_nand.c
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1 /*
2  * Freescale Integrated Flash Controller NAND driver
3  *
4  * Copyright 2011-2012 Freescale Semiconductor, Inc
5  *
6  * Author: Dipen Dudhat <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <asm/fsl_ifc.h>
33 
34 #define FSL_IFC_V1_1_0 0x01010000
35 #define ERR_BYTE 0xFF /* Value returned for read
36  bytes when read failed */
37 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
38  for IFC NAND Machine */
39 
40 struct fsl_ifc_ctrl;
41 
42 /* mtd information per set */
43 struct fsl_ifc_mtd {
44  struct mtd_info mtd;
45  struct nand_chip chip;
46  struct fsl_ifc_ctrl *ctrl;
47 
48  struct device *dev;
49  int bank; /* Chip select bank number */
50  unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
51  u8 __iomem *vbase; /* Chip select base virtual address */
52 };
53 
54 /* overview of the fsl ifc controller */
55 struct fsl_ifc_nand_ctrl {
56  struct nand_hw_control controller;
57  struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
58 
59  u8 __iomem *addr; /* Address of assigned IFC buffer */
60  unsigned int page; /* Last page written to / read from */
61  unsigned int read_bytes;/* Number of bytes read during command */
62  unsigned int column; /* Saved column from SEQIN */
63  unsigned int index; /* Pointer to next byte to 'read' */
64  unsigned int oob; /* Non zero if operating on OOB data */
65  unsigned int eccread; /* Non zero for a full-page ECC read */
66  unsigned int counter; /* counter for the initializations */
67  unsigned int max_bitflips; /* Saved during READ0 cmd */
68 };
69 
70 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
71 
72 /* 512-byte page with 4-bit ECC, 8-bit */
73 static struct nand_ecclayout oob_512_8bit_ecc4 = {
74  .eccbytes = 8,
75  .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
76  .oobfree = { {0, 5}, {6, 2} },
77 };
78 
79 /* 512-byte page with 4-bit ECC, 16-bit */
80 static struct nand_ecclayout oob_512_16bit_ecc4 = {
81  .eccbytes = 8,
82  .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
83  .oobfree = { {2, 6}, },
84 };
85 
86 /* 2048-byte page size with 4-bit ECC */
87 static struct nand_ecclayout oob_2048_ecc4 = {
88  .eccbytes = 32,
89  .eccpos = {
90  8, 9, 10, 11, 12, 13, 14, 15,
91  16, 17, 18, 19, 20, 21, 22, 23,
92  24, 25, 26, 27, 28, 29, 30, 31,
93  32, 33, 34, 35, 36, 37, 38, 39,
94  },
95  .oobfree = { {2, 6}, {40, 24} },
96 };
97 
98 /* 4096-byte page size with 4-bit ECC */
99 static struct nand_ecclayout oob_4096_ecc4 = {
100  .eccbytes = 64,
101  .eccpos = {
102  8, 9, 10, 11, 12, 13, 14, 15,
103  16, 17, 18, 19, 20, 21, 22, 23,
104  24, 25, 26, 27, 28, 29, 30, 31,
105  32, 33, 34, 35, 36, 37, 38, 39,
106  40, 41, 42, 43, 44, 45, 46, 47,
107  48, 49, 50, 51, 52, 53, 54, 55,
108  56, 57, 58, 59, 60, 61, 62, 63,
109  64, 65, 66, 67, 68, 69, 70, 71,
110  },
111  .oobfree = { {2, 6}, {72, 56} },
112 };
113 
114 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
115 static struct nand_ecclayout oob_4096_ecc8 = {
116  .eccbytes = 128,
117  .eccpos = {
118  8, 9, 10, 11, 12, 13, 14, 15,
119  16, 17, 18, 19, 20, 21, 22, 23,
120  24, 25, 26, 27, 28, 29, 30, 31,
121  32, 33, 34, 35, 36, 37, 38, 39,
122  40, 41, 42, 43, 44, 45, 46, 47,
123  48, 49, 50, 51, 52, 53, 54, 55,
124  56, 57, 58, 59, 60, 61, 62, 63,
125  64, 65, 66, 67, 68, 69, 70, 71,
126  72, 73, 74, 75, 76, 77, 78, 79,
127  80, 81, 82, 83, 84, 85, 86, 87,
128  88, 89, 90, 91, 92, 93, 94, 95,
129  96, 97, 98, 99, 100, 101, 102, 103,
130  104, 105, 106, 107, 108, 109, 110, 111,
131  112, 113, 114, 115, 116, 117, 118, 119,
132  120, 121, 122, 123, 124, 125, 126, 127,
133  128, 129, 130, 131, 132, 133, 134, 135,
134  },
135  .oobfree = { {2, 6}, {136, 82} },
136 };
137 
138 
139 /*
140  * Generic flash bbt descriptors
141  */
142 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
143 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
144 
145 static struct nand_bbt_descr bbt_main_descr = {
146  .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
147  NAND_BBT_2BIT | NAND_BBT_VERSION,
148  .offs = 2, /* 0 on 8-bit small page */
149  .len = 4,
150  .veroffs = 6,
151  .maxblocks = 4,
152  .pattern = bbt_pattern,
153 };
154 
155 static struct nand_bbt_descr bbt_mirror_descr = {
156  .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
157  NAND_BBT_2BIT | NAND_BBT_VERSION,
158  .offs = 2, /* 0 on 8-bit small page */
159  .len = 4,
160  .veroffs = 6,
161  .maxblocks = 4,
162  .pattern = mirror_pattern,
163 };
164 
165 /*
166  * Set up the IFC hardware block and page address fields, and the ifc nand
167  * structure addr field to point to the correct IFC buffer in memory
168  */
169 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
170 {
171  struct nand_chip *chip = mtd->priv;
172  struct fsl_ifc_mtd *priv = chip->priv;
173  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
174  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
175  int buf_num;
176 
177  ifc_nand_ctrl->page = page_addr;
178  /* Program ROW0/COL0 */
179  out_be32(&ifc->ifc_nand.row0, page_addr);
180  out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
181 
182  buf_num = page_addr & priv->bufnum_mask;
183 
184  ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
185  ifc_nand_ctrl->index = column;
186 
187  /* for OOB data point to the second half of the buffer */
188  if (oob)
189  ifc_nand_ctrl->index += mtd->writesize;
190 }
191 
192 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
193 {
194  struct nand_chip *chip = mtd->priv;
195  struct fsl_ifc_mtd *priv = chip->priv;
196  u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
197  u32 __iomem *mainarea = (u32 __iomem *)addr;
198  u8 __iomem *oob = addr + mtd->writesize;
199  int i;
200 
201  for (i = 0; i < mtd->writesize / 4; i++) {
202  if (__raw_readl(&mainarea[i]) != 0xffffffff)
203  return 0;
204  }
205 
206  for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
207  int pos = chip->ecc.layout->eccpos[i];
208 
209  if (__raw_readb(&oob[pos]) != 0xff)
210  return 0;
211  }
212 
213  return 1;
214 }
215 
216 /* returns nonzero if entire page is blank */
217 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
218  u32 *eccstat, unsigned int bufnum)
219 {
220  u32 reg = eccstat[bufnum / 4];
221  int errors;
222 
223  errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
224 
225  return errors;
226 }
227 
228 /*
229  * execute IFC NAND command and wait for it to complete
230  */
231 static void fsl_ifc_run_command(struct mtd_info *mtd)
232 {
233  struct nand_chip *chip = mtd->priv;
234  struct fsl_ifc_mtd *priv = chip->priv;
235  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
236  struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
237  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
238  u32 eccstat[4];
239  int i;
240 
241  /* set the chip select for NAND Transaction */
242  out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
243 
244  dev_vdbg(priv->dev,
245  "%s: fir0=%08x fcr0=%08x\n",
246  __func__,
247  in_be32(&ifc->ifc_nand.nand_fir0),
248  in_be32(&ifc->ifc_nand.nand_fcr0));
249 
250  ctrl->nand_stat = 0;
251 
252  /* start read/write seq */
253  out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
254 
255  /* wait for command complete flag or timeout */
256  wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
257  IFC_TIMEOUT_MSECS * HZ/1000);
258 
259  /* ctrl->nand_stat will be updated from IRQ context */
260  if (!ctrl->nand_stat)
261  dev_err(priv->dev, "Controller is not responding\n");
262  if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
263  dev_err(priv->dev, "NAND Flash Timeout Error\n");
264  if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
265  dev_err(priv->dev, "NAND Flash Write Protect Error\n");
266 
267  nctrl->max_bitflips = 0;
268 
269  if (nctrl->eccread) {
270  int errors;
271  int bufnum = nctrl->page & priv->bufnum_mask;
272  int sector = bufnum * chip->ecc.steps;
273  int sector_end = sector + chip->ecc.steps - 1;
274 
275  for (i = sector / 4; i <= sector_end / 4; i++)
276  eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
277 
278  for (i = sector; i <= sector_end; i++) {
279  errors = check_read_ecc(mtd, ctrl, eccstat, i);
280 
281  if (errors == 15) {
282  /*
283  * Uncorrectable error.
284  * OK only if the whole page is blank.
285  *
286  * We disable ECCER reporting due to...
287  * erratum IFC-A002770 -- so report it now if we
288  * see an uncorrectable error in ECCSTAT.
289  */
290  if (!is_blank(mtd, bufnum))
291  ctrl->nand_stat |=
292  IFC_NAND_EVTER_STAT_ECCER;
293  break;
294  }
295 
296  mtd->ecc_stats.corrected += errors;
297  nctrl->max_bitflips = max_t(unsigned int,
298  nctrl->max_bitflips,
299  errors);
300  }
301 
302  nctrl->eccread = 0;
303  }
304 }
305 
306 static void fsl_ifc_do_read(struct nand_chip *chip,
307  int oob,
308  struct mtd_info *mtd)
309 {
310  struct fsl_ifc_mtd *priv = chip->priv;
311  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
312  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
313 
314  /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
315  if (mtd->writesize > 512) {
316  out_be32(&ifc->ifc_nand.nand_fir0,
317  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
321  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
322  out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
323 
324  out_be32(&ifc->ifc_nand.nand_fcr0,
325  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
326  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
327  } else {
328  out_be32(&ifc->ifc_nand.nand_fir0,
329  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
330  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
331  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
332  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
333  out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
334 
335  if (oob)
336  out_be32(&ifc->ifc_nand.nand_fcr0,
337  NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
338  else
339  out_be32(&ifc->ifc_nand.nand_fcr0,
340  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
341  }
342 }
343 
344 /* cmdfunc send commands to the IFC NAND Machine */
345 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
346  int column, int page_addr) {
347  struct nand_chip *chip = mtd->priv;
348  struct fsl_ifc_mtd *priv = chip->priv;
349  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
350  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
351 
352  /* clear the read buffer */
353  ifc_nand_ctrl->read_bytes = 0;
354  if (command != NAND_CMD_PAGEPROG)
355  ifc_nand_ctrl->index = 0;
356 
357  switch (command) {
358  /* READ0 read the entire buffer to use hardware ECC. */
359  case NAND_CMD_READ0:
360  out_be32(&ifc->ifc_nand.nand_fbcr, 0);
361  set_addr(mtd, 0, page_addr, 0);
362 
363  ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
364  ifc_nand_ctrl->index += column;
365 
366  if (chip->ecc.mode == NAND_ECC_HW)
367  ifc_nand_ctrl->eccread = 1;
368 
369  fsl_ifc_do_read(chip, 0, mtd);
370  fsl_ifc_run_command(mtd);
371  return;
372 
373  /* READOOB reads only the OOB because no ECC is performed. */
374  case NAND_CMD_READOOB:
375  out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
376  set_addr(mtd, column, page_addr, 1);
377 
378  ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
379 
380  fsl_ifc_do_read(chip, 1, mtd);
381  fsl_ifc_run_command(mtd);
382 
383  return;
384 
385  case NAND_CMD_READID:
386  case NAND_CMD_PARAM: {
387  int timing = IFC_FIR_OP_RB;
388  if (command == NAND_CMD_PARAM)
389  timing = IFC_FIR_OP_RBCD;
390 
391  out_be32(&ifc->ifc_nand.nand_fir0,
392  (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
393  (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
394  (timing << IFC_NAND_FIR0_OP2_SHIFT));
395  out_be32(&ifc->ifc_nand.nand_fcr0,
396  command << IFC_NAND_FCR0_CMD0_SHIFT);
397  out_be32(&ifc->ifc_nand.row3, column);
398 
399  /*
400  * although currently it's 8 bytes for READID, we always read
401  * the maximum 256 bytes(for PARAM)
402  */
403  out_be32(&ifc->ifc_nand.nand_fbcr, 256);
404  ifc_nand_ctrl->read_bytes = 256;
405 
406  set_addr(mtd, 0, 0, 0);
407  fsl_ifc_run_command(mtd);
408  return;
409  }
410 
411  /* ERASE1 stores the block and page address */
412  case NAND_CMD_ERASE1:
413  set_addr(mtd, 0, page_addr, 0);
414  return;
415 
416  /* ERASE2 uses the block and page address from ERASE1 */
417  case NAND_CMD_ERASE2:
418  out_be32(&ifc->ifc_nand.nand_fir0,
419  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
420  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
421  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
422 
423  out_be32(&ifc->ifc_nand.nand_fcr0,
424  (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
425  (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
426 
427  out_be32(&ifc->ifc_nand.nand_fbcr, 0);
428  ifc_nand_ctrl->read_bytes = 0;
429  fsl_ifc_run_command(mtd);
430  return;
431 
432  /* SEQIN sets up the addr buffer and all registers except the length */
433  case NAND_CMD_SEQIN: {
434  u32 nand_fcr0;
435  ifc_nand_ctrl->column = column;
436  ifc_nand_ctrl->oob = 0;
437 
438  if (mtd->writesize > 512) {
439  nand_fcr0 =
440  (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
441  (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
442 
443  out_be32(&ifc->ifc_nand.nand_fir0,
444  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
445  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
446  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
447  (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
448  (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
449  } else {
450  nand_fcr0 = ((NAND_CMD_PAGEPROG <<
451  IFC_NAND_FCR0_CMD1_SHIFT) |
452  (NAND_CMD_SEQIN <<
453  IFC_NAND_FCR0_CMD2_SHIFT));
454 
455  out_be32(&ifc->ifc_nand.nand_fir0,
456  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
457  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
458  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
459  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
460  (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
461  out_be32(&ifc->ifc_nand.nand_fir1,
462  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
463 
464  if (column >= mtd->writesize)
465  nand_fcr0 |=
466  NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
467  else
468  nand_fcr0 |=
469  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
470  }
471 
472  if (column >= mtd->writesize) {
473  /* OOB area --> READOOB */
474  column -= mtd->writesize;
475  ifc_nand_ctrl->oob = 1;
476  }
477  out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
478  set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
479  return;
480  }
481 
482  /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
483  case NAND_CMD_PAGEPROG: {
484  if (ifc_nand_ctrl->oob) {
485  out_be32(&ifc->ifc_nand.nand_fbcr,
486  ifc_nand_ctrl->index - ifc_nand_ctrl->column);
487  } else {
488  out_be32(&ifc->ifc_nand.nand_fbcr, 0);
489  }
490 
491  fsl_ifc_run_command(mtd);
492  return;
493  }
494 
495  case NAND_CMD_STATUS:
496  out_be32(&ifc->ifc_nand.nand_fir0,
497  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499  out_be32(&ifc->ifc_nand.nand_fcr0,
500  NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501  out_be32(&ifc->ifc_nand.nand_fbcr, 1);
502  set_addr(mtd, 0, 0, 0);
503  ifc_nand_ctrl->read_bytes = 1;
504 
505  fsl_ifc_run_command(mtd);
506 
507  /*
508  * The chip always seems to report that it is
509  * write-protected, even when it is not.
510  */
511  setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
512  return;
513 
514  case NAND_CMD_RESET:
515  out_be32(&ifc->ifc_nand.nand_fir0,
516  IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
517  out_be32(&ifc->ifc_nand.nand_fcr0,
518  NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
519  fsl_ifc_run_command(mtd);
520  return;
521 
522  default:
523  dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
524  __func__, command);
525  }
526 }
527 
528 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
529 {
530  /* The hardware does not seem to support multiple
531  * chips per bank.
532  */
533 }
534 
535 /*
536  * Write buf to the IFC NAND Controller Data Buffer
537  */
538 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
539 {
540  struct nand_chip *chip = mtd->priv;
541  struct fsl_ifc_mtd *priv = chip->priv;
542  unsigned int bufsize = mtd->writesize + mtd->oobsize;
543 
544  if (len <= 0) {
545  dev_err(priv->dev, "%s: len %d bytes", __func__, len);
546  return;
547  }
548 
549  if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
550  dev_err(priv->dev,
551  "%s: beyond end of buffer (%d requested, %u available)\n",
552  __func__, len, bufsize - ifc_nand_ctrl->index);
553  len = bufsize - ifc_nand_ctrl->index;
554  }
555 
556  memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
557  ifc_nand_ctrl->index += len;
558 }
559 
560 /*
561  * Read a byte from either the IFC hardware buffer
562  * read function for 8-bit buswidth
563  */
564 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
565 {
566  struct nand_chip *chip = mtd->priv;
567  struct fsl_ifc_mtd *priv = chip->priv;
568 
569  /*
570  * If there are still bytes in the IFC buffer, then use the
571  * next byte.
572  */
573  if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
574  return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
575 
576  dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
577  return ERR_BYTE;
578 }
579 
580 /*
581  * Read two bytes from the IFC hardware buffer
582  * read function for 16-bit buswith
583  */
584 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
585 {
586  struct nand_chip *chip = mtd->priv;
587  struct fsl_ifc_mtd *priv = chip->priv;
588  uint16_t data;
589 
590  /*
591  * If there are still bytes in the IFC buffer, then use the
592  * next byte.
593  */
594  if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
595  data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
596  addr[ifc_nand_ctrl->index]);
597  ifc_nand_ctrl->index += 2;
598  return (uint8_t) data;
599  }
600 
601  dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
602  return ERR_BYTE;
603 }
604 
605 /*
606  * Read from the IFC Controller Data Buffer
607  */
608 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
609 {
610  struct nand_chip *chip = mtd->priv;
611  struct fsl_ifc_mtd *priv = chip->priv;
612  int avail;
613 
614  if (len < 0) {
615  dev_err(priv->dev, "%s: len %d bytes", __func__, len);
616  return;
617  }
618 
619  avail = min((unsigned int)len,
620  ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
621  memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
622  ifc_nand_ctrl->index += avail;
623 
624  if (len > avail)
625  dev_err(priv->dev,
626  "%s: beyond end of buffer (%d requested, %d available)\n",
627  __func__, len, avail);
628 }
629 
630 /*
631  * This function is called after Program and Erase Operations to
632  * check for success or failure.
633  */
634 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
635 {
636  struct fsl_ifc_mtd *priv = chip->priv;
637  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
638  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
639  u32 nand_fsr;
640 
641  /* Use READ_STATUS command, but wait for the device to be ready */
642  out_be32(&ifc->ifc_nand.nand_fir0,
643  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
644  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
645  out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
646  IFC_NAND_FCR0_CMD0_SHIFT);
647  out_be32(&ifc->ifc_nand.nand_fbcr, 1);
648  set_addr(mtd, 0, 0, 0);
649  ifc_nand_ctrl->read_bytes = 1;
650 
651  fsl_ifc_run_command(mtd);
652 
653  nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
654 
655  /*
656  * The chip always seems to report that it is
657  * write-protected, even when it is not.
658  */
659  return nand_fsr | NAND_STATUS_WP;
660 }
661 
662 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
663  uint8_t *buf, int oob_required, int page)
664 {
665  struct fsl_ifc_mtd *priv = chip->priv;
666  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
667  struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
668 
669  fsl_ifc_read_buf(mtd, buf, mtd->writesize);
670  if (oob_required)
671  fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
672 
673  if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
674  dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
675 
676  if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
677  mtd->ecc_stats.failed++;
678 
679  return nctrl->max_bitflips;
680 }
681 
682 /* ECC will be calculated automatically, and errors will be detected in
683  * waitfunc.
684  */
685 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
686  const uint8_t *buf, int oob_required)
687 {
688  fsl_ifc_write_buf(mtd, buf, mtd->writesize);
689  fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
690 
691  return 0;
692 }
693 
694 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
695 {
696  struct nand_chip *chip = mtd->priv;
697  struct fsl_ifc_mtd *priv = chip->priv;
698 
699  dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
700  chip->numchips);
701  dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
702  chip->chipsize);
703  dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
704  chip->pagemask);
705  dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
706  chip->chip_delay);
707  dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
708  chip->badblockpos);
709  dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
710  chip->chip_shift);
711  dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
712  chip->page_shift);
713  dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
714  chip->phys_erase_shift);
715  dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
716  chip->ecclayout);
717  dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
718  chip->ecc.mode);
719  dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
720  chip->ecc.steps);
721  dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
722  chip->ecc.bytes);
723  dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
724  chip->ecc.total);
725  dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
726  chip->ecc.layout);
727  dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
728  dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
729  dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
730  mtd->erasesize);
731  dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
732  mtd->writesize);
733  dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
734  mtd->oobsize);
735 
736  return 0;
737 }
738 
739 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
740 {
741  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
742  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
743  uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
744  uint32_t cs = priv->bank;
745 
746  /* Save CSOR and CSOR_ext */
747  csor = in_be32(&ifc->csor_cs[cs].csor);
748  csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext);
749 
750  /* chage PageSize 8K and SpareSize 1K*/
751  csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
752  out_be32(&ifc->csor_cs[cs].csor, csor_8k);
753  out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400);
754 
755  /* READID */
756  out_be32(&ifc->ifc_nand.nand_fir0,
757  (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
758  (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
759  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
760  out_be32(&ifc->ifc_nand.nand_fcr0,
761  NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
762  out_be32(&ifc->ifc_nand.row3, 0x0);
763 
764  out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
765 
766  /* Program ROW0/COL0 */
767  out_be32(&ifc->ifc_nand.row0, 0x0);
768  out_be32(&ifc->ifc_nand.col0, 0x0);
769 
770  /* set the chip select for NAND Transaction */
771  out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT);
772 
773  /* start read seq */
774  out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
775 
776  /* wait for command complete flag or timeout */
777  wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
778  IFC_TIMEOUT_MSECS * HZ/1000);
779 
780  if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
781  printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
782 
783  /* Restore CSOR and CSOR_ext */
784  out_be32(&ifc->csor_cs[cs].csor, csor);
785  out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext);
786 }
787 
788 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
789 {
790  struct fsl_ifc_ctrl *ctrl = priv->ctrl;
791  struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
792  struct nand_chip *chip = &priv->chip;
793  struct nand_ecclayout *layout;
794  u32 csor, ver;
795 
796  /* Fill in fsl_ifc_mtd structure */
797  priv->mtd.priv = chip;
798  priv->mtd.owner = THIS_MODULE;
799 
800  /* fill in nand_chip structure */
801  /* set up function call table */
802  if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
803  chip->read_byte = fsl_ifc_read_byte16;
804  else
805  chip->read_byte = fsl_ifc_read_byte;
806 
807  chip->write_buf = fsl_ifc_write_buf;
808  chip->read_buf = fsl_ifc_read_buf;
809  chip->select_chip = fsl_ifc_select_chip;
810  chip->cmdfunc = fsl_ifc_cmdfunc;
811  chip->waitfunc = fsl_ifc_wait;
812 
813  chip->bbt_td = &bbt_main_descr;
814  chip->bbt_md = &bbt_mirror_descr;
815 
816  out_be32(&ifc->ifc_nand.ncfgr, 0x0);
817 
818  /* set up nand options */
819  chip->bbt_options = NAND_BBT_USE_FLASH;
820 
821 
822  if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
823  chip->read_byte = fsl_ifc_read_byte16;
824  chip->options |= NAND_BUSWIDTH_16;
825  } else {
826  chip->read_byte = fsl_ifc_read_byte;
827  }
828 
829  chip->controller = &ifc_nand_ctrl->controller;
830  chip->priv = priv;
831 
832  chip->ecc.read_page = fsl_ifc_read_page;
833  chip->ecc.write_page = fsl_ifc_write_page;
834 
835  csor = in_be32(&ifc->csor_cs[priv->bank].csor);
836 
837  /* Hardware generates ECC per 512 Bytes */
838  chip->ecc.size = 512;
839  chip->ecc.bytes = 8;
840  chip->ecc.strength = 4;
841 
842  switch (csor & CSOR_NAND_PGS_MASK) {
843  case CSOR_NAND_PGS_512:
844  if (chip->options & NAND_BUSWIDTH_16) {
845  layout = &oob_512_16bit_ecc4;
846  } else {
847  layout = &oob_512_8bit_ecc4;
848 
849  /* Avoid conflict with bad block marker */
850  bbt_main_descr.offs = 0;
851  bbt_mirror_descr.offs = 0;
852  }
853 
854  priv->bufnum_mask = 15;
855  break;
856 
857  case CSOR_NAND_PGS_2K:
858  layout = &oob_2048_ecc4;
859  priv->bufnum_mask = 3;
860  break;
861 
862  case CSOR_NAND_PGS_4K:
863  if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
864  CSOR_NAND_ECC_MODE_4) {
865  layout = &oob_4096_ecc4;
866  } else {
867  layout = &oob_4096_ecc8;
868  chip->ecc.bytes = 16;
869  }
870 
871  priv->bufnum_mask = 1;
872  break;
873 
874  default:
875  dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
876  return -ENODEV;
877  }
878 
879  /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
880  if (csor & CSOR_NAND_ECC_DEC_EN) {
881  chip->ecc.mode = NAND_ECC_HW;
882  chip->ecc.layout = layout;
883  } else {
884  chip->ecc.mode = NAND_ECC_SOFT;
885  }
886 
887  ver = in_be32(&ifc->ifc_rev);
888  if (ver == FSL_IFC_V1_1_0)
889  fsl_ifc_sram_init(priv);
890 
891  return 0;
892 }
893 
894 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
895 {
896  nand_release(&priv->mtd);
897 
898  kfree(priv->mtd.name);
899 
900  if (priv->vbase)
901  iounmap(priv->vbase);
902 
903  ifc_nand_ctrl->chips[priv->bank] = NULL;
904  dev_set_drvdata(priv->dev, NULL);
905  kfree(priv);
906 
907  return 0;
908 }
909 
910 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
911  phys_addr_t addr)
912 {
913  u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
914 
915  if (!(cspr & CSPR_V))
916  return 0;
917  if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
918  return 0;
919 
920  return (cspr & CSPR_BA) == convert_ifc_address(addr);
921 }
922 
923 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
924 
925 static int __devinit fsl_ifc_nand_probe(struct platform_device *dev)
926 {
927  struct fsl_ifc_regs __iomem *ifc;
928  struct fsl_ifc_mtd *priv;
929  struct resource res;
930  static const char *part_probe_types[]
931  = { "cmdlinepart", "RedBoot", "ofpart", NULL };
932  int ret;
933  int bank;
934  struct device_node *node = dev->dev.of_node;
935  struct mtd_part_parser_data ppdata;
936 
937  ppdata.of_node = dev->dev.of_node;
938  if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
939  return -ENODEV;
940  ifc = fsl_ifc_ctrl_dev->regs;
941 
942  /* get, allocate and map the memory resource */
943  ret = of_address_to_resource(node, 0, &res);
944  if (ret) {
945  dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
946  return ret;
947  }
948 
949  /* find which chip select it is connected to */
950  for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
951  if (match_bank(ifc, bank, res.start))
952  break;
953  }
954 
955  if (bank >= FSL_IFC_BANK_COUNT) {
956  dev_err(&dev->dev, "%s: address did not match any chip selects\n",
957  __func__);
958  return -ENODEV;
959  }
960 
961  priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
962  if (!priv)
963  return -ENOMEM;
964 
965  mutex_lock(&fsl_ifc_nand_mutex);
966  if (!fsl_ifc_ctrl_dev->nand) {
967  ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
968  if (!ifc_nand_ctrl) {
969  dev_err(&dev->dev, "failed to allocate memory\n");
970  mutex_unlock(&fsl_ifc_nand_mutex);
971  return -ENOMEM;
972  }
973 
974  ifc_nand_ctrl->read_bytes = 0;
975  ifc_nand_ctrl->index = 0;
976  ifc_nand_ctrl->addr = NULL;
977  fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
978 
979  spin_lock_init(&ifc_nand_ctrl->controller.lock);
980  init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
981  } else {
982  ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
983  }
984  mutex_unlock(&fsl_ifc_nand_mutex);
985 
986  ifc_nand_ctrl->chips[bank] = priv;
987  priv->bank = bank;
988  priv->ctrl = fsl_ifc_ctrl_dev;
989  priv->dev = &dev->dev;
990 
991  priv->vbase = ioremap(res.start, resource_size(&res));
992  if (!priv->vbase) {
993  dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
994  ret = -ENOMEM;
995  goto err;
996  }
997 
998  dev_set_drvdata(priv->dev, priv);
999 
1000  out_be32(&ifc->ifc_nand.nand_evter_en,
1001  IFC_NAND_EVTER_EN_OPC_EN |
1002  IFC_NAND_EVTER_EN_FTOER_EN |
1003  IFC_NAND_EVTER_EN_WPER_EN);
1004 
1005  /* enable NAND Machine Interrupts */
1006  out_be32(&ifc->ifc_nand.nand_evter_intr_en,
1007  IFC_NAND_EVTER_INTR_OPCIR_EN |
1008  IFC_NAND_EVTER_INTR_FTOERIR_EN |
1009  IFC_NAND_EVTER_INTR_WPERIR_EN);
1010 
1011  priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
1012  if (!priv->mtd.name) {
1013  ret = -ENOMEM;
1014  goto err;
1015  }
1016 
1017  ret = fsl_ifc_chip_init(priv);
1018  if (ret)
1019  goto err;
1020 
1021  ret = nand_scan_ident(&priv->mtd, 1, NULL);
1022  if (ret)
1023  goto err;
1024 
1025  ret = fsl_ifc_chip_init_tail(&priv->mtd);
1026  if (ret)
1027  goto err;
1028 
1029  ret = nand_scan_tail(&priv->mtd);
1030  if (ret)
1031  goto err;
1032 
1033  /* First look for RedBoot table or partitions on the command
1034  * line, these take precedence over device tree information */
1035  mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1036  NULL, 0);
1037 
1038  dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1039  (unsigned long long)res.start, priv->bank);
1040  return 0;
1041 
1042 err:
1043  fsl_ifc_chip_remove(priv);
1044  return ret;
1045 }
1046 
1047 static int fsl_ifc_nand_remove(struct platform_device *dev)
1048 {
1049  struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1050 
1051  fsl_ifc_chip_remove(priv);
1052 
1053  mutex_lock(&fsl_ifc_nand_mutex);
1054  ifc_nand_ctrl->counter--;
1055  if (!ifc_nand_ctrl->counter) {
1056  fsl_ifc_ctrl_dev->nand = NULL;
1057  kfree(ifc_nand_ctrl);
1058  }
1059  mutex_unlock(&fsl_ifc_nand_mutex);
1060 
1061  return 0;
1062 }
1063 
1064 static const struct of_device_id fsl_ifc_nand_match[] = {
1065  {
1066  .compatible = "fsl,ifc-nand",
1067  },
1068  {}
1069 };
1070 
1071 static struct platform_driver fsl_ifc_nand_driver = {
1072  .driver = {
1073  .name = "fsl,ifc-nand",
1074  .owner = THIS_MODULE,
1075  .of_match_table = fsl_ifc_nand_match,
1076  },
1077  .probe = fsl_ifc_nand_probe,
1078  .remove = fsl_ifc_nand_remove,
1079 };
1080 
1081 static int __init fsl_ifc_nand_init(void)
1082 {
1083  int ret;
1084 
1085  ret = platform_driver_register(&fsl_ifc_nand_driver);
1086  if (ret)
1087  printk(KERN_ERR "fsl-ifc: Failed to register platform"
1088  "driver\n");
1089 
1090  return ret;
1091 }
1092 
1093 static void __exit fsl_ifc_nand_exit(void)
1094 {
1095  platform_driver_unregister(&fsl_ifc_nand_driver);
1096 }
1097 
1098 module_init(fsl_ifc_nand_init);
1099 module_exit(fsl_ifc_nand_exit);
1100 
1101 MODULE_LICENSE("GPL");
1102 MODULE_AUTHOR("Freescale");
1103 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Generated on Thu Jan 10 2013 13:56:49 for Linux Kernel by   doxygen 1.8.2