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hac.c File Reference
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>

Go to the source code of this file.

Data Structures

struct  hac_priv
 

Macros

#define HACCR   0x08
 
#define HACCSAR   0x20
 
#define HACCSDR   0x24
 
#define HACPCML   0x28
 
#define HACPCMR   0x2C
 
#define HACTIER   0x50
 
#define HACTSR   0x54
 
#define HACRIER   0x58
 
#define HACRSR   0x5C
 
#define HACACR   0x60
 
#define CR_CR   (1 << 15) /* "codec-ready" indicator */
 
#define CR_CDRT   (1 << 11) /* cold reset */
 
#define CR_WMRT   (1 << 10) /* warm reset */
 
#define CR_B9   (1 << 9) /* the mysterious "bit 9" */
 
#define CR_ST   (1 << 5) /* AC97 link start bit */
 
#define CSAR_RD   (1 << 19) /* AC97 data read bit */
 
#define CSAR_WR   (0)
 
#define TSR_CMDAMT   (1 << 31)
 
#define TSR_CMDDMT   (1 << 30)
 
#define RSR_STARY   (1 << 22)
 
#define RSR_STDRY   (1 << 21)
 
#define ACR_DMARX16   (1 << 30)
 
#define ACR_DMATX16   (1 << 29)
 
#define ACR_TX12ATOM   (1 << 26)
 
#define ACR_DMARX20   ((1 << 24) | (1 << 22))
 
#define ACR_DMATX20   ((1 << 23) | (1 << 21))
 
#define CSDR_SHIFT   4
 
#define CSDR_MASK   (0xffff << CSDR_SHIFT)
 
#define CSAR_SHIFT   12
 
#define CSAR_MASK   (0x7f << CSAR_SHIFT)
 
#define AC97_WRITE_RETRY   1
 
#define AC97_READ_RETRY   5
 
#define TMO_E1   500 /* 21 < E1 < 1000 */
 
#define TMO_E2   13 /* 13 < E2 */
 
#define TMO_E3   21 /* 21 < E3 */
 
#define TMO_E4   500 /* 21 < E4 < 1000 */
 
#define HACREG(reg)   (*(unsigned long *)(hac->mmio + (reg)))
 
#define AC97_RATES   SNDRV_PCM_RATE_8000_192000
 
#define AC97_FMTS   SNDRV_PCM_FMTBIT_S16_LE
 

Functions

 EXPORT_SYMBOL_GPL (soc_ac97_ops)
 
 module_platform_driver (hac_pcm_driver)
 
 MODULE_LICENSE ("GPL")
 
 MODULE_DESCRIPTION ("SuperH onchip HAC (AC97) audio driver")
 
 MODULE_AUTHOR ("Manuel Lauss <[email protected]>")
 

Variables

struct hac_priv hac_cpu_data []
 
struct snd_ac97_bus_ops soc_ac97_ops
 

Macro Definition Documentation

#define AC97_FMTS   SNDRV_PCM_FMTBIT_S16_LE

Definition at line 266 of file hac.c.

#define AC97_RATES   SNDRV_PCM_RATE_8000_192000

Definition at line 263 of file hac.c.

#define AC97_READ_RETRY   5

Definition at line 69 of file hac.c.

#define AC97_WRITE_RETRY   1

Definition at line 68 of file hac.c.

#define ACR_DMARX16   (1 << 30)

Definition at line 57 of file hac.c.

#define ACR_DMARX20   ((1 << 24) | (1 << 22))

Definition at line 60 of file hac.c.

#define ACR_DMATX16   (1 << 29)

Definition at line 58 of file hac.c.

#define ACR_DMATX20   ((1 << 23) | (1 << 21))

Definition at line 61 of file hac.c.

#define ACR_TX12ATOM   (1 << 26)

Definition at line 59 of file hac.c.

#define CR_B9   (1 << 9) /* the mysterious "bit 9" */

Definition at line 45 of file hac.c.

#define CR_CDRT   (1 << 11) /* cold reset */

Definition at line 43 of file hac.c.

#define CR_CR   (1 << 15) /* "codec-ready" indicator */

Definition at line 42 of file hac.c.

#define CR_ST   (1 << 5) /* AC97 link start bit */

Definition at line 46 of file hac.c.

#define CR_WMRT   (1 << 10) /* warm reset */

Definition at line 44 of file hac.c.

#define CSAR_MASK   (0x7f << CSAR_SHIFT)

Definition at line 66 of file hac.c.

#define CSAR_RD   (1 << 19) /* AC97 data read bit */

Definition at line 48 of file hac.c.

#define CSAR_SHIFT   12

Definition at line 65 of file hac.c.

#define CSAR_WR   (0)

Definition at line 49 of file hac.c.

#define CSDR_MASK   (0xffff << CSDR_SHIFT)

Definition at line 64 of file hac.c.

#define CSDR_SHIFT   4

Definition at line 63 of file hac.c.

#define HACACR   0x60

Definition at line 40 of file hac.c.

#define HACCR   0x08

Definition at line 31 of file hac.c.

#define HACCSAR   0x20

Definition at line 32 of file hac.c.

#define HACCSDR   0x24

Definition at line 33 of file hac.c.

#define HACPCML   0x28

Definition at line 34 of file hac.c.

#define HACPCMR   0x2C

Definition at line 35 of file hac.c.

#define HACREG (   reg)    (*(unsigned long *)(hac->mmio + (reg)))

Definition at line 96 of file hac.c.

#define HACRIER   0x58

Definition at line 38 of file hac.c.

#define HACRSR   0x5C

Definition at line 39 of file hac.c.

#define HACTIER   0x50

Definition at line 36 of file hac.c.

#define HACTSR   0x54

Definition at line 37 of file hac.c.

#define RSR_STARY   (1 << 22)

Definition at line 54 of file hac.c.

#define RSR_STDRY   (1 << 21)

Definition at line 55 of file hac.c.

#define TMO_E1   500 /* 21 < E1 < 1000 */

Definition at line 72 of file hac.c.

#define TMO_E2   13 /* 13 < E2 */

Definition at line 73 of file hac.c.

#define TMO_E3   21 /* 21 < E3 */

Definition at line 74 of file hac.c.

#define TMO_E4   500 /* 21 < E4 < 1000 */

Definition at line 75 of file hac.c.

#define TSR_CMDAMT   (1 << 31)

Definition at line 51 of file hac.c.

#define TSR_CMDDMT   (1 << 30)

Definition at line 52 of file hac.c.

Function Documentation

EXPORT_SYMBOL_GPL ( soc_ac97_ops  )
MODULE_AUTHOR ( "Manuel Lauss <[email protected]>"  )
MODULE_DESCRIPTION ( "SuperH onchip HAC (AC97) audio driver )
MODULE_LICENSE ( "GPL"  )
module_platform_driver ( hac_pcm_driver  )

Variable Documentation

struct hac_priv hac_cpu_data[]
Initial value:
= {
}
struct snd_ac97_bus_ops soc_ac97_ops
Initial value:
= {
.read = hac_ac97_read,
.write = hac_ac97_write,
.reset = hac_ac97_coldrst,
.warm_reset = hac_ac97_warmrst,
}

Definition at line 230 of file hac.c.