|
| #define | H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */ |
| |
| #define | H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */ |
| |
| #define | H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */ |
| |
| #define | H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */ |
| |
| #define | H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */ |
| |
| #define | H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */ |
| |
| #define | H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */ |
| |
| #define | H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */ |
| |
| #define | H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */ |
| |
| #define | H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */ |
| |
| #define | H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */ |
| |
| #define | H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */ |
| |
| #define | H2_IAR_PARAM 0x000C /* Parameter Select */ |
| |
| #define | H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */ |
| |
| #define | H2I_RELAY_C 0x9100 |
| |
| #define | H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */ |
| |
| #define | H2I_DMA_PORT_EN 0x9104 |
| |
| #define | H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */ |
| |
| #define | H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */ |
| |
| #define | H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */ |
| |
| #define | H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */ |
| |
| #define | H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */ |
| |
| #define | H2I_DMA_END 0x9108 /* global dma endian select */ |
| |
| #define | H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */ |
| |
| #define | H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */ |
| |
| #define | H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */ |
| |
| #define | H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */ |
| |
| #define | H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */ |
| |
| #define | H2I_DMA_DRV 0x910C /* global PBUS DMA enable */ |
| |
| #define | H2I_SYNTH_C 0x1104 /* Synth DMA control */ |
| |
| #define | H2I_AESRX_C 0x1204 /* AES RX dma control */ |
| |
| #define | H2I_C_TS_EN 0x20 /* Timestamp enable */ |
| |
| #define | H2I_C_TS_FRMT 0x40 /* Timestamp format */ |
| |
| #define | H2I_C_NAUDIO 0x80 /* Sign extend */ |
| |
| #define | H2I_AESTX_C 0x1304 /* AES TX DMA control */ |
| |
| #define | H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ |
| |
| #define | H2I_AESTX_C_CLKID_M 0x18 |
| |
| #define | H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ |
| |
| #define | H2I_AESTX_C_DATAT_M 0x300 |
| |
| #define | H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */ |
| |
| #define | H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */ |
| |
| #define | H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */ |
| |
| #define | H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */ |
| |
| #define | H2I_C1_DMA_SHIFT 0 /* DMA channel */ |
| |
| #define | H2I_C1_DMA_M 0x7 |
| |
| #define | H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ |
| |
| #define | H2I_C1_CLKID_M 0x18 |
| |
| #define | H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ |
| |
| #define | H2I_C1_DATAT_M 0x300 |
| |
| #define | H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */ |
| |
| #define | H2I_C2_R_GAIN_M 0xf |
| |
| #define | H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */ |
| |
| #define | H2I_C2_L_GAIN_M 0xf0 |
| |
| #define | H2I_C2_R_SEL 0x100 /* right input select */ |
| |
| #define | H2I_C2_L_SEL 0x200 /* left input select */ |
| |
| #define | H2I_C2_MUTE 0x400 /* mute */ |
| |
| #define | H2I_C2_DO1 0x00010000 /* digital output port bit 0 */ |
| |
| #define | H2I_C2_DO2 0x00020000 /* digital output port bit 1 */ |
| |
| #define | H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */ |
| |
| #define | H2I_C2_R_ATT_M 0x007c0000 /* attenuation */ |
| |
| #define | H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */ |
| |
| #define | H2I_C2_L_ATT_M 0x0f800000 /* attenuation */ |
| |
| #define | H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */ |
| |
| #define | H2I_BRES1_C1 0x2104 |
| |
| #define | H2I_BRES2_C1 0x2204 |
| |
| #define | H2I_BRES3_C1 0x2304 |
| |
| #define | H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */ |
| |
| #define | H2I_BRES_C1_M 0x03 |
| |
| #define | H2I_BRES1_C2 0x2108 |
| |
| #define | H2I_BRES2_C2 0x2208 |
| |
| #define | H2I_BRES3_C2 0x2308 |
| |
| #define | H2I_BRES_C2_INC_SHIFT 0 /* increment value */ |
| |
| #define | H2I_BRES_C2_INC_M 0xffff |
| |
| #define | H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */ |
| |
| #define | H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */ |
| |
| #define | H2I_UTIME 0x3104 |
| |
| #define | H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */ |
| |
| #define | H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */ |
| |
| #define | H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */ |
| |
| #define | H2I_UTIME_2_LD 0xffff /* seconds, LSB's */ |
| |
| #define | H2I_UTIME_3_LD 0xffff /* seconds, MSB's */ |
| |
1.8.2