Go to the source code of this file.
| #define B_FIFO_SIZE (0x2000 - B_SUB_VAL) |
| #define HFCPCI_ACTIVATE 0x20 |
| #define HFCPCI_ANYINT 0x80 |
| #define HFCPCI_AUTO_AWAKE 0x01 |
| #define HFCPCI_AUTO_TIMER 0x20 |
| #define HFCPCI_AUX1_D 0xA8 |
| #define HFCPCI_AUX1_RSL 0x98 |
| #define HFCPCI_AUX1_SSL 0x88 |
| #define HFCPCI_AUX2_D 0xAC |
| #define HFCPCI_AUX2_RSL 0x9C |
| #define HFCPCI_AUX2_SSL 0x8C |
| #define HFCPCI_AUX_MSK 0x07 |
| #define HFCPCI_B1_REC 0xF0 |
| #define HFCPCI_B1_REV 0x40 |
| #define HFCPCI_B1_RSL 0x90 |
| #define HFCPCI_B1_SEND 0xF0 |
| #define HFCPCI_B1_SSL 0x80 |
| #define HFCPCI_B2_REC 0xF4 |
| #define HFCPCI_B2_REV 0x80 |
| #define HFCPCI_B2_RSL 0x94 |
| #define HFCPCI_B2_SEND 0xF4 |
| #define HFCPCI_B2_SSL 0x84 |
| #define HFCPCI_B_MODE 0x4C |
| #define HFCPCI_BTRANS_THRESHOLD 128 |
| #define HFCPCI_BTRANS_THRESMASK 0x00 |
| #define HFCPCI_CHG_B1_B2 0x80 |
| #define HFCPCI_CHIP_ID 0x58 |
| #define HFCPCI_CLKDEL 0xDC |
| #define HFCPCI_CLTIMER 0x80 |
| #define HFCPCI_CONNECT 0xBC |
| #define HFCPCI_D_REC 0xF8 |
| #define HFCPCI_D_SEND 0xF8 |
| #define HFCPCI_DBIT_1 0x04 |
| #define HFCPCI_DO_ACTION 0x40 |
| #define HFCPCI_E_REC 0xFC |
| #define HFCPCI_FIFO_EN 0x44 |
| #define HFCPCI_FIFOEN_B1 0x03 |
| #define HFCPCI_FIFOEN_B1RX 0x02 |
| #define HFCPCI_FIFOEN_B1TX 0x01 |
| #define HFCPCI_FIFOEN_B2 0x0C |
| #define HFCPCI_FIFOEN_B2RX 0x08 |
| #define HFCPCI_FIFOEN_B2TX 0x04 |
| #define HFCPCI_FIFOEN_DTX 0x10 |
| #define HFCPCI_FRAMEINT 0x40 |
| #define HFCPCI_GCI_I_CHG 0x02 |
| #define HFCPCI_GCI_MON_REC 0x04 |
| #define HFCPCI_IGNORE_COL 0x08 |
| #define HFCPCI_INT_M1 0x68 |
| #define HFCPCI_INT_M2 0x6C |
| #define HFCPCI_INT_S1 0x78 |
| #define HFCPCI_INT_S2 0x7C |
| #define HFCPCI_INTS_B1REC 0x08 |
| #define HFCPCI_INTS_B1TRANS 0x01 |
| #define HFCPCI_INTS_B2REC 0x10 |
| #define HFCPCI_INTS_B2TRANS 0x02 |
| #define HFCPCI_INTS_DREC 0x20 |
| #define HFCPCI_INTS_DTRANS 0x04 |
| #define HFCPCI_INTS_L1STATE 0x40 |
| #define HFCPCI_INTS_TIMER 0x80 |
| #define HFCPCI_IRQ_ENABLE 0x08 |
| #define HFCPCI_LOAD_STATE 0x10 |
| #define HFCPCI_MASTER 0x01 |
| #define HFCPCI_MON1_D 0x28 |
| #define HFCPCI_MON2_D 0x2C |
| #define HFCPCI_MST_EMOD 0xB4 |
| #define HFCPCI_MST_MODE 0xB8 |
| #define HFCPCI_NBUSY 0x04 |
| #define HFCPCI_NT_G2_G3 0x80 |
| #define HFCPCI_PCI_PROC 0x02 |
| #define HFCPCI_PMESEL 0x80 |
| #define HFCPCI_PROC_TRANS 0x01 |
| #define HFCPCI_RESET 0x08 |
| #define HFCPCI_SCTRL 0xC4 |
| #define HFCPCI_SCTRL_E 0xC8 |
| #define HFCPCI_SCTRL_R 0xCC |
| #define HFCPCI_SLAVE 0x00 |
| #define HFCPCI_STATE_MSK 0x0F |
| #define HFCPCI_STATES 0xC0 |
| #define HFCPCI_STATINT 0x20 |
| #define HFCPCI_STATUS 0x70 |
| #define HFCPCI_TIM25 0x10 |
| #define HFCPCI_TIM3_125 0x04 |
| #define HFCPCI_TIM400 0x18 |
| #define HFCPCI_TIM50 0x14 |
| #define HFCPCI_TIM800 0x1C |
| #define HFCPCI_TIMER_ELAP 0x10 |
| #define HFCPCI_TRANSB1 0x01 |
| #define HFCPCI_TRANSB2 0x02 |
| #define PCI_ENA_MASTER 0x04 |
| #define PCI_ENA_MEMIO 0x02 |
| #define Read_hfc |
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a, |
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b |
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) |
| (*(((u_char *)a->hw.hfcpci.pci_io) + b)) |
| #define SCTRL_B1_ENA 0x01 |
| #define SCTRL_B2_ENA 0x02 |
| #define SCTRL_LOW_PRIO 0x08 |
| #define SCTRL_MODE_NT 0x04 |
| #define SCTRL_MODE_TE 0x00 |
| #define SCTRL_NONE_CAP 0x40 |
| #define SCTRL_PWR_DOWN 0x80 |
| #define SCTRL_SQ_ENA 0x10 |
| #define Write_hfc |
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a, |
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b, |
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c |
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) |
| (*(((u_char *)a->hw.hfcpci.pci_io) + b) = c) |
1.8.2