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Data Structures | Macros
idt77252.h File Reference
#include <linux/ptrace.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>
#include <linux/mutex.h>

Go to the source code of this file.

Data Structures

struct  scqe
 
struct  scq_info
 
struct  rx_pool
 
struct  aal1
 
struct  rate_estimator
 
struct  vc_map
 
struct  rct_entry
 
struct  rsq_entry
 
struct  rsq_info
 
struct  tsq_entry
 
struct  tsq_info
 
struct  tst_info
 
struct  sb_pool
 
struct  idt77252_dev
 
struct  idt77252_skb_prv
 

Macros

#define VPCI2VC(card, vpi, vci)   (((vpi) << card->vcibits) | ((vci) & card->vcimask))
 
#define DBG_RAW_CELL   0x00000400
 
#define DBG_TINY   0x00000200
 
#define DBG_GENERAL   0x00000100
 
#define DBG_XGENERAL   0x00000080
 
#define DBG_INIT   0x00000040
 
#define DBG_DEINIT   0x00000020
 
#define DBG_INTERRUPT   0x00000010
 
#define DBG_OPEN_CONN   0x00000008
 
#define DBG_CLOSE_CONN   0x00000004
 
#define DBG_RX_DATA   0x00000002
 
#define DBG_TX_DATA   0x00000001
 
#define CPRINTK(args...)   do { } while(0)
 
#define OPRINTK(args...)   do { } while(0)
 
#define IPRINTK(args...)   do { } while(0)
 
#define INTPRINTK(args...)   do { } while(0)
 
#define DIPRINTK(args...)   do { } while(0)
 
#define TXPRINTK(args...)   do { } while(0)
 
#define RXPRINTK(args...)   do { } while(0)
 
#define XPRINTK(args...)   do { } while(0)
 
#define DPRINTK(args...)   do { } while(0)
 
#define NPRINTK(args...)   do { } while(0)
 
#define RPRINTK(args...)   do { } while(0)
 
#define SCHED_UBR0   0
 
#define SCHED_UBR   1
 
#define SCHED_VBR   2
 
#define SCHED_ABR   3
 
#define SCHED_CBR   4
 
#define SCQFULL_TIMEOUT   HZ
 
#define SAR_FB_SIZE_0   (2048 - 256)
 
#define SAR_FB_SIZE_1   (4096 - 256)
 
#define SAR_FB_SIZE_2   (8192 - 256)
 
#define SAR_FB_SIZE_3   (16384 - 256)
 
#define SAR_FBQ0_LOW   4
 
#define SAR_FBQ0_HIGH   8
 
#define SAR_FBQ1_LOW   2
 
#define SAR_FBQ1_HIGH   4
 
#define SAR_FBQ2_LOW   1
 
#define SAR_FBQ2_HIGH   2
 
#define SAR_FBQ3_LOW   1
 
#define SAR_FBQ3_HIGH   2
 
#define SAR_TST_RESERVED   0 /* Num TST reserved for UBR/ABR/VBR */
 
#define TCT_CBR   0x00000000
 
#define TCT_UBR   0x00000000
 
#define TCT_VBR   0x40000000
 
#define TCT_ABR   0x80000000
 
#define TCT_TYPE   0xc0000000
 
#define TCT_RR   0x20000000
 
#define TCT_LMCR   0x08000000
 
#define TCT_SCD_MASK   0x0007ffff
 
#define TCT_TSIF   0x00004000
 
#define TCT_HALT   0x80000000
 
#define TCT_IDLE   0x40000000
 
#define TCT_FLAG_UBR   0x80000000
 
#define SCQ_ENTRIES   64
 
#define SCQ_SIZE   (SCQ_ENTRIES * sizeof(struct scqe))
 
#define SCQ_MASK   (SCQ_SIZE - 1)
 
#define VCF_TX   0
 
#define VCF_RX   1
 
#define VCF_IDLE   2
 
#define VCF_RSV   3
 
#define SAR_RSQE_VALID   0x80000000
 
#define SAR_RSQE_IDLE   0x40000000
 
#define SAR_RSQE_BUF_MASK   0x00030000
 
#define SAR_RSQE_BUF_ASGN   0x00008000
 
#define SAR_RSQE_NZGFC   0x00004000
 
#define SAR_RSQE_EPDU   0x00002000
 
#define SAR_RSQE_BUF_CONT   0x00001000
 
#define SAR_RSQE_EFCIE   0x00000800
 
#define SAR_RSQE_CLP   0x00000400
 
#define SAR_RSQE_CRC   0x00000200
 
#define SAR_RSQE_CELLCNT   0x000001FF
 
#define RSQSIZE   8192
 
#define RSQ_NUM_ENTRIES   (RSQSIZE / 16)
 
#define RSQ_ALIGNMENT   8192
 
#define SAR_TSQE_INVALID   0x80000000
 
#define SAR_TSQE_TIMESTAMP   0x00FFFFFF
 
#define SAR_TSQE_TYPE   0x60000000
 
#define SAR_TSQE_TYPE_TIMER   0x00000000
 
#define SAR_TSQE_TYPE_TSR   0x20000000
 
#define SAR_TSQE_TYPE_IDLE   0x40000000
 
#define SAR_TSQE_TYPE_TBD_COMP   0x60000000
 
#define SAR_TSQE_TAG(stat)   (((stat) >> 24) & 0x1f)
 
#define TSQSIZE   8192
 
#define TSQ_NUM_ENTRIES   1024
 
#define TSQ_ALIGNMENT   8192
 
#define TSTE_MASK   0x601fffff
 
#define TSTE_OPC_MASK   0x60000000
 
#define TSTE_OPC_NULL   0x00000000
 
#define TSTE_OPC_CBR   0x20000000
 
#define TSTE_OPC_VAR   0x40000000
 
#define TSTE_OPC_JMP   0x60000000
 
#define TSTE_PUSH_IDLE   0x01000000
 
#define TSTE_PUSH_ACTIVE   0x02000000
 
#define TST_SWITCH_DONE   0
 
#define TST_SWITCH_PENDING   1
 
#define TST_SWITCH_WAIT   2
 
#define FBQ_SHIFT   9
 
#define FBQ_SIZE   (1 << FBQ_SHIFT)
 
#define FBQ_MASK   (FBQ_SIZE - 1)
 
#define POOL_HANDLE(queue, index)   (((queue + 1) << 16) | (index))
 
#define POOL_QUEUE(handle)   (((handle) >> 16) - 1)
 
#define POOL_INDEX(handle)   ((handle) & 0xffff)
 
#define IDT77252_BIT_INIT   1
 
#define IDT77252_BIT_INTERRUPT   2
 
#define ATM_CELL_PAYLOAD   48
 
#define FREEBUF_ALIGNMENT   16
 
#define ALIGN_ADDRESS(addr, alignment)   ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
 
#define SAR_REG_DR0   (card->membase + 0x00)
 
#define SAR_REG_DR1   (card->membase + 0x04)
 
#define SAR_REG_DR2   (card->membase + 0x08)
 
#define SAR_REG_DR3   (card->membase + 0x0C)
 
#define SAR_REG_CMD   (card->membase + 0x10)
 
#define SAR_REG_CFG   (card->membase + 0x14)
 
#define SAR_REG_STAT   (card->membase + 0x18)
 
#define SAR_REG_RSQB   (card->membase + 0x1C)
 
#define SAR_REG_RSQT   (card->membase + 0x20)
 
#define SAR_REG_RSQH   (card->membase + 0x24)
 
#define SAR_REG_CDC   (card->membase + 0x28)
 
#define SAR_REG_VPEC   (card->membase + 0x2C)
 
#define SAR_REG_ICC   (card->membase + 0x30)
 
#define SAR_REG_RAWCT   (card->membase + 0x34)
 
#define SAR_REG_TMR   (card->membase + 0x38)
 
#define SAR_REG_TSTB   (card->membase + 0x3C)
 
#define SAR_REG_TSQB   (card->membase + 0x40)
 
#define SAR_REG_TSQT   (card->membase + 0x44)
 
#define SAR_REG_TSQH   (card->membase + 0x48)
 
#define SAR_REG_GP   (card->membase + 0x4C)
 
#define SAR_REG_VPM   (card->membase + 0x50)
 
#define SAR_REG_RXFD   (card->membase + 0x54)
 
#define SAR_REG_RXFT   (card->membase + 0x58)
 
#define SAR_REG_RXFH   (card->membase + 0x5C)
 
#define SAR_REG_RAWHND   (card->membase + 0x60)
 
#define SAR_REG_RXSTAT   (card->membase + 0x64)
 
#define SAR_REG_ABRSTD   (card->membase + 0x68)
 
#define SAR_REG_ABRRQ   (card->membase + 0x6C)
 
#define SAR_REG_VBRRQ   (card->membase + 0x70)
 
#define SAR_REG_RTBL   (card->membase + 0x74)
 
#define SAR_REG_MDFCT   (card->membase + 0x78)
 
#define SAR_REG_TXSTAT   (card->membase + 0x7C)
 
#define SAR_REG_TCMDQ   (card->membase + 0x80)
 
#define SAR_REG_IRCP   (card->membase + 0x84)
 
#define SAR_REG_FBQP0   (card->membase + 0x88)
 
#define SAR_REG_FBQP1   (card->membase + 0x8C)
 
#define SAR_REG_FBQP2   (card->membase + 0x90)
 
#define SAR_REG_FBQP3   (card->membase + 0x94)
 
#define SAR_REG_FBQS0   (card->membase + 0x98)
 
#define SAR_REG_FBQS1   (card->membase + 0x9C)
 
#define SAR_REG_FBQS2   (card->membase + 0xA0)
 
#define SAR_REG_FBQS3   (card->membase + 0xA4)
 
#define SAR_REG_FBQWP0   (card->membase + 0xA8)
 
#define SAR_REG_FBQWP1   (card->membase + 0xAC)
 
#define SAR_REG_FBQWP2   (card->membase + 0xB0)
 
#define SAR_REG_FBQWP3   (card->membase + 0xB4)
 
#define SAR_REG_NOW   (card->membase + 0xB8)
 
#define SAR_CMD_NO_OPERATION   0x00000000
 
#define SAR_CMD_OPENCLOSE_CONNECTION   0x20000000
 
#define SAR_CMD_WRITE_SRAM   0x40000000
 
#define SAR_CMD_READ_SRAM   0x50000000
 
#define SAR_CMD_READ_UTILITY   0x80000000
 
#define SAR_CMD_WRITE_UTILITY   0x90000000
 
#define SAR_CMD_OPEN_CONNECTION   (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
 
#define SAR_CMD_CLOSE_CONNECTION   SAR_CMD_OPENCLOSE_CONNECTION
 
#define SAR_CFG_SWRST   0x80000000 /* Software reset */
 
#define SAR_CFG_LOOP   0x40000000 /* Internal Loopback */
 
#define SAR_CFG_RXPTH   0x20000000 /* Receive Path Enable */
 
#define SAR_CFG_IDLE_CLP   0x10000000 /* SAR set CLP Bits of Null Cells */
 
#define SAR_CFG_TX_FIFO_SIZE_1   0x04000000 /* TX FIFO Size = 1 cell */
 
#define SAR_CFG_TX_FIFO_SIZE_2   0x08000000 /* TX FIFO Size = 2 cells */
 
#define SAR_CFG_TX_FIFO_SIZE_4   0x0C000000 /* TX FIFO Size = 4 cells */
 
#define SAR_CFG_TX_FIFO_SIZE_9   0x00000000 /* TX FIFO Size = 9 cells (full) */
 
#define SAR_CFG_NO_IDLE   0x02000000 /* SAR sends no Null Cells */
 
#define SAR_CFG_RSVD1   0x01000000 /* Reserved */
 
#define SAR_CFG_RXSTQ_SIZE_2k   0x00000000 /* RX Stat Queue Size = 2048 byte */
 
#define SAR_CFG_RXSTQ_SIZE_4k   0x00400000 /* RX Stat Queue Size = 4096 byte */
 
#define SAR_CFG_RXSTQ_SIZE_8k   0x00800000 /* RX Stat Queue Size = 8192 byte */
 
#define SAR_CFG_RXSTQ_SIZE_R   0x00C00000 /* RX Stat Queue Size = reserved */
 
#define SAR_CFG_ICAPT   0x00200000 /* accept Invalid Cells */
 
#define SAR_CFG_IGGFC   0x00100000 /* Ignore GFC */
 
#define SAR_CFG_VPVCS_0   0x00000000 /* VPI/VCI Select bit range */
 
#define SAR_CFG_VPVCS_1   0x00040000 /* VPI/VCI Select bit range */
 
#define SAR_CFG_VPVCS_2   0x00080000 /* VPI/VCI Select bit range */
 
#define SAR_CFG_VPVCS_8   0x000C0000 /* VPI/VCI Select bit range */
 
#define SAR_CFG_CNTBL_1k   0x00000000 /* Connection Table Size */
 
#define SAR_CFG_CNTBL_4k   0x00010000 /* Connection Table Size */
 
#define SAR_CFG_CNTBL_16k   0x00020000 /* Connection Table Size */
 
#define SAR_CFG_CNTBL_512   0x00030000 /* Connection Table Size */
 
#define SAR_CFG_VPECA   0x00008000 /* VPI/VCI Error Cell Accept */
 
#define SAR_CFG_RXINT_NOINT   0x00000000 /* No Interrupt on PDU received */
 
#define SAR_CFG_RXINT_NODELAY   0x00001000 /* Interrupt without delay to host*/
 
#define SAR_CFG_RXINT_256US   0x00002000 /* Interrupt with delay 256 usec */
 
#define SAR_CFG_RXINT_505US   0x00003000 /* Interrupt with delay 505 usec */
 
#define SAR_CFG_RXINT_742US   0x00004000 /* Interrupt with delay 742 usec */
 
#define SAR_CFG_RAWIE   0x00000800 /* Raw Cell Queue Interrupt Enable*/
 
#define SAR_CFG_RQFIE   0x00000400 /* RSQ Almost Full Int Enable */
 
#define SAR_CFG_RSVD2   0x00000200 /* Reserved */
 
#define SAR_CFG_CACHE   0x00000100 /* DMA on Cache Line Boundary */
 
#define SAR_CFG_TMOIE   0x00000080 /* Timer Roll Over Int Enable */
 
#define SAR_CFG_FBIE   0x00000040 /* Free Buffer Queue Int Enable */
 
#define SAR_CFG_TXEN   0x00000020 /* Transmit Operation Enable */
 
#define SAR_CFG_TXINT   0x00000010 /* Transmit status Int Enable */
 
#define SAR_CFG_TXUIE   0x00000008 /* Transmit underrun Int Enable */
 
#define SAR_CFG_UMODE   0x00000004 /* Utopia Mode Select */
 
#define SAR_CFG_TXSFI   0x00000002 /* Transmit status Full Int Enable*/
 
#define SAR_CFG_PHYIE   0x00000001 /* PHY Interrupt Enable */
 
#define SAR_CFG_TX_FIFO_SIZE_MASK   0x0C000000 /* TX FIFO Size Mask */
 
#define SAR_CFG_RXSTQSIZE_MASK   0x00C00000
 
#define SAR_CFG_CNTBL_MASK   0x00030000
 
#define SAR_CFG_RXINT_MASK   0x00007000
 
#define SAR_STAT_FRAC_3   0xF0000000 /* Fraction of Free Buffer Queue 3 */
 
#define SAR_STAT_FRAC_2   0x0F000000 /* Fraction of Free Buffer Queue 2 */
 
#define SAR_STAT_FRAC_1   0x00F00000 /* Fraction of Free Buffer Queue 1 */
 
#define SAR_STAT_FRAC_0   0x000F0000 /* Fraction of Free Buffer Queue 0 */
 
#define SAR_STAT_TSIF   0x00008000 /* Transmit Status Indicator */
 
#define SAR_STAT_TXICP   0x00004000 /* Transmit Status Indicator */
 
#define SAR_STAT_RSVD1   0x00002000 /* Reserved */
 
#define SAR_STAT_TSQF   0x00001000 /* Transmit Status Queue full */
 
#define SAR_STAT_TMROF   0x00000800 /* Timer overflow */
 
#define SAR_STAT_PHYI   0x00000400 /* PHY device Interrupt flag */
 
#define SAR_STAT_CMDBZ   0x00000200 /* ABR SAR Command Busy Flag */
 
#define SAR_STAT_FBQ3A   0x00000100 /* Free Buffer Queue 3 Attention */
 
#define SAR_STAT_FBQ2A   0x00000080 /* Free Buffer Queue 2 Attention */
 
#define SAR_STAT_RSQF   0x00000040 /* Receive Status Queue full */
 
#define SAR_STAT_EPDU   0x00000020 /* End Of PDU Flag */
 
#define SAR_STAT_RAWCF   0x00000010 /* Raw Cell Flag */
 
#define SAR_STAT_FBQ1A   0x00000008 /* Free Buffer Queue 1 Attention */
 
#define SAR_STAT_FBQ0A   0x00000004 /* Free Buffer Queue 0 Attention */
 
#define SAR_STAT_RSQAF   0x00000002 /* Receive Status Queue almost full*/
 
#define SAR_STAT_RSVD2   0x00000001 /* Reserved */
 
#define SAR_GP_TXNCC_MASK   0xff000000 /* Transmit Negative Credit Count */
 
#define SAR_GP_EEDI   0x00010000 /* EEPROM Data In */
 
#define SAR_GP_BIGE   0x00008000 /* Big Endian Operation */
 
#define SAR_GP_RM_NORMAL   0x00000000 /* Normal handling of RM cells */
 
#define SAR_GP_RM_TO_RCQ   0x00002000 /* put RM cells into Raw Cell Queue */
 
#define SAR_GP_RM_RSVD   0x00004000 /* Reserved */
 
#define SAR_GP_RM_INHIBIT   0x00006000 /* Inhibit update of Connection tab */
 
#define SAR_GP_PHY_RESET   0x00000008 /* PHY Reset */
 
#define SAR_GP_EESCLK   0x00000004 /* EEPROM SCLK */
 
#define SAR_GP_EECS   0x00000002 /* EEPROM Chip Select */
 
#define SAR_GP_EEDO   0x00000001 /* EEPROM Data Out */
 
#define SAR_SRAM_SCD_SIZE   12
 
#define SAR_SRAM_TCT_SIZE   8
 
#define SAR_SRAM_RCT_SIZE   4
 
#define SAR_SRAM_TCT_128_BASE   0x00000
 
#define SAR_SRAM_TCT_128_TOP   0x01fff
 
#define SAR_SRAM_RCT_128_BASE   0x02000
 
#define SAR_SRAM_RCT_128_TOP   0x02fff
 
#define SAR_SRAM_FB0_128_BASE   0x03000
 
#define SAR_SRAM_FB0_128_TOP   0x033ff
 
#define SAR_SRAM_FB1_128_BASE   0x03400
 
#define SAR_SRAM_FB1_128_TOP   0x037ff
 
#define SAR_SRAM_FB2_128_BASE   0x03800
 
#define SAR_SRAM_FB2_128_TOP   0x03bff
 
#define SAR_SRAM_FB3_128_BASE   0x03c00
 
#define SAR_SRAM_FB3_128_TOP   0x03fff
 
#define SAR_SRAM_SCD_128_BASE   0x04000
 
#define SAR_SRAM_SCD_128_TOP   0x07fff
 
#define SAR_SRAM_TST1_128_BASE   0x08000
 
#define SAR_SRAM_TST1_128_TOP   0x0bfff
 
#define SAR_SRAM_TST2_128_BASE   0x0c000
 
#define SAR_SRAM_TST2_128_TOP   0x0ffff
 
#define SAR_SRAM_ABRSTD_128_BASE   0x10000
 
#define SAR_SRAM_ABRSTD_128_TOP   0x13fff
 
#define SAR_SRAM_RT_128_BASE   0x14000
 
#define SAR_SRAM_RT_128_TOP   0x15fff
 
#define SAR_SRAM_FIFO_128_BASE   0x18000
 
#define SAR_SRAM_FIFO_128_TOP   0x1ffff
 
#define SAR_SRAM_TCT_32_BASE   0x00000
 
#define SAR_SRAM_TCT_32_TOP   0x00fff
 
#define SAR_SRAM_RCT_32_BASE   0x01000
 
#define SAR_SRAM_RCT_32_TOP   0x017ff
 
#define SAR_SRAM_FB0_32_BASE   0x01800
 
#define SAR_SRAM_FB0_32_TOP   0x01bff
 
#define SAR_SRAM_FB1_32_BASE   0x01c00
 
#define SAR_SRAM_FB1_32_TOP   0x01fff
 
#define SAR_SRAM_FB2_32_BASE   0x02000
 
#define SAR_SRAM_FB2_32_TOP   0x023ff
 
#define SAR_SRAM_FB3_32_BASE   0x02400
 
#define SAR_SRAM_FB3_32_TOP   0x027ff
 
#define SAR_SRAM_SCD_32_BASE   0x02800
 
#define SAR_SRAM_SCD_32_TOP   0x03fff
 
#define SAR_SRAM_TST1_32_BASE   0x04000
 
#define SAR_SRAM_TST1_32_TOP   0x04fff
 
#define SAR_SRAM_TST2_32_BASE   0x05000
 
#define SAR_SRAM_TST2_32_TOP   0x05fff
 
#define SAR_SRAM_ABRSTD_32_BASE   0x06000
 
#define SAR_SRAM_ABRSTD_32_TOP   0x067ff
 
#define SAR_SRAM_RT_32_BASE   0x06800
 
#define SAR_SRAM_RT_32_TOP   0x06fff
 
#define SAR_SRAM_FIFO_32_BASE   0x07000
 
#define SAR_SRAM_FIFO_32_TOP   0x07fff
 
#define SAR_TSR_TYPE_TSR   0x80000000
 
#define SAR_TSR_TYPE_TBD   0x00000000
 
#define SAR_TSR_TSIF   0x20000000
 
#define SAR_TSR_TAG_MASK   0x01F00000
 
#define SAR_TBD_EPDU   0x40000000
 
#define SAR_TBD_TSIF   0x20000000
 
#define SAR_TBD_OAM   0x10000000
 
#define SAR_TBD_AAL0   0x00000000
 
#define SAR_TBD_AAL34   0x04000000
 
#define SAR_TBD_AAL5   0x08000000
 
#define SAR_TBD_GTSI   0x02000000
 
#define SAR_TBD_TAG_MASK   0x01F00000
 
#define SAR_TBD_VPI_MASK   0x0FF00000
 
#define SAR_TBD_VCI_MASK   0x000FFFF0
 
#define SAR_TBD_VC_MASK   (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)
 
#define SAR_TBD_VPI_SHIFT   20
 
#define SAR_TBD_VCI_SHIFT   4
 
#define SAR_RXFD_SIZE_MASK   0x0F000000
 
#define SAR_RXFD_SIZE_512   0x00000000 /* 512 words */
 
#define SAR_RXFD_SIZE_1K   0x01000000 /* 1k words */
 
#define SAR_RXFD_SIZE_2K   0x02000000 /* 2k words */
 
#define SAR_RXFD_SIZE_4K   0x03000000 /* 4k words */
 
#define SAR_RXFD_SIZE_8K   0x04000000 /* 8k words */
 
#define SAR_RXFD_SIZE_16K   0x05000000 /* 16k words */
 
#define SAR_RXFD_SIZE_32K   0x06000000 /* 32k words */
 
#define SAR_RXFD_SIZE_64K   0x07000000 /* 64k words */
 
#define SAR_RXFD_SIZE_128K   0x08000000 /* 128k words */
 
#define SAR_RXFD_SIZE_256K   0x09000000 /* 256k words */
 
#define SAR_RXFD_ADDR_MASK   0x001ffc00
 
#define SAR_ABRSTD_SIZE_MASK   0x07000000
 
#define SAR_ABRSTD_SIZE_512   0x00000000 /* 512 words */
 
#define SAR_ABRSTD_SIZE_1K   0x01000000 /* 1k words */
 
#define SAR_ABRSTD_SIZE_2K   0x02000000 /* 2k words */
 
#define SAR_ABRSTD_SIZE_4K   0x03000000 /* 4k words */
 
#define SAR_ABRSTD_SIZE_8K   0x04000000 /* 8k words */
 
#define SAR_ABRSTD_SIZE_16K   0x05000000 /* 16k words */
 
#define SAR_ABRSTD_ADDR_MASK   0x001ffc00
 
#define SAR_RCTE_IL_MASK   0xE0000000 /* inactivity limit */
 
#define SAR_RCTE_IC_MASK   0x1C000000 /* inactivity count */
 
#define SAR_RCTE_RSVD   0x02000000 /* reserved */
 
#define SAR_RCTE_LCD   0x01000000 /* last cell data */
 
#define SAR_RCTE_CI_VC   0x00800000 /* EFCI in previous cell of VC */
 
#define SAR_RCTE_FBP_01   0x00000000 /* 1. cell->FBQ0, others->FBQ1 */
 
#define SAR_RCTE_FBP_1   0x00200000 /* use FBQ 1 for all cells */
 
#define SAR_RCTE_FBP_2   0x00400000 /* use FBQ 2 for all cells */
 
#define SAR_RCTE_FBP_3   0x00600000 /* use FBQ 3 for all cells */
 
#define SAR_RCTE_NZ_GFC   0x00100000 /* non zero GFC in all cell of VC */
 
#define SAR_RCTE_CONNECTOPEN   0x00080000 /* VC is open */
 
#define SAR_RCTE_AAL_MASK   0x00070000 /* mask for AAL type field s.b. */
 
#define SAR_RCTE_RAWCELLINTEN   0x00008000 /* raw cell interrupt enable */
 
#define SAR_RCTE_RXCONCELLADDR   0x00004000 /* RX constant cell address */
 
#define SAR_RCTE_BUFFSTAT_MASK   0x00003000 /* buffer status */
 
#define SAR_RCTE_EFCI   0x00000800 /* EFCI Congestion flag */
 
#define SAR_RCTE_CLP   0x00000400 /* Cell Loss Priority flag */
 
#define SAR_RCTE_CRC   0x00000200 /* Received CRC Error */
 
#define SAR_RCTE_CELLCNT_MASK   0x000001FF /* cell Count */
 
#define SAR_RCTE_AAL0   0x00000000 /* AAL types for ALL field */
 
#define SAR_RCTE_AAL34   0x00010000
 
#define SAR_RCTE_AAL5   0x00020000
 
#define SAR_RCTE_RCQ   0x00030000
 
#define SAR_RCTE_OAM   0x00040000
 
#define TCMDQ_START   0x01000000
 
#define TCMDQ_LACR   0x02000000
 
#define TCMDQ_START_LACR   0x03000000
 
#define TCMDQ_INIT_ER   0x04000000
 
#define TCMDQ_HALT   0x05000000
 
#define IDT77252_PRV_TBD(skb)   (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
 
#define IDT77252_PRV_PADDR(skb)   (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
 
#define IDT77252_PRV_POOL(skb)   (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)
 
#define PCI_VENDOR_ID_IDT   0x111D
 
#define PCI_DEVICE_ID_IDT_IDT77252   0x0003
 

Macro Definition Documentation

#define ALIGN_ADDRESS (   addr,
  alignment 
)    ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))

Definition at line 428 of file idt77252.h.

#define ATM_CELL_PAYLOAD   48

Definition at line 419 of file idt77252.h.

#define CPRINTK (   args...)    do { } while(0)

Definition at line 80 of file idt77252.h.

#define DBG_CLOSE_CONN   0x00000004

Definition at line 60 of file idt77252.h.

#define DBG_DEINIT   0x00000020

Definition at line 57 of file idt77252.h.

#define DBG_GENERAL   0x00000100

Definition at line 54 of file idt77252.h.

#define DBG_INIT   0x00000040

Definition at line 56 of file idt77252.h.

#define DBG_INTERRUPT   0x00000010

Definition at line 58 of file idt77252.h.

#define DBG_OPEN_CONN   0x00000008

Definition at line 59 of file idt77252.h.

#define DBG_RAW_CELL   0x00000400

Definition at line 52 of file idt77252.h.

#define DBG_RX_DATA   0x00000002

Definition at line 61 of file idt77252.h.

#define DBG_TINY   0x00000200

Definition at line 53 of file idt77252.h.

#define DBG_TX_DATA   0x00000001

Definition at line 62 of file idt77252.h.

#define DBG_XGENERAL   0x00000080

Definition at line 55 of file idt77252.h.

#define DIPRINTK (   args...)    do { } while(0)

Definition at line 84 of file idt77252.h.

#define DPRINTK (   args...)    do { } while(0)

Definition at line 88 of file idt77252.h.

#define FBQ_MASK   (FBQ_SIZE - 1)

Definition at line 332 of file idt77252.h.

#define FBQ_SHIFT   9

Definition at line 330 of file idt77252.h.

#define FBQ_SIZE   (1 << FBQ_SHIFT)

Definition at line 331 of file idt77252.h.

#define FREEBUF_ALIGNMENT   16

Definition at line 421 of file idt77252.h.

#define IDT77252_BIT_INIT   1

Definition at line 415 of file idt77252.h.

#define IDT77252_BIT_INTERRUPT   2

Definition at line 416 of file idt77252.h.

#define IDT77252_PRV_PADDR (   skb)    (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)

Definition at line 793 of file idt77252.h.

#define IDT77252_PRV_POOL (   skb)    (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)

Definition at line 795 of file idt77252.h.

#define IDT77252_PRV_TBD (   skb)    (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)

Definition at line 791 of file idt77252.h.

#define INTPRINTK (   args...)    do { } while(0)

Definition at line 83 of file idt77252.h.

#define IPRINTK (   args...)    do { } while(0)

Definition at line 82 of file idt77252.h.

#define NPRINTK (   args...)    do { } while(0)

Definition at line 89 of file idt77252.h.

#define OPRINTK (   args...)    do { } while(0)

Definition at line 81 of file idt77252.h.

#define PCI_DEVICE_ID_IDT_IDT77252   0x0003

Definition at line 809 of file idt77252.h.

#define PCI_VENDOR_ID_IDT   0x111D

Definition at line 805 of file idt77252.h.

#define POOL_HANDLE (   queue,
  index 
)    (((queue + 1) << 16) | (index))

Definition at line 340 of file idt77252.h.

#define POOL_INDEX (   handle)    ((handle) & 0xffff)

Definition at line 342 of file idt77252.h.

#define POOL_QUEUE (   handle)    (((handle) >> 16) - 1)

Definition at line 341 of file idt77252.h.

#define RPRINTK (   args...)    do { } while(0)

Definition at line 90 of file idt77252.h.

#define RSQ_ALIGNMENT   8192

Definition at line 258 of file idt77252.h.

#define RSQ_NUM_ENTRIES   (RSQSIZE / 16)

Definition at line 257 of file idt77252.h.

#define RSQSIZE   8192

Definition at line 256 of file idt77252.h.

#define RXPRINTK (   args...)    do { } while(0)

Definition at line 86 of file idt77252.h.

#define SAR_ABRSTD_ADDR_MASK   0x001ffc00

Definition at line 743 of file idt77252.h.

#define SAR_ABRSTD_SIZE_16K   0x05000000 /* 16k words */

Definition at line 742 of file idt77252.h.

#define SAR_ABRSTD_SIZE_1K   0x01000000 /* 1k words */

Definition at line 738 of file idt77252.h.

#define SAR_ABRSTD_SIZE_2K   0x02000000 /* 2k words */

Definition at line 739 of file idt77252.h.

#define SAR_ABRSTD_SIZE_4K   0x03000000 /* 4k words */

Definition at line 740 of file idt77252.h.

#define SAR_ABRSTD_SIZE_512   0x00000000 /* 512 words */

Definition at line 737 of file idt77252.h.

#define SAR_ABRSTD_SIZE_8K   0x04000000 /* 8k words */

Definition at line 741 of file idt77252.h.

#define SAR_ABRSTD_SIZE_MASK   0x07000000

Definition at line 736 of file idt77252.h.

#define SAR_CFG_CACHE   0x00000100 /* DMA on Cache Line Boundary */

Definition at line 543 of file idt77252.h.

#define SAR_CFG_CNTBL_16k   0x00020000 /* Connection Table Size */

Definition at line 532 of file idt77252.h.

#define SAR_CFG_CNTBL_1k   0x00000000 /* Connection Table Size */

Definition at line 530 of file idt77252.h.

#define SAR_CFG_CNTBL_4k   0x00010000 /* Connection Table Size */

Definition at line 531 of file idt77252.h.

#define SAR_CFG_CNTBL_512   0x00030000 /* Connection Table Size */

Definition at line 533 of file idt77252.h.

#define SAR_CFG_CNTBL_MASK   0x00030000

Definition at line 555 of file idt77252.h.

#define SAR_CFG_FBIE   0x00000040 /* Free Buffer Queue Int Enable */

Definition at line 545 of file idt77252.h.

#define SAR_CFG_ICAPT   0x00200000 /* accept Invalid Cells */

Definition at line 524 of file idt77252.h.

#define SAR_CFG_IDLE_CLP   0x10000000 /* SAR set CLP Bits of Null Cells */

Definition at line 513 of file idt77252.h.

#define SAR_CFG_IGGFC   0x00100000 /* Ignore GFC */

Definition at line 525 of file idt77252.h.

#define SAR_CFG_LOOP   0x40000000 /* Internal Loopback */

Definition at line 511 of file idt77252.h.

#define SAR_CFG_NO_IDLE   0x02000000 /* SAR sends no Null Cells */

Definition at line 518 of file idt77252.h.

#define SAR_CFG_PHYIE   0x00000001 /* PHY Interrupt Enable */

Definition at line 551 of file idt77252.h.

#define SAR_CFG_RAWIE   0x00000800 /* Raw Cell Queue Interrupt Enable*/

Definition at line 540 of file idt77252.h.

#define SAR_CFG_RQFIE   0x00000400 /* RSQ Almost Full Int Enable */

Definition at line 541 of file idt77252.h.

#define SAR_CFG_RSVD1   0x01000000 /* Reserved */

Definition at line 519 of file idt77252.h.

#define SAR_CFG_RSVD2   0x00000200 /* Reserved */

Definition at line 542 of file idt77252.h.

#define SAR_CFG_RXINT_256US   0x00002000 /* Interrupt with delay 256 usec */

Definition at line 537 of file idt77252.h.

#define SAR_CFG_RXINT_505US   0x00003000 /* Interrupt with delay 505 usec */

Definition at line 538 of file idt77252.h.

#define SAR_CFG_RXINT_742US   0x00004000 /* Interrupt with delay 742 usec */

Definition at line 539 of file idt77252.h.

#define SAR_CFG_RXINT_MASK   0x00007000

Definition at line 556 of file idt77252.h.

#define SAR_CFG_RXINT_NODELAY   0x00001000 /* Interrupt without delay to host*/

Definition at line 536 of file idt77252.h.

#define SAR_CFG_RXINT_NOINT   0x00000000 /* No Interrupt on PDU received */

Definition at line 535 of file idt77252.h.

#define SAR_CFG_RXPTH   0x20000000 /* Receive Path Enable */

Definition at line 512 of file idt77252.h.

#define SAR_CFG_RXSTQ_SIZE_2k   0x00000000 /* RX Stat Queue Size = 2048 byte */

Definition at line 520 of file idt77252.h.

#define SAR_CFG_RXSTQ_SIZE_4k   0x00400000 /* RX Stat Queue Size = 4096 byte */

Definition at line 521 of file idt77252.h.

#define SAR_CFG_RXSTQ_SIZE_8k   0x00800000 /* RX Stat Queue Size = 8192 byte */

Definition at line 522 of file idt77252.h.

#define SAR_CFG_RXSTQ_SIZE_R   0x00C00000 /* RX Stat Queue Size = reserved */

Definition at line 523 of file idt77252.h.

#define SAR_CFG_RXSTQSIZE_MASK   0x00C00000

Definition at line 554 of file idt77252.h.

#define SAR_CFG_SWRST   0x80000000 /* Software reset */

Definition at line 510 of file idt77252.h.

#define SAR_CFG_TMOIE   0x00000080 /* Timer Roll Over Int Enable */

Definition at line 544 of file idt77252.h.

#define SAR_CFG_TX_FIFO_SIZE_1   0x04000000 /* TX FIFO Size = 1 cell */

Definition at line 514 of file idt77252.h.

#define SAR_CFG_TX_FIFO_SIZE_2   0x08000000 /* TX FIFO Size = 2 cells */

Definition at line 515 of file idt77252.h.

#define SAR_CFG_TX_FIFO_SIZE_4   0x0C000000 /* TX FIFO Size = 4 cells */

Definition at line 516 of file idt77252.h.

#define SAR_CFG_TX_FIFO_SIZE_9   0x00000000 /* TX FIFO Size = 9 cells (full) */

Definition at line 517 of file idt77252.h.

#define SAR_CFG_TX_FIFO_SIZE_MASK   0x0C000000 /* TX FIFO Size Mask */

Definition at line 553 of file idt77252.h.

#define SAR_CFG_TXEN   0x00000020 /* Transmit Operation Enable */

Definition at line 546 of file idt77252.h.

#define SAR_CFG_TXINT   0x00000010 /* Transmit status Int Enable */

Definition at line 547 of file idt77252.h.

#define SAR_CFG_TXSFI   0x00000002 /* Transmit status Full Int Enable*/

Definition at line 550 of file idt77252.h.

#define SAR_CFG_TXUIE   0x00000008 /* Transmit underrun Int Enable */

Definition at line 548 of file idt77252.h.

#define SAR_CFG_UMODE   0x00000004 /* Utopia Mode Select */

Definition at line 549 of file idt77252.h.

#define SAR_CFG_VPECA   0x00008000 /* VPI/VCI Error Cell Accept */

Definition at line 534 of file idt77252.h.

#define SAR_CFG_VPVCS_0   0x00000000 /* VPI/VCI Select bit range */

Definition at line 526 of file idt77252.h.

#define SAR_CFG_VPVCS_1   0x00040000 /* VPI/VCI Select bit range */

Definition at line 527 of file idt77252.h.

#define SAR_CFG_VPVCS_2   0x00080000 /* VPI/VCI Select bit range */

Definition at line 528 of file idt77252.h.

#define SAR_CFG_VPVCS_8   0x000C0000 /* VPI/VCI Select bit range */

Definition at line 529 of file idt77252.h.

#define SAR_CMD_CLOSE_CONNECTION   SAR_CMD_OPENCLOSE_CONNECTION

Definition at line 501 of file idt77252.h.

#define SAR_CMD_NO_OPERATION   0x00000000

Definition at line 493 of file idt77252.h.

#define SAR_CMD_OPEN_CONNECTION   (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)

Definition at line 500 of file idt77252.h.

#define SAR_CMD_OPENCLOSE_CONNECTION   0x20000000

Definition at line 494 of file idt77252.h.

#define SAR_CMD_READ_SRAM   0x50000000

Definition at line 496 of file idt77252.h.

#define SAR_CMD_READ_UTILITY   0x80000000

Definition at line 497 of file idt77252.h.

#define SAR_CMD_WRITE_SRAM   0x40000000

Definition at line 495 of file idt77252.h.

#define SAR_CMD_WRITE_UTILITY   0x90000000

Definition at line 498 of file idt77252.h.

#define SAR_FB_SIZE_0   (2048 - 256)

Definition at line 107 of file idt77252.h.

#define SAR_FB_SIZE_1   (4096 - 256)

Definition at line 108 of file idt77252.h.

#define SAR_FB_SIZE_2   (8192 - 256)

Definition at line 109 of file idt77252.h.

#define SAR_FB_SIZE_3   (16384 - 256)

Definition at line 110 of file idt77252.h.

#define SAR_FBQ0_HIGH   8

Definition at line 113 of file idt77252.h.

#define SAR_FBQ0_LOW   4

Definition at line 112 of file idt77252.h.

#define SAR_FBQ1_HIGH   4

Definition at line 115 of file idt77252.h.

#define SAR_FBQ1_LOW   2

Definition at line 114 of file idt77252.h.

#define SAR_FBQ2_HIGH   2

Definition at line 117 of file idt77252.h.

#define SAR_FBQ2_LOW   1

Definition at line 116 of file idt77252.h.

#define SAR_FBQ3_HIGH   2

Definition at line 119 of file idt77252.h.

#define SAR_FBQ3_LOW   1

Definition at line 118 of file idt77252.h.

#define SAR_GP_BIGE   0x00008000 /* Big Endian Operation */

Definition at line 595 of file idt77252.h.

#define SAR_GP_EECS   0x00000002 /* EEPROM Chip Select */

Definition at line 602 of file idt77252.h.

#define SAR_GP_EEDI   0x00010000 /* EEPROM Data In */

Definition at line 594 of file idt77252.h.

#define SAR_GP_EEDO   0x00000001 /* EEPROM Data Out */

Definition at line 603 of file idt77252.h.

#define SAR_GP_EESCLK   0x00000004 /* EEPROM SCLK */

Definition at line 601 of file idt77252.h.

#define SAR_GP_PHY_RESET   0x00000008 /* PHY Reset */

Definition at line 600 of file idt77252.h.

#define SAR_GP_RM_INHIBIT   0x00006000 /* Inhibit update of Connection tab */

Definition at line 599 of file idt77252.h.

#define SAR_GP_RM_NORMAL   0x00000000 /* Normal handling of RM cells */

Definition at line 596 of file idt77252.h.

#define SAR_GP_RM_RSVD   0x00004000 /* Reserved */

Definition at line 598 of file idt77252.h.

#define SAR_GP_RM_TO_RCQ   0x00002000 /* put RM cells into Raw Cell Queue */

Definition at line 597 of file idt77252.h.

#define SAR_GP_TXNCC_MASK   0xff000000 /* Transmit Negative Credit Count */

Definition at line 593 of file idt77252.h.

#define SAR_RCTE_AAL0   0x00000000 /* AAL types for ALL field */

Definition at line 772 of file idt77252.h.

#define SAR_RCTE_AAL34   0x00010000

Definition at line 773 of file idt77252.h.

#define SAR_RCTE_AAL5   0x00020000

Definition at line 774 of file idt77252.h.

#define SAR_RCTE_AAL_MASK   0x00070000 /* mask for AAL type field s.b. */

Definition at line 763 of file idt77252.h.

#define SAR_RCTE_BUFFSTAT_MASK   0x00003000 /* buffer status */

Definition at line 766 of file idt77252.h.

#define SAR_RCTE_CELLCNT_MASK   0x000001FF /* cell Count */

Definition at line 770 of file idt77252.h.

#define SAR_RCTE_CI_VC   0x00800000 /* EFCI in previous cell of VC */

Definition at line 756 of file idt77252.h.

#define SAR_RCTE_CLP   0x00000400 /* Cell Loss Priority flag */

Definition at line 768 of file idt77252.h.

#define SAR_RCTE_CONNECTOPEN   0x00080000 /* VC is open */

Definition at line 762 of file idt77252.h.

#define SAR_RCTE_CRC   0x00000200 /* Received CRC Error */

Definition at line 769 of file idt77252.h.

#define SAR_RCTE_EFCI   0x00000800 /* EFCI Congestion flag */

Definition at line 767 of file idt77252.h.

#define SAR_RCTE_FBP_01   0x00000000 /* 1. cell->FBQ0, others->FBQ1 */

Definition at line 757 of file idt77252.h.

#define SAR_RCTE_FBP_1   0x00200000 /* use FBQ 1 for all cells */

Definition at line 758 of file idt77252.h.

#define SAR_RCTE_FBP_2   0x00400000 /* use FBQ 2 for all cells */

Definition at line 759 of file idt77252.h.

#define SAR_RCTE_FBP_3   0x00600000 /* use FBQ 3 for all cells */

Definition at line 760 of file idt77252.h.

#define SAR_RCTE_IC_MASK   0x1C000000 /* inactivity count */

Definition at line 753 of file idt77252.h.

#define SAR_RCTE_IL_MASK   0xE0000000 /* inactivity limit */

Definition at line 752 of file idt77252.h.

#define SAR_RCTE_LCD   0x01000000 /* last cell data */

Definition at line 755 of file idt77252.h.

#define SAR_RCTE_NZ_GFC   0x00100000 /* non zero GFC in all cell of VC */

Definition at line 761 of file idt77252.h.

#define SAR_RCTE_OAM   0x00040000

Definition at line 776 of file idt77252.h.

#define SAR_RCTE_RAWCELLINTEN   0x00008000 /* raw cell interrupt enable */

Definition at line 764 of file idt77252.h.

#define SAR_RCTE_RCQ   0x00030000

Definition at line 775 of file idt77252.h.

#define SAR_RCTE_RSVD   0x02000000 /* reserved */

Definition at line 754 of file idt77252.h.

#define SAR_RCTE_RXCONCELLADDR   0x00004000 /* RX constant cell address */

Definition at line 765 of file idt77252.h.

#define SAR_REG_ABRRQ   (card->membase + 0x6C)

Definition at line 465 of file idt77252.h.

#define SAR_REG_ABRSTD   (card->membase + 0x68)

Definition at line 464 of file idt77252.h.

#define SAR_REG_CDC   (card->membase + 0x28)

Definition at line 448 of file idt77252.h.

#define SAR_REG_CFG   (card->membase + 0x14)

Definition at line 443 of file idt77252.h.

#define SAR_REG_CMD   (card->membase + 0x10)

Definition at line 442 of file idt77252.h.

#define SAR_REG_DR0   (card->membase + 0x00)

Definition at line 438 of file idt77252.h.

#define SAR_REG_DR1   (card->membase + 0x04)

Definition at line 439 of file idt77252.h.

#define SAR_REG_DR2   (card->membase + 0x08)

Definition at line 440 of file idt77252.h.

#define SAR_REG_DR3   (card->membase + 0x0C)

Definition at line 441 of file idt77252.h.

#define SAR_REG_FBQP0   (card->membase + 0x88)

Definition at line 472 of file idt77252.h.

#define SAR_REG_FBQP1   (card->membase + 0x8C)

Definition at line 473 of file idt77252.h.

#define SAR_REG_FBQP2   (card->membase + 0x90)

Definition at line 474 of file idt77252.h.

#define SAR_REG_FBQP3   (card->membase + 0x94)

Definition at line 475 of file idt77252.h.

#define SAR_REG_FBQS0   (card->membase + 0x98)

Definition at line 476 of file idt77252.h.

#define SAR_REG_FBQS1   (card->membase + 0x9C)

Definition at line 477 of file idt77252.h.

#define SAR_REG_FBQS2   (card->membase + 0xA0)

Definition at line 478 of file idt77252.h.

#define SAR_REG_FBQS3   (card->membase + 0xA4)

Definition at line 479 of file idt77252.h.

#define SAR_REG_FBQWP0   (card->membase + 0xA8)

Definition at line 480 of file idt77252.h.

#define SAR_REG_FBQWP1   (card->membase + 0xAC)

Definition at line 481 of file idt77252.h.

#define SAR_REG_FBQWP2   (card->membase + 0xB0)

Definition at line 482 of file idt77252.h.

#define SAR_REG_FBQWP3   (card->membase + 0xB4)

Definition at line 483 of file idt77252.h.

#define SAR_REG_GP   (card->membase + 0x4C)

Definition at line 457 of file idt77252.h.

#define SAR_REG_ICC   (card->membase + 0x30)

Definition at line 450 of file idt77252.h.

#define SAR_REG_IRCP   (card->membase + 0x84)

Definition at line 471 of file idt77252.h.

#define SAR_REG_MDFCT   (card->membase + 0x78)

Definition at line 468 of file idt77252.h.

#define SAR_REG_NOW   (card->membase + 0xB8)

Definition at line 484 of file idt77252.h.

#define SAR_REG_RAWCT   (card->membase + 0x34)

Definition at line 451 of file idt77252.h.

#define SAR_REG_RAWHND   (card->membase + 0x60)

Definition at line 462 of file idt77252.h.

#define SAR_REG_RSQB   (card->membase + 0x1C)

Definition at line 445 of file idt77252.h.

#define SAR_REG_RSQH   (card->membase + 0x24)

Definition at line 447 of file idt77252.h.

#define SAR_REG_RSQT   (card->membase + 0x20)

Definition at line 446 of file idt77252.h.

#define SAR_REG_RTBL   (card->membase + 0x74)

Definition at line 467 of file idt77252.h.

#define SAR_REG_RXFD   (card->membase + 0x54)

Definition at line 459 of file idt77252.h.

#define SAR_REG_RXFH   (card->membase + 0x5C)

Definition at line 461 of file idt77252.h.

#define SAR_REG_RXFT   (card->membase + 0x58)

Definition at line 460 of file idt77252.h.

#define SAR_REG_RXSTAT   (card->membase + 0x64)

Definition at line 463 of file idt77252.h.

#define SAR_REG_STAT   (card->membase + 0x18)

Definition at line 444 of file idt77252.h.

#define SAR_REG_TCMDQ   (card->membase + 0x80)

Definition at line 470 of file idt77252.h.

#define SAR_REG_TMR   (card->membase + 0x38)

Definition at line 452 of file idt77252.h.

#define SAR_REG_TSQB   (card->membase + 0x40)

Definition at line 454 of file idt77252.h.

#define SAR_REG_TSQH   (card->membase + 0x48)

Definition at line 456 of file idt77252.h.

#define SAR_REG_TSQT   (card->membase + 0x44)

Definition at line 455 of file idt77252.h.

#define SAR_REG_TSTB   (card->membase + 0x3C)

Definition at line 453 of file idt77252.h.

#define SAR_REG_TXSTAT   (card->membase + 0x7C)

Definition at line 469 of file idt77252.h.

#define SAR_REG_VBRRQ   (card->membase + 0x70)

Definition at line 466 of file idt77252.h.

#define SAR_REG_VPEC   (card->membase + 0x2C)

Definition at line 449 of file idt77252.h.

#define SAR_REG_VPM   (card->membase + 0x50)

Definition at line 458 of file idt77252.h.

#define SAR_RSQE_BUF_ASGN   0x00008000

Definition at line 246 of file idt77252.h.

#define SAR_RSQE_BUF_CONT   0x00001000

Definition at line 249 of file idt77252.h.

#define SAR_RSQE_BUF_MASK   0x00030000

Definition at line 245 of file idt77252.h.

#define SAR_RSQE_CELLCNT   0x000001FF

Definition at line 253 of file idt77252.h.

#define SAR_RSQE_CLP   0x00000400

Definition at line 251 of file idt77252.h.

#define SAR_RSQE_CRC   0x00000200

Definition at line 252 of file idt77252.h.

#define SAR_RSQE_EFCIE   0x00000800

Definition at line 250 of file idt77252.h.

#define SAR_RSQE_EPDU   0x00002000

Definition at line 248 of file idt77252.h.

#define SAR_RSQE_IDLE   0x40000000

Definition at line 244 of file idt77252.h.

#define SAR_RSQE_NZGFC   0x00004000

Definition at line 247 of file idt77252.h.

#define SAR_RSQE_VALID   0x80000000

Definition at line 243 of file idt77252.h.

#define SAR_RXFD_ADDR_MASK   0x001ffc00

Definition at line 727 of file idt77252.h.

#define SAR_RXFD_SIZE_128K   0x08000000 /* 128k words */

Definition at line 725 of file idt77252.h.

#define SAR_RXFD_SIZE_16K   0x05000000 /* 16k words */

Definition at line 722 of file idt77252.h.

#define SAR_RXFD_SIZE_1K   0x01000000 /* 1k words */

Definition at line 718 of file idt77252.h.

#define SAR_RXFD_SIZE_256K   0x09000000 /* 256k words */

Definition at line 726 of file idt77252.h.

#define SAR_RXFD_SIZE_2K   0x02000000 /* 2k words */

Definition at line 719 of file idt77252.h.

#define SAR_RXFD_SIZE_32K   0x06000000 /* 32k words */

Definition at line 723 of file idt77252.h.

#define SAR_RXFD_SIZE_4K   0x03000000 /* 4k words */

Definition at line 720 of file idt77252.h.

#define SAR_RXFD_SIZE_512   0x00000000 /* 512 words */

Definition at line 717 of file idt77252.h.

#define SAR_RXFD_SIZE_64K   0x07000000 /* 64k words */

Definition at line 724 of file idt77252.h.

#define SAR_RXFD_SIZE_8K   0x04000000 /* 8k words */

Definition at line 721 of file idt77252.h.

#define SAR_RXFD_SIZE_MASK   0x0F000000

Definition at line 716 of file idt77252.h.

#define SAR_SRAM_ABRSTD_128_BASE   0x10000

Definition at line 634 of file idt77252.h.

#define SAR_SRAM_ABRSTD_128_TOP   0x13fff

Definition at line 635 of file idt77252.h.

#define SAR_SRAM_ABRSTD_32_BASE   0x06000

Definition at line 667 of file idt77252.h.

#define SAR_SRAM_ABRSTD_32_TOP   0x067ff

Definition at line 668 of file idt77252.h.

#define SAR_SRAM_FB0_128_BASE   0x03000

Definition at line 620 of file idt77252.h.

#define SAR_SRAM_FB0_128_TOP   0x033ff

Definition at line 621 of file idt77252.h.

#define SAR_SRAM_FB0_32_BASE   0x01800

Definition at line 653 of file idt77252.h.

#define SAR_SRAM_FB0_32_TOP   0x01bff

Definition at line 654 of file idt77252.h.

#define SAR_SRAM_FB1_128_BASE   0x03400

Definition at line 622 of file idt77252.h.

#define SAR_SRAM_FB1_128_TOP   0x037ff

Definition at line 623 of file idt77252.h.

#define SAR_SRAM_FB1_32_BASE   0x01c00

Definition at line 655 of file idt77252.h.

#define SAR_SRAM_FB1_32_TOP   0x01fff

Definition at line 656 of file idt77252.h.

#define SAR_SRAM_FB2_128_BASE   0x03800

Definition at line 624 of file idt77252.h.

#define SAR_SRAM_FB2_128_TOP   0x03bff

Definition at line 625 of file idt77252.h.

#define SAR_SRAM_FB2_32_BASE   0x02000

Definition at line 657 of file idt77252.h.

#define SAR_SRAM_FB2_32_TOP   0x023ff

Definition at line 658 of file idt77252.h.

#define SAR_SRAM_FB3_128_BASE   0x03c00

Definition at line 626 of file idt77252.h.

#define SAR_SRAM_FB3_128_TOP   0x03fff

Definition at line 627 of file idt77252.h.

#define SAR_SRAM_FB3_32_BASE   0x02400

Definition at line 659 of file idt77252.h.

#define SAR_SRAM_FB3_32_TOP   0x027ff

Definition at line 660 of file idt77252.h.

#define SAR_SRAM_FIFO_128_BASE   0x18000

Definition at line 639 of file idt77252.h.

#define SAR_SRAM_FIFO_128_TOP   0x1ffff

Definition at line 640 of file idt77252.h.

#define SAR_SRAM_FIFO_32_BASE   0x07000

Definition at line 671 of file idt77252.h.

#define SAR_SRAM_FIFO_32_TOP   0x07fff

Definition at line 672 of file idt77252.h.

#define SAR_SRAM_RCT_128_BASE   0x02000

Definition at line 618 of file idt77252.h.

#define SAR_SRAM_RCT_128_TOP   0x02fff

Definition at line 619 of file idt77252.h.

#define SAR_SRAM_RCT_32_BASE   0x01000

Definition at line 651 of file idt77252.h.

#define SAR_SRAM_RCT_32_TOP   0x017ff

Definition at line 652 of file idt77252.h.

#define SAR_SRAM_RCT_SIZE   4

Definition at line 614 of file idt77252.h.

#define SAR_SRAM_RT_128_BASE   0x14000

Definition at line 636 of file idt77252.h.

#define SAR_SRAM_RT_128_TOP   0x15fff

Definition at line 637 of file idt77252.h.

#define SAR_SRAM_RT_32_BASE   0x06800

Definition at line 669 of file idt77252.h.

#define SAR_SRAM_RT_32_TOP   0x06fff

Definition at line 670 of file idt77252.h.

#define SAR_SRAM_SCD_128_BASE   0x04000

Definition at line 628 of file idt77252.h.

#define SAR_SRAM_SCD_128_TOP   0x07fff

Definition at line 629 of file idt77252.h.

#define SAR_SRAM_SCD_32_BASE   0x02800

Definition at line 661 of file idt77252.h.

#define SAR_SRAM_SCD_32_TOP   0x03fff

Definition at line 662 of file idt77252.h.

#define SAR_SRAM_SCD_SIZE   12

Definition at line 612 of file idt77252.h.

#define SAR_SRAM_TCT_128_BASE   0x00000

Definition at line 616 of file idt77252.h.

#define SAR_SRAM_TCT_128_TOP   0x01fff

Definition at line 617 of file idt77252.h.

#define SAR_SRAM_TCT_32_BASE   0x00000

Definition at line 649 of file idt77252.h.

#define SAR_SRAM_TCT_32_TOP   0x00fff

Definition at line 650 of file idt77252.h.

#define SAR_SRAM_TCT_SIZE   8

Definition at line 613 of file idt77252.h.

#define SAR_SRAM_TST1_128_BASE   0x08000

Definition at line 630 of file idt77252.h.

#define SAR_SRAM_TST1_128_TOP   0x0bfff

Definition at line 631 of file idt77252.h.

#define SAR_SRAM_TST1_32_BASE   0x04000

Definition at line 663 of file idt77252.h.

#define SAR_SRAM_TST1_32_TOP   0x04fff

Definition at line 664 of file idt77252.h.

#define SAR_SRAM_TST2_128_BASE   0x0c000

Definition at line 632 of file idt77252.h.

#define SAR_SRAM_TST2_128_TOP   0x0ffff

Definition at line 633 of file idt77252.h.

#define SAR_SRAM_TST2_32_BASE   0x05000

Definition at line 665 of file idt77252.h.

#define SAR_SRAM_TST2_32_TOP   0x05fff

Definition at line 666 of file idt77252.h.

#define SAR_STAT_CMDBZ   0x00000200 /* ABR SAR Command Busy Flag */

Definition at line 575 of file idt77252.h.

#define SAR_STAT_EPDU   0x00000020 /* End Of PDU Flag */

Definition at line 579 of file idt77252.h.

#define SAR_STAT_FBQ0A   0x00000004 /* Free Buffer Queue 0 Attention */

Definition at line 582 of file idt77252.h.

#define SAR_STAT_FBQ1A   0x00000008 /* Free Buffer Queue 1 Attention */

Definition at line 581 of file idt77252.h.

#define SAR_STAT_FBQ2A   0x00000080 /* Free Buffer Queue 2 Attention */

Definition at line 577 of file idt77252.h.

#define SAR_STAT_FBQ3A   0x00000100 /* Free Buffer Queue 3 Attention */

Definition at line 576 of file idt77252.h.

#define SAR_STAT_FRAC_0   0x000F0000 /* Fraction of Free Buffer Queue 0 */

Definition at line 568 of file idt77252.h.

#define SAR_STAT_FRAC_1   0x00F00000 /* Fraction of Free Buffer Queue 1 */

Definition at line 567 of file idt77252.h.

#define SAR_STAT_FRAC_2   0x0F000000 /* Fraction of Free Buffer Queue 2 */

Definition at line 566 of file idt77252.h.

#define SAR_STAT_FRAC_3   0xF0000000 /* Fraction of Free Buffer Queue 3 */

Definition at line 565 of file idt77252.h.

#define SAR_STAT_PHYI   0x00000400 /* PHY device Interrupt flag */

Definition at line 574 of file idt77252.h.

#define SAR_STAT_RAWCF   0x00000010 /* Raw Cell Flag */

Definition at line 580 of file idt77252.h.

#define SAR_STAT_RSQAF   0x00000002 /* Receive Status Queue almost full*/

Definition at line 583 of file idt77252.h.

#define SAR_STAT_RSQF   0x00000040 /* Receive Status Queue full */

Definition at line 578 of file idt77252.h.

#define SAR_STAT_RSVD1   0x00002000 /* Reserved */

Definition at line 571 of file idt77252.h.

#define SAR_STAT_RSVD2   0x00000001 /* Reserved */

Definition at line 584 of file idt77252.h.

#define SAR_STAT_TMROF   0x00000800 /* Timer overflow */

Definition at line 573 of file idt77252.h.

#define SAR_STAT_TSIF   0x00008000 /* Transmit Status Indicator */

Definition at line 569 of file idt77252.h.

#define SAR_STAT_TSQF   0x00001000 /* Transmit Status Queue full */

Definition at line 572 of file idt77252.h.

#define SAR_STAT_TXICP   0x00004000 /* Transmit Status Indicator */

Definition at line 570 of file idt77252.h.

#define SAR_TBD_AAL0   0x00000000

Definition at line 696 of file idt77252.h.

#define SAR_TBD_AAL34   0x04000000

Definition at line 697 of file idt77252.h.

#define SAR_TBD_AAL5   0x08000000

Definition at line 698 of file idt77252.h.

#define SAR_TBD_EPDU   0x40000000

Definition at line 693 of file idt77252.h.

#define SAR_TBD_GTSI   0x02000000

Definition at line 699 of file idt77252.h.

#define SAR_TBD_OAM   0x10000000

Definition at line 695 of file idt77252.h.

#define SAR_TBD_TAG_MASK   0x01F00000

Definition at line 700 of file idt77252.h.

#define SAR_TBD_TSIF   0x20000000

Definition at line 694 of file idt77252.h.

#define SAR_TBD_VC_MASK   (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)

Definition at line 704 of file idt77252.h.

#define SAR_TBD_VCI_MASK   0x000FFFF0

Definition at line 703 of file idt77252.h.

#define SAR_TBD_VCI_SHIFT   4

Definition at line 707 of file idt77252.h.

#define SAR_TBD_VPI_MASK   0x0FF00000

Definition at line 702 of file idt77252.h.

#define SAR_TBD_VPI_SHIFT   20

Definition at line 706 of file idt77252.h.

#define SAR_TSQE_INVALID   0x80000000

Definition at line 281 of file idt77252.h.

#define SAR_TSQE_TAG (   stat)    (((stat) >> 24) & 0x1f)

Definition at line 289 of file idt77252.h.

#define SAR_TSQE_TIMESTAMP   0x00FFFFFF

Definition at line 282 of file idt77252.h.

#define SAR_TSQE_TYPE   0x60000000

Definition at line 283 of file idt77252.h.

#define SAR_TSQE_TYPE_IDLE   0x40000000

Definition at line 286 of file idt77252.h.

#define SAR_TSQE_TYPE_TBD_COMP   0x60000000

Definition at line 287 of file idt77252.h.

#define SAR_TSQE_TYPE_TIMER   0x00000000

Definition at line 284 of file idt77252.h.

#define SAR_TSQE_TYPE_TSR   0x20000000

Definition at line 285 of file idt77252.h.

#define SAR_TSR_TAG_MASK   0x01F00000

Definition at line 684 of file idt77252.h.

#define SAR_TSR_TSIF   0x20000000

Definition at line 683 of file idt77252.h.

#define SAR_TSR_TYPE_TBD   0x00000000

Definition at line 682 of file idt77252.h.

#define SAR_TSR_TYPE_TSR   0x80000000

Definition at line 681 of file idt77252.h.

#define SAR_TST_RESERVED   0 /* Num TST reserved for UBR/ABR/VBR */

Definition at line 124 of file idt77252.h.

#define SCHED_ABR   3

Definition at line 97 of file idt77252.h.

#define SCHED_CBR   4

Definition at line 98 of file idt77252.h.

#define SCHED_UBR   1

Definition at line 95 of file idt77252.h.

#define SCHED_UBR0   0

Definition at line 94 of file idt77252.h.

#define SCHED_VBR   2

Definition at line 96 of file idt77252.h.

#define SCQ_ENTRIES   64

Definition at line 156 of file idt77252.h.

#define SCQ_MASK   (SCQ_SIZE - 1)

Definition at line 158 of file idt77252.h.

#define SCQ_SIZE   (SCQ_ENTRIES * sizeof(struct scqe))

Definition at line 157 of file idt77252.h.

#define SCQFULL_TIMEOUT   HZ

Definition at line 100 of file idt77252.h.

#define TCMDQ_HALT   0x05000000

Definition at line 782 of file idt77252.h.

#define TCMDQ_INIT_ER   0x04000000

Definition at line 781 of file idt77252.h.

#define TCMDQ_LACR   0x02000000

Definition at line 779 of file idt77252.h.

#define TCMDQ_START   0x01000000

Definition at line 778 of file idt77252.h.

#define TCMDQ_START_LACR   0x03000000

Definition at line 780 of file idt77252.h.

#define TCT_ABR   0x80000000

Definition at line 130 of file idt77252.h.

#define TCT_CBR   0x00000000

Definition at line 127 of file idt77252.h.

#define TCT_FLAG_UBR   0x80000000

Definition at line 140 of file idt77252.h.

#define TCT_HALT   0x80000000

Definition at line 138 of file idt77252.h.

#define TCT_IDLE   0x40000000

Definition at line 139 of file idt77252.h.

#define TCT_LMCR   0x08000000

Definition at line 134 of file idt77252.h.

#define TCT_RR   0x20000000

Definition at line 133 of file idt77252.h.

#define TCT_SCD_MASK   0x0007ffff

Definition at line 135 of file idt77252.h.

#define TCT_TSIF   0x00004000

Definition at line 137 of file idt77252.h.

#define TCT_TYPE   0xc0000000

Definition at line 131 of file idt77252.h.

#define TCT_UBR   0x00000000

Definition at line 128 of file idt77252.h.

#define TCT_VBR   0x40000000

Definition at line 129 of file idt77252.h.

#define TSQ_ALIGNMENT   8192

Definition at line 293 of file idt77252.h.

#define TSQ_NUM_ENTRIES   1024

Definition at line 292 of file idt77252.h.

#define TSQSIZE   8192

Definition at line 291 of file idt77252.h.

#define TST_SWITCH_DONE   0

Definition at line 326 of file idt77252.h.

#define TST_SWITCH_PENDING   1

Definition at line 327 of file idt77252.h.

#define TST_SWITCH_WAIT   2

Definition at line 328 of file idt77252.h.

#define TSTE_MASK   0x601fffff

Definition at line 315 of file idt77252.h.

#define TSTE_OPC_CBR   0x20000000

Definition at line 319 of file idt77252.h.

#define TSTE_OPC_JMP   0x60000000

Definition at line 321 of file idt77252.h.

#define TSTE_OPC_MASK   0x60000000

Definition at line 317 of file idt77252.h.

#define TSTE_OPC_NULL   0x00000000

Definition at line 318 of file idt77252.h.

#define TSTE_OPC_VAR   0x40000000

Definition at line 320 of file idt77252.h.

#define TSTE_PUSH_ACTIVE   0x02000000

Definition at line 324 of file idt77252.h.

#define TSTE_PUSH_IDLE   0x01000000

Definition at line 323 of file idt77252.h.

#define TXPRINTK (   args...)    do { } while(0)

Definition at line 85 of file idt77252.h.

#define VCF_IDLE   2

Definition at line 203 of file idt77252.h.

#define VCF_RSV   3

Definition at line 204 of file idt77252.h.

#define VCF_RX   1

Definition at line 202 of file idt77252.h.

#define VCF_TX   0

Definition at line 201 of file idt77252.h.

#define VPCI2VC (   card,
  vpi,
  vci 
)    (((vpi) << card->vcibits) | ((vci) & card->vcimask))

Definition at line 43 of file idt77252.h.

#define XPRINTK (   args...)    do { } while(0)

Definition at line 87 of file idt77252.h.

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