Data Structures
struct	IA_CMDBUF

struct	cpcs_trailer

struct	cpcs_trailer_desc

struct	ia_vcc

struct	abr_vc_table

struct	main_vc

struct	ext_vc

struct	dle

struct	dle_q

struct	free_desc_q

struct	tx_buf_desc

struct	rx_buf_desc

struct	_ffredn_t

struct	_rfredn_t

struct	ia_regs_t

struct	f_vc_abr_entry

struct	r_vc_abr_entry

struct	srv_cls_param

struct	testTable_t

struct	RX_ERROR_Q

struct	vcstatus_t

struct	ia_rfL_t

struct	ia_ffL_t

struct	desc_tbl_t

struct	ia_rtn_q

struct	_SUNI_STATS_

struct	iadev_priv

Macros
#define	IF_IADBG_INIT_ADAPTER 0x00000001

#define	IF_IADBG_TX 0x00000002

#define	IF_IADBG_RX 0x00000004

#define	IF_IADBG_QUERY_INFO 0x00000008

#define	IF_IADBG_SHUTDOWN 0x00000010

#define	IF_IADBG_INTR 0x00000020

#define	IF_IADBG_TXPKT 0x00000040

#define	IF_IADBG_RXPKT 0x00000080

#define	IF_IADBG_ERR 0x00000100

#define	IF_IADBG_EVENT 0x00000200

#define	IF_IADBG_DIS_INTR 0x00001000

#define	IF_IADBG_EN_INTR 0x00002000

#define	IF_IADBG_LOUD 0x00004000

#define	IF_IADBG_VERY_LOUD 0x00008000

#define	IF_IADBG_CBR 0x00100000

#define	IF_IADBG_UBR 0x00200000

#define	IF_IADBG_ABR 0x00400000

#define	IF_IADBG_DESC 0x01000000

#define	IF_IADBG_SUNI_STAT 0x02000000

#define	IF_IADBG_RESET 0x04000000

#define	IF_IADBG(f) if (IADebugFlag & (f))

#define	IF_LOUD(A)

#define	IF_VERY_LOUD(A)

#define	IF_INIT_ADAPTER(A)

#define	IF_INIT(A)

#define	IF_SUNI_STAT(A)

#define	IF_PVC_CHKPKT(A)

#define	IF_QUERY_INFO(A)

#define	IF_COPY_OVER(A)

#define	IF_HANG(A)

#define	IF_INTR(A)

#define	IF_DIS_INTR(A)

#define	IF_EN_INTR(A)

#define	IF_TX(A)

#define	IF_RX(A)

#define	IF_TXDEBUG(A)

#define	IF_VC(A)

#define	IF_ERR(A)

#define	IF_CBR(A)

#define	IF_UBR(A)

#define	IF_ABR(A)

#define	IF_SHUTDOWN(A)

#define	DbgPrint(A)

#define	IF_EVENT(A)

#define	IF_TXPKT(A)

#define	IF_RXPKT(A)

#define	isprint(a) ((a >=' ')&&(a <= '~'))

#define	ATM_DESC(skb) (skb->protocol)

#define	IA_SKB_STATE(skb) (skb->protocol)

#define	IA_DLED 1

#define	IA_TX_DONE 2

#define	IA_CMD 0x7749

#define	MEMDUMP 0x01

#define	MEMDUMP_SEGREG 0x2

#define	MEMDUMP_DEV 0x1

#define	MEMDUMP_REASSREG 0x3

#define	MEMDUMP_FFL 0x4

#define	READ_REG 0x5

#define	WAKE_DBG_WAIT 0x6

#define	Boolean(x) ((x) ? 1 : 0)

#define	NR_VCI 1024 /* number of VCIs */

#define	NR_VCI_LD 10 /* log2(NR_VCI) */

#define	NR_VCI_4K 4096 /* number of VCIs */

#define	NR_VCI_4K_LD 12 /* log2(NR_VCI) */

#define	MEM_VALID 0xfffffff0 /* mask base address with this */

#define	PCI_VENDOR_ID_IPHASE 0x107e

#define	PCI_DEVICE_ID_IPHASE_5575 0x0008

#define	DEV_LABEL "ia"

#define	PCR 207692

#define	ICR 100000

#define	MCR 0

#define	TBE 1000

#define	FRTT 1

#define	RIF 2

#define	RDF 4

#define	NRMCODE 5 /* 0 - 7 */

#define	TRMCODE 3 /* 0 - 7 */

#define	CDFCODE 6

#define	ATDFCODE 2 /* 0 - 15 */

#define	TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */

#define	DFL_TX_BUF_SZ 10240 /* 10 K buffers */

#define	DFL_TX_BUFFERS

#define	REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */

#define	RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */

#define	DFL_RX_BUF_SZ 10240 /* 10k buffers */

#define	DFL_RX_BUFFERS

#define	ABR 0x8000

#define	UBR 0xc000

#define	CBR 0x0000

#define	UIOLI 0x80

#define	CRC_APPEND 0x40 /* for status field - CRC-32 append */

#define	ABR_STATE 0x02

#define	DLE_ENTRIES 256

#define	DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */

#define	TX_DLE_PSI 0x0001

#define	DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)

#define	EPROM_SIZE 0x40000 /* says 64K in the docs ??? */

#define	MAC1_LEN 4

#define	MAC2_LEN 2

#define	IPHASE5575_PCI_CONFIG_REG_BASE 0x0000

#define	IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */

#define	IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000

#define	IPHASE5575_REASS_CONTROL_REG_BASE 0x3000

#define	IPHASE5575_DMA_CONTROL_REG_BASE 0x4000

#define	IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE

#define	IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000

#define	IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000

#define	IPHASE5575_BUS_CONTROL_REG 0x00

#define	IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */

#define	IPHASE5575_MAC1 0x02

#define	IPHASE5575_REV 0x03

#define	IPHASE5575_MAC2 0x03 /actual offset 0x0e-reg 0x0c/

#define	IPHASE5575_EXT_RESET 0x04

#define	IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */

#define	IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */

#define	IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */

#define	IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b

#define	IPHASE5575_CELL_FIFO_MARK_STATE 0x0c

#define	IPHASE5575_CELL_FIFO_READ_PTR 0x0d

#define	IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e

#define	IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */

#define	CTRL_FE_RST 0x80000000

#define	CTRL_LED 0x40000000

#define	CTRL_25MBPHY 0x10000000

#define	CTRL_ENCMBMEM 0x08000000

#define	CTRL_ENOFFSEG 0x01000000

#define	CTRL_ERRMASK 0x00400000

#define	CTRL_DLETMASK 0x00100000

#define	CTRL_DLERMASK 0x00080000

#define	CTRL_FEMASK 0x00040000

#define	CTRL_SEGMASK 0x00020000

#define	CTRL_REASSMASK 0x00010000

#define	CTRL_CSPREEMPT 0x00002000

#define	CTRL_B128 0x00000200

#define	CTRL_B64 0x00000100

#define	CTRL_B48 0x00000080

#define	CTRL_B32 0x00000040

#define	CTRL_B16 0x00000020

#define	CTRL_B8 0x00000010

#define	STAT_CMEMSIZ 0xc0000000

#define	STAT_ADPARCK 0x20000000

#define	STAT_RESVD 0x1fffff80

#define	STAT_ERRINT 0x00000040

#define	STAT_MARKINT 0x00000020

#define	STAT_DLETINT 0x00000010

#define	STAT_DLERINT 0x00000008

#define	STAT_FEINT 0x00000004

#define	STAT_SEGINT 0x00000002

#define	STAT_REASSINT 0x00000001

#define	IDLEHEADHI 0x00

#define	IDLEHEADLO 0x01

#define	MAXRATE 0x02

#define	RATE155 0x64b1

#define	MAX_ATM_155 352768

#define	RATE25 0x5f9d

#define	STPARMS 0x03

#define	STPARMS_1K 0x008c

#define	STPARMS_2K 0x0049

#define	STPARMS_4K 0x0026

#define	COMP_EN 0x4000

#define	CBR_EN 0x2000

#define	ABR_EN 0x0800

#define	UBR_EN 0x0400

#define	ABRUBR_ARB 0x04

#define	RM_TYPE 0x05

#define	RM_TYPE_4_0 0x0100

#define	SEG_COMMAND_REG 0x17

#define	RESET_SEG 0x0055

#define	RESET_SEG_STATE 0x00aa

#define	RESET_TX_CELL_CTR 0x00cc

#define	CBR_PTR_BASE 0x20

#define	ABR_SBPTR_BASE 0x22

#define	UBR_SBPTR_BASE 0x23

#define	ABRWQ_BASE 0x26

#define	UBRWQ_BASE 0x27

#define	VCT_BASE 0x28

#define	VCTE_BASE 0x29

#define	CBR_TAB_BEG 0x2c

#define	CBR_TAB_END 0x2d

#define	PRQ_ST_ADR 0x30

#define	PRQ_ED_ADR 0x31

#define	PRQ_RD_PTR 0x32

#define	PRQ_WR_PTR 0x33

#define	TCQ_ST_ADR 0x34

#define	TCQ_ED_ADR 0x35

#define	TCQ_RD_PTR 0x36

#define	TCQ_WR_PTR 0x37

#define	SEG_QUEUE_BASE 0x40

#define	SEG_DESC_BASE 0x41

#define	MODE_REG_0 0x45

#define	T_ONLINE 0x0002 /* (i)chipSAR is online */

#define	MODE_REG_1 0x46

#define	MODE_REG_1_VAL 0x0400 /for propoer device operation/

#define	SEG_INTR_STATUS_REG 0x47

#define	SEG_MASK_REG 0x48

#define	TRANSMIT_DONE 0x0200

#define	TCQ_NOT_EMPTY

#define	CELL_CTR_HIGH_AUTO 0x49

#define	CELL_CTR_HIGH_NOAUTO 0xc9

#define	CELL_CTR_LO_AUTO 0x4a

#define	CELL_CTR_LO_NOAUTO 0xca

#define	NEXTDESC 0x59

#define	NEXTVC 0x5a

#define	PSLOTCNT 0x5d

#define	NEWDN 0x6a

#define	NEWVC 0x6b

#define	SBPTR 0x6c

#define	ABRWQ_WRPTR 0x6f

#define	ABRWQ_RDPTR 0x70

#define	UBRWQ_WRPTR 0x71

#define	UBRWQ_RDPTR 0x72

#define	CBR_VC 0x73

#define	ABR_SBVC 0x75

#define	UBR_SBVC 0x76

#define	ABRNEXTLINK 0x78

#define	UBRNEXTLINK 0x79

#define	MODE_REG 0x00

#define	R_ONLINE 0x0002 /* (i)chip is online */

#define	IGN_RAW_FL 0x0004

#define	PROTOCOL_ID 0x01

#define	REASS_MASK_REG 0x02

#define	REASS_INTR_STATUS_REG 0x03

#define	RX_PKT_CTR_OF 0x8000

#define	RX_ERR_CTR_OF 0x4000

#define	RX_CELL_CTR_OF 0x1000

#define	RX_FREEQ_EMPT 0x0200

#define	RX_EXCPQ_FL 0x0080

#define	RX_RAWQ_FL 0x0010

#define	RX_EXCP_RCVD 0x0008

#define	RX_PKT_RCVD 0x0004

#define	RX_RAW_RCVD 0x0001

#define	DRP_PKT_CNTR 0x04

#define	ERR_CNTR 0x05

#define	RAW_BASE_ADR 0x08

#define	CELL_CTR0 0x0c

#define	CELL_CTR1 0x0d

#define	REASS_COMMAND_REG 0x0f

#define	RESET_REASS 0x0055

#define	RESET_REASS_STATE 0x00aa

#define	RESET_DRP_PKT_CNTR 0x00f1

#define	RESET_ERR_CNTR 0x00f2

#define	RESET_CELL_CNTR 0x00f8

#define	RESET_REASS_ALL_REGS 0x00ff

#define	REASS_DESC_BASE 0x10

#define	VC_LKUP_BASE 0x11

#define	REASS_TABLE_BASE 0x12

#define	REASS_QUEUE_BASE 0x13

#define	PKT_TM_CNT 0x16

#define	TMOUT_RANGE 0x17

#define	INTRVL_CNTR 0x18

#define	TMOUT_INDX 0x19

#define	VP_LKUP_BASE 0x1c

#define	VP_FILTER 0x1d

#define	ABR_LKUP_BASE 0x1e

#define	FREEQ_ST_ADR 0x24

#define	FREEQ_ED_ADR 0x25

#define	FREEQ_RD_PTR 0x26

#define	FREEQ_WR_PTR 0x27

#define	PCQ_ST_ADR 0x28

#define	PCQ_ED_ADR 0x29

#define	PCQ_RD_PTR 0x2a

#define	PCQ_WR_PTR 0x2b

#define	EXCP_Q_ST_ADR 0x2c

#define	EXCP_Q_ED_ADR 0x2d

#define	EXCP_Q_RD_PTR 0x2e

#define	EXCP_Q_WR_PTR 0x2f

#define	CC_FIFO_ST_ADR 0x34

#define	CC_FIFO_ED_ADR 0x35

#define	CC_FIFO_RD_PTR 0x36

#define	CC_FIFO_WR_PTR 0x37

#define	STATE_REG 0x38

#define	BUF_SIZE 0x42

#define	XTRA_RM_OFFSET 0x44

#define	DRP_PKT_CNTR_NC 0x84

#define	ERR_CNTR_NC 0x85

#define	CELL_CNTR0_NC 0x8c

#define	CELL_CNTR1_NC 0x8d

#define	EXCPQ_EMPTY 0x0040

#define	PCQ_EMPTY 0x0010

#define	FREEQ_EMPTY 0x0004

#define	IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */

#define	IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */

#define	IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */

#define	IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */

#define	TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */

#define	TX_COMP_Q 0x1000 /* Transmit Complete Queue */

#define	PKT_RDY_Q 0x1400 /* Packet Ready Queue */

#define	CBR_SCHED_TABLE 0x1800 /* CBR Table */

#define	UBR_SCHED_TABLE 0x3000 /* UBR Table */

#define	UBR_WAIT_Q 0x4000 /* UBR Wait Queue */

#define	ABR_SCHED_TABLE 0x5000 /* ABR Table */

#define	ABR_WAIT_Q 0x5800 /* ABR Wait Queue */

#define	EXT_VC_TABLE 0x6000 /* Extended VC Table */

#define	MAIN_VC_TABLE 0x8000 /* Main VC Table */

#define	SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */

#define	TX_DESC_TABLE_SZ

#define	DESC_MODE 0x0

#define	VC_INDEX 0x1

#define	BYTE_CNT 0x3

#define	PKT_START_HI 0x4

#define	PKT_START_LO 0x5

#define	EOM_EN 0x0800

#define	AAL5 0x0100

#define	APP_CRC32 0x0400

#define	CMPL_INT 0x1000

#define	TABLE_ADDRESS(db, dn, to) (((unsigned long)(db & 0x04)) << 16) \| (dn << 5) \| (to << 1)

#define	RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */

#define	VP_TABLE 0x5c00 /* VP Table */

#define	EXCEPTION_Q 0x5e00 /* Exception Queue */

#define	FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */

#define	PKT_COMP_Q 0x6800 /* Packet Complete Queue */

#define	REASS_TABLE 0x7000 /* Reassembly Table */

#define	RX_VC_TABLE 0x7800 /* VC Table */

#define	ABR_VC_TABLE 0x8000 /* ABR VC Table */

#define	RX_DESC_TABLE_SZ

#define	VP_TABLE_SZ 256 /* Number of entries in VPTable */

#define	RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */

#define	REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */

#define	RX_ACT 0x8000

#define	RX_VPVC 0x4000

#define	RX_CNG 0x0040

#define	RX_CER 0x0008

#define	RX_PTE 0x0004

#define	RX_OFL 0x0002

#define	NUM_RX_EXCP 32

#define	NO_AAL5_PKT 0x0000

#define	AAL5_PKT_REASSEMBLED 0x4000

#define	AAL5_PKT_TERMINATED 0x8000

#define	RAW_PKT 0xc000

#define	REASS_ABR 0x2000

#define	REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE

#define	RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE

#define	PHY_BASE IPHASE5575_FRONT_END_REG_BASE

#define	SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE

#define	REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE

#define	MRM 3

#define	VC_ACTIVE 0x01

#define	VC_ABR 0x02

#define	VC_UBR 0x04

#define	SUNI_LOSV 0x04

#define	INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)

#define	INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)

#define	MB25_MC_UPLO 0x80 /* UPLO */

#define	MB25_MC_DREC 0x40 /* Discard receive cell errors */

#define	MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */

#define	MB25_MC_TDPC 0x10 /* Transmit data parity check */

#define	MB25_MC_DRIC 0x08 /* Discard receive idle cells */

#define	MB25_MC_HALTTX 0x04 /* Halt Tx */

#define	MB25_MC_UMS 0x02 /* UTOPIA mode select */

#define	MB25_MC_ENABLED 0x01 /* Enable interrupt */

#define	MB25_IS_GSB 0x40 /* GOOD Symbol Bit */

#define	MB25_IS_HECECR 0x20 /* HEC error cell received */

#define	MB25_IS_SCR 0x10 /* "Short Cell" Received */

#define	MB25_IS_TPE 0x08 /* Trnamsit Parity Error */

#define	MB25_IS_RSCC 0x04 /* Receive Signal Condition change */

#define	MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */

#define	MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */

#define	MB25_DC_FTXCD 0x80 /* Force TxClav deassert */

#define	MB25_DC_RXCOS 0x40 /* RxClav operation select */

#define	MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */

#define	MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */

#define	MB25_DC_IXPE 0x08 /* Insert xmit payload error */

#define	MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */

#define	MB25_DC_LB_MASK 0x03 /* Loopback control mask */

#define	MB25_DC_LL 0x03 /* Line Loopback */

#define	MB25_DC_PL 0x02 /* PHY Loopback */

#define	MB25_DC_NM 0x00

#define	FE_MASK 0x00F0

#define	FE_MULTI_MODE 0x0000

#define	FE_SINGLE_MODE 0x0010

#define	FE_UTP_OPTION 0x0020

#define	FE_25MBIT_PHY 0x0040

#define	FE_DS3_PHY 0x0080 /* DS3 */

#define	FE_E3_PHY 0x0090 /* E3 */

#define	SUNI_PM7345_T suni_pm7345_t

#define	SUNI_PM7345 0x20 /* Suni chip type */

#define	SUNI_PM5346 0x30 /* Suni chip type */

#define	SUNI_PM7345_CLB 0x01 /* Cell loopback */

#define	SUNI_PM7345_PLB 0x02 /* Payload loopback */

#define	SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */

#define	SUNI_PM7345_LLB 0x80 /* Line loopback */

#define	SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */

#define	SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */

#define	SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */

#define	SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */

#define	SUNI_DS3_COFAE 0x80 /* Enable change of frame align */

#define	SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */

#define	SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */

#define	SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/

#define	SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */

#define	SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/

#define	SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */

#define	SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */

#define	SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */

#define	SUNI_DS3_REDV 0x40 /* DS3 RED state */

#define	SUNI_DS3_CBITV 0x20 /* Application ID channel state */

#define	SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/

#define	SUNI_DS3_IDLV 0x08 /* Idle signal state */

#define	SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/

#define	SUNI_DS3_OOFV 0x02 /* Out of frame state */

#define	SUNI_DS3_LOSV 0x01 /* Loss of signal state */

#define	SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */

#define	SUNI_E3_LOSI 0x20 /* Loss of signal intr status */

#define	SUNI_E3_LCVI 0x10 /* Line code violation intr */

#define	SUNI_E3_COFAI 0x08 /* Change of frame align intr */

#define	SUNI_E3_OOFI 0x04 /* Out of frame intr status */

#define	SUNI_E3_LOS 0x02 /* Loss of signal state */

#define	SUNI_E3_OOF 0x01 /* Out of frame state */

#define	SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/

#define	SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */

#define	SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/

#define	SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */

#define	SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */

#define	SUNI_DS3_HCSADD 0x20 /* Add coset poly */

#define	SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/

#define	SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */

#define	SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */

#define	SUNI_DS3_OOCDV 0x02 /* Cell delineation state */

#define	SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */

#define	SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */

#define	SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */

#define	SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */

#define	SUNI_DS3_OOCDI 0x10 /* SYNC state */

#define	SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */

#define	SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */

#define	SUNI_DS3_FOVRI 0x02 /* FIFO overrun */

#define	SUNI_DS3_FUDRI 0x01 /* FIFO underrun */

#define	MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/

#define	MEM_SIZE_128K 0x0000 /* board has 128k buffer */

#define	MEM_SIZE_512K 0x0001 /* board has 512K of buffer */

#define	MEM_SIZE_1M 0x0002 /* board has 1M of buffer */

#define	FE_MASK 0x00F0 /* mask of 4 bits defining FE type */

#define	FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */

#define	FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */

#define	FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */

#define	NOVRAM_SIZE 64

#define	CMD_LEN 10

#define	EXTEND 0x100

#define	IAWRITE 0x140

#define	IAREAD 0x180

#define	ERASE 0x1c0

#define	EWDS 0x00

#define	WRAL 0x10

#define	ERAL 0x20

#define	EWEN 0x30

#define	NVCE 0x02

#define	NVSK 0x01

#define	NVDO 0x08

#define	NVDI 0x04

#define	CFG_AND(val)

#define	CFG_OR(val)

#define	NVRAM_CMD(cmd)

#define	NVRAM_CLR_CE {CFG_AND(~NVCE)}

#define	NVRAM_CLKOUT(bitval)

#define	NVRAM_CLKIN(value)

Typedefs
typedef struct IA_CMDBUF *	PIA_CMDBUF

typedef volatile u_int	freg_t

typedef u_int	rreg_t

typedef struct _ffredn_t	ffredn_t

typedef struct _rfredn_t	rfredn_t

typedef struct srv_cls_param	srv_cls_param_t

typedef struct ia_rtn_q	IARTN_Q

typedef struct _SUNI_STATS_	IA_SUNI_STATS

typedef struct iadev_priv	IADEV

Enumerations
enum	ia_suni { SUNI_MASTER_RESET = 0x000, SUNI_MASTER_CONFIG = 0x004, SUNI_MASTER_INTR_STAT = 0x008, SUNI_RESERVED1 = 0x00c, SUNI_MASTER_CLK_MONITOR = 0x010, SUNI_MASTER_CONTROL = 0x014, SUNI_RSOP_CONTROL = 0x040, SUNI_RSOP_STATUS = 0x044, SUNI_RSOP_SECTION_BIP8L = 0x048, SUNI_RSOP_SECTION_BIP8M = 0x04c, SUNI_TSOP_CONTROL = 0x050, SUNI_TSOP_DIAG = 0x054, SUNI_RLOP_CS = 0x060, SUNI_RLOP_INTR = 0x064, SUNI_RLOP_LINE_BIP24L = 0x068, SUNI_RLOP_LINE_BIP24 = 0x06c, SUNI_RLOP_LINE_BIP24M = 0x070, SUNI_RLOP_LINE_FEBEL = 0x074, SUNI_RLOP_LINE_FEBE = 0x078, SUNI_RLOP_LINE_FEBEM = 0x07c, SUNI_TLOP_CONTROL = 0x080, SUNI_TLOP_DISG = 0x084, SUNI_RPOP_CS = 0x0c0, SUNI_RPOP_INTR = 0x0c4, SUNI_RPOP_RESERVED = 0x0c8, SUNI_RPOP_INTR_ENA = 0x0cc, SUNI_RPOP_PATH_SIG = 0x0dc, SUNI_RPOP_BIP8L = 0x0e0, SUNI_RPOP_BIP8M = 0x0e4, SUNI_RPOP_FEBEL = 0x0e8, SUNI_RPOP_FEBEM = 0x0ec, SUNI_TPOP_CNTRL_DAIG = 0x100, SUNI_TPOP_POINTER_CTRL = 0x104, SUNI_TPOP_SOURCER_CTRL = 0x108, SUNI_TPOP_ARB_PRTL = 0x114, SUNI_TPOP_ARB_PRTM = 0x118, SUNI_TPOP_RESERVED2 = 0x11c, SUNI_TPOP_PATH_SIG = 0x120, SUNI_TPOP_PATH_STATUS = 0x124, SUNI_RACP_CS = 0x140, SUNI_RACP_INTR = 0x144, SUNI_RACP_HDR_PATTERN = 0x148, SUNI_RACP_HDR_MASK = 0x14c, SUNI_RACP_CORR_HCS = 0x150, SUNI_RACP_UNCORR_HCS = 0x154, SUNI_TACP_CONTROL = 0x180, SUNI_TACP_IDLE_HDR_PAT = 0x184, SUNI_TACP_IDLE_PAY_PAY = 0x188, SUNI_RESERVED_TEST = 0x204 }

enum	ia_mb25 { MB25_MASTER_CTRL = 0x00, MB25_INTR_STATUS = 0x04, MB25_DIAG_CONTROL = 0x08, MB25_LED_HEC = 0x0c, MB25_LOW_BYTE_COUNTER = 0x10, MB25_HIGH_BYTE_COUNTER = 0x14 }

enum	suni_pm7345 { SUNI_CONFIG = 0x000, SUNI_INTR_ENBL = 0x004, SUNI_INTR_STAT = 0x008, SUNI_CONTROL = 0x00c, SUNI_ID_RESET = 0x010, SUNI_DATA_LINK_CTRL = 0x014, SUNI_RBOC_CONF_INTR_ENBL = 0x018, SUNI_RBOC_STAT = 0x01c, SUNI_DS3_FRM_CFG = 0x020, SUNI_DS3_FRM_INTR_ENBL = 0x024, SUNI_DS3_FRM_INTR_STAT = 0x028, SUNI_DS3_FRM_STAT = 0x02c, SUNI_RFDL_CFG = 0x030, SUNI_RFDL_ENBL_STAT = 0x034, SUNI_RFDL_STAT = 0x038, SUNI_RFDL_DATA = 0x03c, SUNI_PMON_CHNG = 0x040, SUNI_PMON_INTR_ENBL_STAT = 0x044, SUNI_PMON_LCV_EVT_CNT_LSB = 0x050, SUNI_PMON_LCV_EVT_CNT_MSB = 0x054, SUNI_PMON_FBE_EVT_CNT_LSB = 0x058, SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c, SUNI_PMON_SEZ_DET_CNT_LSB = 0x060, SUNI_PMON_SEZ_DET_CNT_MSB = 0x064, SUNI_PMON_PE_EVT_CNT_LSB = 0x068, SUNI_PMON_PE_EVT_CNT_MSB = 0x06c, SUNI_PMON_PPE_EVT_CNT_LSB = 0x070, SUNI_PMON_PPE_EVT_CNT_MSB = 0x074, SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078, SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c, SUNI_DS3_TRAN_CFG = 0x080, SUNI_DS3_TRAN_DIAG = 0x084, SUNI_XFDL_CFG = 0x090, SUNI_XFDL_INTR_ST = 0x094, SUNI_XFDL_XMIT_DATA = 0x098, SUNI_XBOC_CODE = 0x09c, SUNI_SPLR_CFG = 0x0a0, SUNI_SPLR_INTR_EN = 0x0a4, SUNI_SPLR_INTR_ST = 0x0a8, SUNI_SPLR_STATUS = 0x0ac, SUNI_SPLT_CFG = 0x0b0, SUNI_SPLT_CNTL = 0x0b4, SUNI_SPLT_DIAG_G1 = 0x0b8, SUNI_SPLT_F1 = 0x0bc, SUNI_CPPM_LOC_METERS = 0x0c0, SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4, SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8, SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc, SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0, SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4, SUNI_CPPM_FEBE_CNT_LSB = 0x0d8, SUNI_CPPM_FEBE_CNT_MSB = 0x0dc, SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0, SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4, SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8, SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec, SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0, SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4, SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8, SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc, SUNI_RXCP_CTRL = 0x100, SUNI_RXCP_FCTRL = 0x104, SUNI_RXCP_INTR_EN_STS = 0x108, SUNI_RXCP_IDLE_PAT_H1 = 0x10c, SUNI_RXCP_IDLE_PAT_H2 = 0x110, SUNI_RXCP_IDLE_PAT_H3 = 0x114, SUNI_RXCP_IDLE_PAT_H4 = 0x118, SUNI_RXCP_IDLE_MASK_H1 = 0x11c, SUNI_RXCP_IDLE_MASK_H2 = 0x120, SUNI_RXCP_IDLE_MASK_H3 = 0x124, SUNI_RXCP_IDLE_MASK_H4 = 0x128, SUNI_RXCP_CELL_PAT_H1 = 0x12c, SUNI_RXCP_CELL_PAT_H2 = 0x130, SUNI_RXCP_CELL_PAT_H3 = 0x134, SUNI_RXCP_CELL_PAT_H4 = 0x138, SUNI_RXCP_CELL_MASK_H1 = 0x13c, SUNI_RXCP_CELL_MASK_H2 = 0x140, SUNI_RXCP_CELL_MASK_H3 = 0x144, SUNI_RXCP_CELL_MASK_H4 = 0x148, SUNI_RXCP_HCS_CS = 0x14c, SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150, SUNI_TXCP_CTRL = 0x160, SUNI_TXCP_INTR_EN_STS = 0x164, SUNI_TXCP_IDLE_PAT_H1 = 0x168, SUNI_TXCP_IDLE_PAT_H2 = 0x16c, SUNI_TXCP_IDLE_PAT_H3 = 0x170, SUNI_TXCP_IDLE_PAT_H4 = 0x174, SUNI_TXCP_IDLE_PAT_H5 = 0x178, SUNI_TXCP_IDLE_PAYLOAD = 0x17c, SUNI_E3_FRM_FRAM_OPTIONS = 0x180, SUNI_E3_FRM_MAINT_OPTIONS = 0x184, SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188, SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c, SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190, SUNI_E3_FRM_MAINT_INTR_IND = 0x194, SUNI_E3_FRM_MAINT_STAT = 0x198, SUNI_RESERVED4 = 0x19c, SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0, SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4, SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8, SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac, SUNI_TTB_CTRL = 0x1b0, SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4, SUNI_TTB_IND_ADDR = 0x1b8, SUNI_TTB_IND_DATA = 0x1bc, SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0, SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4, SUNI_MASTER_TEST = 0x200 }

Macro Definition Documentation

#define AAL5 0x0100

Definition at line 591 of file iphase.h.

#define AAL5_PKT_REASSEMBLED 0x4000

Definition at line 622 of file iphase.h.

#define AAL5_PKT_TERMINATED 0x8000

Definition at line 623 of file iphase.h.

#define ABR 0x8000

Definition at line 235 of file iphase.h.

#define ABR_EN 0x0800

Definition at line 410 of file iphase.h.

#define ABR_LKUP_BASE 0x1e

Definition at line 522 of file iphase.h.

#define ABR_SBPTR_BASE 0x22

Definition at line 425 of file iphase.h.

#define ABR_SBVC 0x75

Definition at line 471 of file iphase.h.

#define ABR_SCHED_TABLE 0x5000 /* ABR Table */

Definition at line 575 of file iphase.h.

#define ABR_STATE 0x02

Definition at line 258 of file iphase.h.

#define ABR_VC_TABLE 0x8000 /* ABR VC Table */

Definition at line 606 of file iphase.h.

#define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */

Definition at line 576 of file iphase.h.

#define ABRNEXTLINK 0x78

Definition at line 473 of file iphase.h.

#define ABRUBR_ARB 0x04

Definition at line 413 of file iphase.h.

#define ABRWQ_BASE 0x26

Definition at line 427 of file iphase.h.

#define ABRWQ_RDPTR 0x70

Definition at line 467 of file iphase.h.

#define ABRWQ_WRPTR 0x6f

Definition at line 466 of file iphase.h.

#define APP_CRC32 0x0400

Definition at line 592 of file iphase.h.

#define ATDFCODE 2 /* 0 - 15 */

Definition at line 181 of file iphase.h.

#define ATM_DESC ( skb ) (skb->protocol)

Definition at line 128 of file iphase.h.

#define Boolean ( x ) ((x) ? 1 : 0)

Definition at line 157 of file iphase.h.

#define BUF_SIZE 0x42

Definition at line 540 of file iphase.h.

#define BYTE_CNT 0x3

Definition at line 585 of file iphase.h.

#define CBR 0x0000

Definition at line 237 of file iphase.h.

#define CBR_EN 0x2000

Definition at line 409 of file iphase.h.

#define CBR_PTR_BASE 0x20

Definition at line 424 of file iphase.h.

#define CBR_SCHED_TABLE 0x1800 /* CBR Table */

Definition at line 572 of file iphase.h.

#define CBR_TAB_BEG 0x2c

Definition at line 431 of file iphase.h.

#define CBR_TAB_END 0x2d

Definition at line 432 of file iphase.h.

#define CBR_VC 0x73

Definition at line 470 of file iphase.h.

#define CC_FIFO_ED_ADR 0x35

Definition at line 536 of file iphase.h.

#define CC_FIFO_RD_PTR 0x36

Definition at line 537 of file iphase.h.

#define CC_FIFO_ST_ADR 0x34

Definition at line 535 of file iphase.h.

#define CC_FIFO_WR_PTR 0x37

Definition at line 538 of file iphase.h.

#define CDFCODE 6

Definition at line 180 of file iphase.h.

#define CELL_CNTR0_NC 0x8c

Definition at line 544 of file iphase.h.

#define CELL_CNTR1_NC 0x8d

Definition at line 545 of file iphase.h.

#define CELL_CTR0 0x0c

Definition at line 501 of file iphase.h.

#define CELL_CTR1 0x0d

Definition at line 502 of file iphase.h.

#define CELL_CTR_HIGH_AUTO 0x49

Definition at line 454 of file iphase.h.

#define CELL_CTR_HIGH_NOAUTO 0xc9

Definition at line 455 of file iphase.h.

#define CELL_CTR_LO_AUTO 0x4a

Definition at line 456 of file iphase.h.

#define CELL_CTR_LO_NOAUTO 0xca

Definition at line 457 of file iphase.h.

#define CFG_AND ( val )

Value:

{ \
		u32 t; \
        t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
        t &= (val); \
        writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
    }

Definition at line 1368 of file iphase.h.

#define CFG_OR ( val )

Value:

{ \
		u32 t; \
        t =  readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
        t |= (val); \
        writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
    }

Definition at line 1382 of file iphase.h.

#define CMD_LEN 10

Definition at line 1326 of file iphase.h.

#define CMPL_INT 0x1000

Definition at line 593 of file iphase.h.

#define COMP_EN 0x4000

Definition at line 408 of file iphase.h.

#define CRC_APPEND 0x40 /* for status field - CRC-32 append */

Definition at line 257 of file iphase.h.

#define CTRL_25MBPHY 0x10000000

Definition at line 363 of file iphase.h.

#define CTRL_B128 0x00000200

Definition at line 373 of file iphase.h.

#define CTRL_B16 0x00000020

Definition at line 377 of file iphase.h.

#define CTRL_B32 0x00000040

Definition at line 376 of file iphase.h.

#define CTRL_B48 0x00000080

Definition at line 375 of file iphase.h.

#define CTRL_B64 0x00000100

Definition at line 374 of file iphase.h.

#define CTRL_B8 0x00000010

Definition at line 378 of file iphase.h.

#define CTRL_CSPREEMPT 0x00002000

Definition at line 372 of file iphase.h.

#define CTRL_DLERMASK 0x00080000

Definition at line 368 of file iphase.h.

#define CTRL_DLETMASK 0x00100000

Definition at line 367 of file iphase.h.

#define CTRL_ENCMBMEM 0x08000000

Definition at line 364 of file iphase.h.

#define CTRL_ENOFFSEG 0x01000000

Definition at line 365 of file iphase.h.

#define CTRL_ERRMASK 0x00400000

Definition at line 366 of file iphase.h.

#define CTRL_FE_RST 0x80000000

Definition at line 361 of file iphase.h.

#define CTRL_FEMASK 0x00040000

Definition at line 369 of file iphase.h.

#define CTRL_LED 0x40000000

Definition at line 362 of file iphase.h.

#define CTRL_REASSMASK 0x00010000

Definition at line 371 of file iphase.h.

#define CTRL_SEGMASK 0x00020000

Definition at line 370 of file iphase.h.

#define DbgPrint ( A )

Definition at line 121 of file iphase.h.

#define DESC_MODE 0x0

Definition at line 583 of file iphase.h.

#define DEV_LABEL "ia"

Definition at line 170 of file iphase.h.

#define DFL_RX_BUF_SZ 10240 /* 10k buffers */

Definition at line 189 of file iphase.h.

#define DFL_RX_BUFFERS

Value:

50 /* number of packet buffers for Rx

- descriptor 0 unused */

Definition at line 190 of file iphase.h.

#define DFL_TX_BUF_SZ 10240 /* 10 K buffers */

Definition at line 185 of file iphase.h.

#define DFL_TX_BUFFERS

Value:

50 /* number of packet buffers for Tx

- descriptor 0 unused */

Definition at line 186 of file iphase.h.

#define DLE_ENTRIES 256

Definition at line 273 of file iphase.h.

#define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)

Definition at line 276 of file iphase.h.

#define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */

Definition at line 274 of file iphase.h.

#define DRP_PKT_CNTR 0x04

Definition at line 498 of file iphase.h.

#define DRP_PKT_CNTR_NC 0x84

Definition at line 542 of file iphase.h.

#define EOM_EN 0x0800

Definition at line 590 of file iphase.h.

#define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */

Definition at line 330 of file iphase.h.

#define ERAL 0x20

Definition at line 1349 of file iphase.h.

#define ERASE 0x1c0

Definition at line 1345 of file iphase.h.

#define ERR_CNTR 0x05

Definition at line 499 of file iphase.h.

#define ERR_CNTR_NC 0x85

Definition at line 543 of file iphase.h.

#define EWDS 0x00

Definition at line 1347 of file iphase.h.

#define EWEN 0x30

Definition at line 1350 of file iphase.h.

#define EXCEPTION_Q 0x5e00 /* Exception Queue */

Definition at line 601 of file iphase.h.

#define EXCP_Q_ED_ADR 0x2d

Definition at line 532 of file iphase.h.

#define EXCP_Q_RD_PTR 0x2e

Definition at line 533 of file iphase.h.

#define EXCP_Q_ST_ADR 0x2c

Definition at line 531 of file iphase.h.

#define EXCP_Q_WR_PTR 0x2f

Definition at line 534 of file iphase.h.

#define EXCPQ_EMPTY 0x0040

Definition at line 548 of file iphase.h.

#define EXT_VC_TABLE 0x6000 /* Extended VC Table */

Definition at line 577 of file iphase.h.

#define EXTEND 0x100

Definition at line 1342 of file iphase.h.

#define FE_25MBIT_PHY 0x0040

Definition at line 1110 of file iphase.h.

#define FE_DS3_PHY 0x0080 /* DS3 */

Definition at line 1111 of file iphase.h.

#define FE_E3_PHY 0x0090 /* E3 */

Definition at line 1112 of file iphase.h.

#define FE_MASK 0x00F0

Definition at line 1320 of file iphase.h.

#define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */

Definition at line 1320 of file iphase.h.

#define FE_MULTI_MODE 0x0000

Definition at line 1321 of file iphase.h.

#define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */

Definition at line 1321 of file iphase.h.

#define FE_SINGLE_MODE 0x0010

Definition at line 1322 of file iphase.h.

#define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */

Definition at line 1322 of file iphase.h.

#define FE_UTP_OPTION 0x0020

Definition at line 1323 of file iphase.h.

#define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */

Definition at line 1323 of file iphase.h.

#define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */

Definition at line 602 of file iphase.h.

#define FREEQ_ED_ADR 0x25

Definition at line 524 of file iphase.h.

#define FREEQ_EMPTY 0x0004

Definition at line 550 of file iphase.h.

#define FREEQ_RD_PTR 0x26

Definition at line 525 of file iphase.h.

#define FREEQ_ST_ADR 0x24

Definition at line 523 of file iphase.h.

#define FREEQ_WR_PTR 0x27

Definition at line 526 of file iphase.h.

#define FRTT 1

Definition at line 175 of file iphase.h.

#define IA_CMD 0x7749

Definition at line 134 of file iphase.h.

#define IA_DLED 1

Definition at line 130 of file iphase.h.

#define IA_SKB_STATE ( skb ) (skb->protocol)

Definition at line 129 of file iphase.h.

#define IA_TX_DONE 2

Definition at line 131 of file iphase.h.

#define IAREAD 0x180

Definition at line 1344 of file iphase.h.

#define IAWRITE 0x140

Definition at line 1343 of file iphase.h.

#define ICR 100000

Definition at line 172 of file iphase.h.

#define IDLEHEADHI 0x00

Definition at line 396 of file iphase.h.

#define IDLEHEADLO 0x01

Definition at line 397 of file iphase.h.

#define IF_ABR ( A )

Definition at line 119 of file iphase.h.

#define IF_CBR ( A )

Definition at line 117 of file iphase.h.

#define IF_COPY_OVER ( A )

Definition at line 107 of file iphase.h.

#define IF_DIS_INTR ( A )

Definition at line 110 of file iphase.h.

#define IF_EN_INTR ( A )

Definition at line 111 of file iphase.h.

#define IF_ERR ( A )

Definition at line 116 of file iphase.h.

#define IF_EVENT ( A )

Definition at line 122 of file iphase.h.

#define IF_HANG ( A )

Definition at line 108 of file iphase.h.

#define IF_IADBG ( f ) if (IADebugFlag & (f))

Definition at line 70 of file iphase.h.

#define IF_IADBG_ABR 0x00400000

Definition at line 65 of file iphase.h.

#define IF_IADBG_CBR 0x00100000

Definition at line 63 of file iphase.h.

#define IF_IADBG_DESC 0x01000000

Definition at line 66 of file iphase.h.

#define IF_IADBG_DIS_INTR 0x00001000

Definition at line 59 of file iphase.h.

#define IF_IADBG_EN_INTR 0x00002000

Definition at line 60 of file iphase.h.

#define IF_IADBG_ERR 0x00000100

Definition at line 57 of file iphase.h.

#define IF_IADBG_EVENT 0x00000200

Definition at line 58 of file iphase.h.

#define IF_IADBG_INIT_ADAPTER 0x00000001

Definition at line 49 of file iphase.h.

#define IF_IADBG_INTR 0x00000020

Definition at line 54 of file iphase.h.

#define IF_IADBG_LOUD 0x00004000

Definition at line 61 of file iphase.h.

#define IF_IADBG_QUERY_INFO 0x00000008

Definition at line 52 of file iphase.h.

#define IF_IADBG_RESET 0x04000000

Definition at line 68 of file iphase.h.

#define IF_IADBG_RX 0x00000004

Definition at line 51 of file iphase.h.

#define IF_IADBG_RXPKT 0x00000080

Definition at line 56 of file iphase.h.

#define IF_IADBG_SHUTDOWN 0x00000010

Definition at line 53 of file iphase.h.

#define IF_IADBG_SUNI_STAT 0x02000000

Definition at line 67 of file iphase.h.

#define IF_IADBG_TX 0x00000002

Definition at line 50 of file iphase.h.

#define IF_IADBG_TXPKT 0x00000040

Definition at line 55 of file iphase.h.

#define IF_IADBG_UBR 0x00200000

Definition at line 64 of file iphase.h.

#define IF_IADBG_VERY_LOUD 0x00008000

Definition at line 62 of file iphase.h.

#define IF_INIT ( A )

Definition at line 103 of file iphase.h.

#define IF_INIT_ADAPTER ( A )

Definition at line 102 of file iphase.h.

#define IF_INTR ( A )

Definition at line 109 of file iphase.h.

#define IF_LOUD ( A )

Definition at line 100 of file iphase.h.

#define IF_PVC_CHKPKT ( A )

Definition at line 105 of file iphase.h.

#define IF_QUERY_INFO ( A )

Definition at line 106 of file iphase.h.

#define IF_RX ( A )

Definition at line 113 of file iphase.h.

#define IF_RXPKT ( A )

Definition at line 124 of file iphase.h.

#define IF_SHUTDOWN ( A )

Definition at line 120 of file iphase.h.

#define IF_SUNI_STAT ( A )

Definition at line 104 of file iphase.h.

#define IF_TX ( A )

Definition at line 112 of file iphase.h.

#define IF_TXDEBUG ( A )

Definition at line 114 of file iphase.h.

#define IF_TXPKT ( A )

Definition at line 123 of file iphase.h.

#define IF_UBR ( A )

Definition at line 118 of file iphase.h.

#define IF_VC ( A )

Definition at line 115 of file iphase.h.

#define IF_VERY_LOUD ( A )

Definition at line 101 of file iphase.h.

#define IGN_RAW_FL 0x0004

Definition at line 482 of file iphase.h.

#define INPH_IA_DEV ( d ) ((IADEV *) (d)->dev_data)

Definition at line 1055 of file iphase.h.

#define INPH_IA_VCC ( v ) ((struct ia_vcc *) (v)->dev_data)

Definition at line 1056 of file iphase.h.

#define INTRVL_CNTR 0x18

Definition at line 518 of file iphase.h.

#define IPHASE5575_BUS_CONTROL_REG 0x00

Definition at line 345 of file iphase.h.

#define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */

Definition at line 336 of file iphase.h.

#define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */

Definition at line 346 of file iphase.h.

#define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */

Definition at line 358 of file iphase.h.

#define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c

Definition at line 355 of file iphase.h.

#define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b

Definition at line 354 of file iphase.h.

#define IPHASE5575_CELL_FIFO_READ_PTR 0x0d

Definition at line 356 of file iphase.h.

#define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e

Definition at line 357 of file iphase.h.

#define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000

Definition at line 339 of file iphase.h.

#define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */

Definition at line 353 of file iphase.h.

#define IPHASE5575_EXT_RESET 0x04

Definition at line 350 of file iphase.h.

#define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000

Definition at line 341 of file iphase.h.

#define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000

Definition at line 337 of file iphase.h.

#define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE

Definition at line 340 of file iphase.h.

#define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */

Definition at line 351 of file iphase.h.

#define IPHASE5575_MAC1 0x02

Definition at line 347 of file iphase.h.

#define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/

Definition at line 349 of file iphase.h.

#define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */

Definition at line 352 of file iphase.h.

#define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000

Definition at line 335 of file iphase.h.

#define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000

Definition at line 342 of file iphase.h.

#define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000

Definition at line 338 of file iphase.h.

#define IPHASE5575_REV 0x03

Definition at line 348 of file iphase.h.

#define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */

Definition at line 561 of file iphase.h.

#define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */

Definition at line 563 of file iphase.h.

#define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */

Definition at line 560 of file iphase.h.

#define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */

Definition at line 562 of file iphase.h.

#define isprint ( a ) ((a >=' ')&&(a <= '~'))

Definition at line 127 of file iphase.h.

#define MAC1_LEN 4

Definition at line 331 of file iphase.h.

#define MAC2_LEN 2

Definition at line 332 of file iphase.h.

#define MAIN_VC_TABLE 0x8000 /* Main VC Table */

Definition at line 578 of file iphase.h.

#define MAX_ATM_155 352768

Definition at line 401 of file iphase.h.

#define MAXRATE 0x02

Definition at line 398 of file iphase.h.

#define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */

Definition at line 1096 of file iphase.h.

#define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */

Definition at line 1094 of file iphase.h.

#define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */

Definition at line 1099 of file iphase.h.

#define MB25_DC_IXPE 0x08 /* Insert xmit payload error */

Definition at line 1098 of file iphase.h.

#define MB25_DC_LB_MASK 0x03 /* Loopback control mask */

Definition at line 1100 of file iphase.h.

#define MB25_DC_LL 0x03 /* Line Loopback */

Definition at line 1102 of file iphase.h.

#define MB25_DC_NM 0x00

Definition at line 1104 of file iphase.h.

#define MB25_DC_PL 0x02 /* PHY Loopback */

Definition at line 1103 of file iphase.h.

#define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */

Definition at line 1097 of file iphase.h.

#define MB25_DC_RXCOS 0x40 /* RxClav operation select */

Definition at line 1095 of file iphase.h.

#define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */

Definition at line 1083 of file iphase.h.

#define MB25_IS_HECECR 0x20 /* HEC error cell received */

Definition at line 1084 of file iphase.h.

#define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */

Definition at line 1088 of file iphase.h.

#define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */

Definition at line 1089 of file iphase.h.

#define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */

Definition at line 1087 of file iphase.h.

#define MB25_IS_SCR 0x10 /* "Short Cell" Received */

Definition at line 1085 of file iphase.h.

#define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */

Definition at line 1086 of file iphase.h.

#define MB25_MC_DREC 0x40 /* Discard receive cell errors */

Definition at line 1072 of file iphase.h.

#define MB25_MC_DRIC 0x08 /* Discard receive idle cells */

Definition at line 1075 of file iphase.h.

#define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */

Definition at line 1073 of file iphase.h.

#define MB25_MC_ENABLED 0x01 /* Enable interrupt */

Definition at line 1078 of file iphase.h.

#define MB25_MC_HALTTX 0x04 /* Halt Tx */

Definition at line 1076 of file iphase.h.

#define MB25_MC_TDPC 0x10 /* Transmit data parity check */

Definition at line 1074 of file iphase.h.

#define MB25_MC_UMS 0x02 /* UTOPIA mode select */

Definition at line 1077 of file iphase.h.

#define MB25_MC_UPLO 0x80 /* UPLO */

Definition at line 1071 of file iphase.h.

#define MCR 0

Definition at line 173 of file iphase.h.

#define MEM_SIZE_128K 0x0000 /* board has 128k buffer */

Definition at line 1315 of file iphase.h.

#define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */

Definition at line 1317 of file iphase.h.

#define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */

Definition at line 1316 of file iphase.h.

#define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/

Definition at line 1314 of file iphase.h.

#define MEM_VALID 0xfffffff0 /* mask base address with this */

Definition at line 162 of file iphase.h.

#define MEMDUMP 0x01

Definition at line 145 of file iphase.h.

#define MEMDUMP_DEV 0x1

Definition at line 149 of file iphase.h.

#define MEMDUMP_FFL 0x4

Definition at line 151 of file iphase.h.

#define MEMDUMP_REASSREG 0x3

Definition at line 150 of file iphase.h.

#define MEMDUMP_SEGREG 0x2

Definition at line 148 of file iphase.h.

#define MODE_REG 0x00

Definition at line 480 of file iphase.h.

#define MODE_REG_0 0x45

Definition at line 443 of file iphase.h.

#define MODE_REG_1 0x46

Definition at line 446 of file iphase.h.

#define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/

Definition at line 447 of file iphase.h.

#define MRM 3

Definition at line 802 of file iphase.h.

#define NEWDN 0x6a

Definition at line 463 of file iphase.h.

#define NEWVC 0x6b

Definition at line 464 of file iphase.h.

#define NEXTDESC 0x59

Definition at line 460 of file iphase.h.

#define NEXTVC 0x5a

Definition at line 461 of file iphase.h.

#define NO_AAL5_PKT 0x0000

Definition at line 621 of file iphase.h.

#define NOVRAM_SIZE 64

Definition at line 1325 of file iphase.h.

#define NR_VCI 1024 /* number of VCIs */

Definition at line 158 of file iphase.h.

#define NR_VCI_4K 4096 /* number of VCIs */

Definition at line 160 of file iphase.h.

#define NR_VCI_4K_LD 12 /* log2(NR_VCI) */

Definition at line 161 of file iphase.h.

#define NR_VCI_LD 10 /* log2(NR_VCI) */

Definition at line 159 of file iphase.h.

#define NRMCODE 5 /* 0 - 7 */

Definition at line 178 of file iphase.h.

#define NUM_RX_EXCP 32

Definition at line 618 of file iphase.h.

#define NVCE 0x02

Definition at line 1357 of file iphase.h.

#define NVDI 0x04

Definition at line 1360 of file iphase.h.

#define NVDO 0x08

Definition at line 1359 of file iphase.h.

#define NVRAM_CLKIN ( value )

Value:

{ \
		u32 _t; \
        CFG_OR(NVSK); \
        CFG_AND(~NVSK); \
        _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
        value = (_t & NVDO) ? 1 : 0; \
    }

Definition at line 1439 of file iphase.h.

#define NVRAM_CLKOUT ( bitval )

Value:

{ \
        CFG_AND(~NVDI); \
        CFG_OR((bitval) ? NVDI : 0); \
        CFG_OR(NVSK); \
        CFG_AND( ~NVSK); \
    }

Definition at line 1425 of file iphase.h.

#define NVRAM_CLR_CE {CFG_AND(~NVCE)}

Definition at line 1416 of file iphase.h.

#define NVRAM_CMD ( cmd )

Value:

{ \
        int i; \
		u_short c = cmd; \
        CFG_AND(~(NVCE|NVSK)); \
        CFG_OR(NVCE); \
        for (i=0; i<CMD_LEN; i++) { \
            NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
            c <<= 1; \
        } \
    }

Definition at line 1399 of file iphase.h.

#define NVSK 0x01

Definition at line 1358 of file iphase.h.

#define PCI_DEVICE_ID_IPHASE_5575 0x0008

Definition at line 168 of file iphase.h.

#define PCI_VENDOR_ID_IPHASE 0x107e

Definition at line 165 of file iphase.h.

#define PCQ_ED_ADR 0x29

Definition at line 528 of file iphase.h.

#define PCQ_EMPTY 0x0010

Definition at line 549 of file iphase.h.

#define PCQ_RD_PTR 0x2a

Definition at line 529 of file iphase.h.

#define PCQ_ST_ADR 0x28

Definition at line 527 of file iphase.h.

#define PCQ_WR_PTR 0x2b

Definition at line 530 of file iphase.h.

#define PCR 207692

Definition at line 171 of file iphase.h.

#define PHY_BASE IPHASE5575_FRONT_END_REG_BASE

Definition at line 630 of file iphase.h.

#define PKT_COMP_Q 0x6800 /* Packet Complete Queue */

Definition at line 603 of file iphase.h.

#define PKT_RDY_Q 0x1400 /* Packet Ready Queue */

Definition at line 571 of file iphase.h.

#define PKT_START_HI 0x4

Definition at line 586 of file iphase.h.

#define PKT_START_LO 0x5

Definition at line 587 of file iphase.h.

#define PKT_TM_CNT 0x16

Definition at line 516 of file iphase.h.

#define PROTOCOL_ID 0x01

Definition at line 484 of file iphase.h.

#define PRQ_ED_ADR 0x31

Definition at line 434 of file iphase.h.

#define PRQ_RD_PTR 0x32

Definition at line 435 of file iphase.h.

#define PRQ_ST_ADR 0x30

Definition at line 433 of file iphase.h.

#define PRQ_WR_PTR 0x33

Definition at line 436 of file iphase.h.

#define PSLOTCNT 0x5d

Definition at line 462 of file iphase.h.

#define R_ONLINE 0x0002 /* (i)chip is online */

Definition at line 481 of file iphase.h.

#define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE

Definition at line 629 of file iphase.h.

#define RATE155 0x64b1

Definition at line 400 of file iphase.h.

#define RATE25 0x5f9d

Definition at line 402 of file iphase.h.

#define RAW_BASE_ADR 0x08

Definition at line 500 of file iphase.h.

#define RAW_PKT 0xc000

Definition at line 624 of file iphase.h.

#define RDF 4

Definition at line 177 of file iphase.h.

#define READ_REG 0x5

Definition at line 152 of file iphase.h.

#define REASS_ABR 0x2000

Definition at line 625 of file iphase.h.

#define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE

Definition at line 632 of file iphase.h.

#define REASS_COMMAND_REG 0x0f

Definition at line 503 of file iphase.h.

#define REASS_DESC_BASE 0x10

Definition at line 512 of file iphase.h.

#define REASS_INTR_STATUS_REG 0x03

Definition at line 486 of file iphase.h.

#define REASS_MASK_REG 0x02

Definition at line 485 of file iphase.h.

#define REASS_QUEUE_BASE 0x13

Definition at line 515 of file iphase.h.

#define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */

Definition at line 187 of file iphase.h.

#define REASS_TABLE 0x7000 /* Reassembly Table */

Definition at line 604 of file iphase.h.

#define REASS_TABLE_BASE 0x12

Definition at line 514 of file iphase.h.

#define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */

Definition at line 610 of file iphase.h.

#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE

Definition at line 628 of file iphase.h.

#define RESET_CELL_CNTR 0x00f8

Definition at line 509 of file iphase.h.

#define RESET_DRP_PKT_CNTR 0x00f1

Definition at line 507 of file iphase.h.

#define RESET_ERR_CNTR 0x00f2

Definition at line 508 of file iphase.h.

#define RESET_REASS 0x0055

Definition at line 505 of file iphase.h.

#define RESET_REASS_ALL_REGS 0x00ff

Definition at line 510 of file iphase.h.

#define RESET_REASS_STATE 0x00aa

Definition at line 506 of file iphase.h.

#define RESET_SEG 0x0055

Definition at line 420 of file iphase.h.

#define RESET_SEG_STATE 0x00aa

Definition at line 421 of file iphase.h.

#define RESET_TX_CELL_CTR 0x00cc

Definition at line 422 of file iphase.h.

#define RIF 2

Definition at line 176 of file iphase.h.

#define RM_TYPE 0x05

Definition at line 414 of file iphase.h.

#define RM_TYPE_4_0 0x0100

Definition at line 416 of file iphase.h.

#define RX_ACT 0x8000

Definition at line 612 of file iphase.h.

#define RX_CELL_CTR_OF 0x1000

Definition at line 490 of file iphase.h.

#define RX_CER 0x0008

Definition at line 615 of file iphase.h.

#define RX_CNG 0x0040

Definition at line 614 of file iphase.h.

#define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */

Definition at line 599 of file iphase.h.

#define RX_DESC_TABLE_SZ

Value:

736 /* Number of entries in the Receive

Buffer Descriptor Table */

Definition at line 607 of file iphase.h.

#define RX_ERR_CTR_OF 0x4000

Definition at line 489 of file iphase.h.

#define RX_EXCP_RCVD 0x0008

Definition at line 494 of file iphase.h.

#define RX_EXCPQ_FL 0x0080

Definition at line 492 of file iphase.h.

#define RX_FREEQ_EMPT 0x0200

Definition at line 491 of file iphase.h.

#define RX_OFL 0x0002

Definition at line 617 of file iphase.h.

#define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */

Definition at line 188 of file iphase.h.

#define RX_PKT_CTR_OF 0x8000

Definition at line 488 of file iphase.h.

#define RX_PKT_RCVD 0x0004

Definition at line 495 of file iphase.h.

#define RX_PTE 0x0004

Definition at line 616 of file iphase.h.

#define RX_RAW_RCVD 0x0001

Definition at line 496 of file iphase.h.

#define RX_RAWQ_FL 0x0010

Definition at line 493 of file iphase.h.

#define RX_VC_TABLE 0x7800 /* VC Table */

Definition at line 605 of file iphase.h.

#define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */

Definition at line 609 of file iphase.h.

#define RX_VPVC 0x4000

Definition at line 613 of file iphase.h.

#define SBPTR 0x6c

Definition at line 465 of file iphase.h.

#define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */

Definition at line 579 of file iphase.h.

#define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE

Definition at line 631 of file iphase.h.

#define SEG_COMMAND_REG 0x17

Definition at line 418 of file iphase.h.

#define SEG_DESC_BASE 0x41

Definition at line 442 of file iphase.h.

#define SEG_INTR_STATUS_REG 0x47

Definition at line 449 of file iphase.h.

#define SEG_MASK_REG 0x48

Definition at line 450 of file iphase.h.

#define SEG_QUEUE_BASE 0x40

Definition at line 441 of file iphase.h.

#define STAT_ADPARCK 0x20000000

Definition at line 382 of file iphase.h.

#define STAT_CMEMSIZ 0xc0000000

Definition at line 381 of file iphase.h.

#define STAT_DLERINT 0x00000008

Definition at line 387 of file iphase.h.

#define STAT_DLETINT 0x00000010

Definition at line 386 of file iphase.h.

#define STAT_ERRINT 0x00000040

Definition at line 384 of file iphase.h.

#define STAT_FEINT 0x00000004

Definition at line 388 of file iphase.h.

#define STAT_MARKINT 0x00000020

Definition at line 385 of file iphase.h.

#define STAT_REASSINT 0x00000001

Definition at line 390 of file iphase.h.

#define STAT_RESVD 0x1fffff80

Definition at line 383 of file iphase.h.

#define STAT_SEGINT 0x00000002

Definition at line 389 of file iphase.h.

#define STATE_REG 0x38

Definition at line 539 of file iphase.h.

#define STPARMS 0x03

Definition at line 404 of file iphase.h.

#define STPARMS_1K 0x008c

Definition at line 405 of file iphase.h.

#define STPARMS_2K 0x0049

Definition at line 406 of file iphase.h.

#define STPARMS_4K 0x0026

Definition at line 407 of file iphase.h.

#define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */

Definition at line 1260 of file iphase.h.

#define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/

Definition at line 1253 of file iphase.h.

#define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/

Definition at line 1265 of file iphase.h.

#define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */

Definition at line 1294 of file iphase.h.

#define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */

Definition at line 1250 of file iphase.h.

#define SUNI_DS3_CBITV 0x20 /* Application ID channel state */

Definition at line 1262 of file iphase.h.

#define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */

Definition at line 1307 of file iphase.h.

#define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */

Definition at line 1248 of file iphase.h.

#define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */

Definition at line 1295 of file iphase.h.

#define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/

Definition at line 1251 of file iphase.h.

#define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/

Definition at line 1263 of file iphase.h.

#define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */

Definition at line 1304 of file iphase.h.

#define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */

Definition at line 1297 of file iphase.h.

#define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */

Definition at line 1308 of file iphase.h.

#define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */

Definition at line 1309 of file iphase.h.

#define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/

Definition at line 1293 of file iphase.h.

#define SUNI_DS3_HCSADD 0x20 /* Add coset poly */

Definition at line 1292 of file iphase.h.

#define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */

Definition at line 1291 of file iphase.h.

#define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */

Definition at line 1303 of file iphase.h.

#define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */

Definition at line 1290 of file iphase.h.

#define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */

Definition at line 1252 of file iphase.h.

#define SUNI_DS3_IDLV 0x08 /* Idle signal state */

Definition at line 1264 of file iphase.h.

#define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */

Definition at line 1255 of file iphase.h.

#define SUNI_DS3_LOSV 0x01 /* Loss of signal state */

Definition at line 1267 of file iphase.h.

#define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */

Definition at line 1302 of file iphase.h.

#define SUNI_DS3_OOCDI 0x10 /* SYNC state */

Definition at line 1305 of file iphase.h.

#define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */

Definition at line 1296 of file iphase.h.

#define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */

Definition at line 1254 of file iphase.h.

#define SUNI_DS3_OOFV 0x02 /* Out of frame state */

Definition at line 1266 of file iphase.h.

#define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */

Definition at line 1249 of file iphase.h.

#define SUNI_DS3_REDV 0x40 /* DS3 RED state */

Definition at line 1261 of file iphase.h.

#define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */

Definition at line 1306 of file iphase.h.

#define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/

Definition at line 1283 of file iphase.h.

#define SUNI_E3_COFAI 0x08 /* Change of frame align intr */

Definition at line 1275 of file iphase.h.

#define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */

Definition at line 1272 of file iphase.h.

#define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/

Definition at line 1285 of file iphase.h.

#define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */

Definition at line 1284 of file iphase.h.

#define SUNI_E3_LCVI 0x10 /* Line code violation intr */

Definition at line 1274 of file iphase.h.

#define SUNI_E3_LOS 0x02 /* Loss of signal state */

Definition at line 1277 of file iphase.h.

#define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */

Definition at line 1273 of file iphase.h.

#define SUNI_E3_OOF 0x01 /* Out of frame state */

Definition at line 1278 of file iphase.h.

#define SUNI_E3_OOFI 0x04 /* Out of frame intr status */

Definition at line 1276 of file iphase.h.

#define SUNI_LOSV 0x04

Definition at line 886 of file iphase.h.

#define SUNI_PM5346 0x30 /* Suni chip type */

Definition at line 1233 of file iphase.h.

#define SUNI_PM7345 0x20 /* Suni chip type */

Definition at line 1232 of file iphase.h.

#define SUNI_PM7345_CLB 0x01 /* Cell loopback */

Definition at line 1237 of file iphase.h.

#define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */

Definition at line 1239 of file iphase.h.

#define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */

Definition at line 1241 of file iphase.h.

#define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */

Definition at line 1243 of file iphase.h.

#define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */

Definition at line 1244 of file iphase.h.

#define SUNI_PM7345_LLB 0x80 /* Line loopback */

Definition at line 1240 of file iphase.h.

#define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */

Definition at line 1242 of file iphase.h.

#define SUNI_PM7345_PLB 0x02 /* Payload loopback */

Definition at line 1238 of file iphase.h.

#define SUNI_PM7345_T suni_pm7345_t

Definition at line 1231 of file iphase.h.

#define T_ONLINE 0x0002 /* (i)chipSAR is online */

Definition at line 444 of file iphase.h.

#define TABLE_ADDRESS	(	db,
		dn,
		to
	)	(((unsigned long)(db & 0x04)) << 16) \| (dn << 5) \| (to << 1)

Definition at line 595 of file iphase.h.

#define TBE 1000

Definition at line 174 of file iphase.h.

#define TCQ_ED_ADR 0x35

Definition at line 438 of file iphase.h.

#define TCQ_NOT_EMPTY

Value:

0x1000 /* this can be used for both the interrupt

status registers as well as the mask register */

Definition at line 452 of file iphase.h.

#define TCQ_RD_PTR 0x36

Definition at line 439 of file iphase.h.

#define TCQ_ST_ADR 0x34

Definition at line 437 of file iphase.h.

#define TCQ_WR_PTR 0x37

Definition at line 440 of file iphase.h.

#define TMOUT_INDX 0x19

Definition at line 519 of file iphase.h.

#define TMOUT_RANGE 0x17

Definition at line 517 of file iphase.h.

#define TRANSMIT_DONE 0x0200

Definition at line 451 of file iphase.h.

#define TRMCODE 3 /* 0 - 7 */

Definition at line 179 of file iphase.h.

#define TX_COMP_Q 0x1000 /* Transmit Complete Queue */

Definition at line 570 of file iphase.h.

#define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */

Definition at line 569 of file iphase.h.

#define TX_DESC_TABLE_SZ

Value:

128 /* Number of entries in the Transmit

Buffer Descriptor Table */

Definition at line 580 of file iphase.h.

#define TX_DLE_PSI 0x0001

Definition at line 275 of file iphase.h.

#define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */

Definition at line 184 of file iphase.h.

#define UBR 0xc000

Definition at line 236 of file iphase.h.

#define UBR_EN 0x0400

Definition at line 411 of file iphase.h.

#define UBR_SBPTR_BASE 0x23

Definition at line 426 of file iphase.h.

#define UBR_SBVC 0x76

Definition at line 472 of file iphase.h.

#define UBR_SCHED_TABLE 0x3000 /* UBR Table */

Definition at line 573 of file iphase.h.

#define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */

Definition at line 574 of file iphase.h.

#define UBRNEXTLINK 0x79

Definition at line 474 of file iphase.h.

#define UBRWQ_BASE 0x27

Definition at line 428 of file iphase.h.

#define UBRWQ_RDPTR 0x72

Definition at line 469 of file iphase.h.

#define UBRWQ_WRPTR 0x71

Definition at line 468 of file iphase.h.

#define UIOLI 0x80

Definition at line 256 of file iphase.h.

#define VC_ABR 0x02

Definition at line 851 of file iphase.h.

#define VC_ACTIVE 0x01

Definition at line 850 of file iphase.h.

#define VC_INDEX 0x1

Definition at line 584 of file iphase.h.

#define VC_LKUP_BASE 0x11

Definition at line 513 of file iphase.h.

#define VC_UBR 0x04

Definition at line 852 of file iphase.h.

#define VCT_BASE 0x28

Definition at line 429 of file iphase.h.

#define VCTE_BASE 0x29

Definition at line 430 of file iphase.h.

#define VP_FILTER 0x1d

Definition at line 521 of file iphase.h.

#define VP_LKUP_BASE 0x1c

Definition at line 520 of file iphase.h.

#define VP_TABLE 0x5c00 /* VP Table */

Definition at line 600 of file iphase.h.

#define VP_TABLE_SZ 256 /* Number of entries in VPTable */

Definition at line 608 of file iphase.h.

#define WAKE_DBG_WAIT 0x6

Definition at line 153 of file iphase.h.

#define WRAL 0x10

Definition at line 1348 of file iphase.h.

#define XTRA_RM_OFFSET 0x44

Definition at line 541 of file iphase.h.

Typedef Documentation

typedef struct _ffredn_t ffredn_t

typedef volatile u_int freg_t

Definition at line 634 of file iphase.h.

typedef struct _SUNI_STATS_ IA_SUNI_STATS

typedef struct iadev_priv IADEV

typedef struct ia_rtn_q IARTN_Q

typedef struct IA_CMDBUF * PIA_CMDBUF

typedef struct _rfredn_t rfredn_t

typedef u_int rreg_t

Definition at line 635 of file iphase.h.

typedef struct srv_cls_param srv_cls_param_t

Enumeration Type Documentation

enum ia_mb25

Enumerator:

MB25_MASTER_CTRL
MB25_INTR_STATUS
MB25_DIAG_CONTROL
MB25_LED_HEC
MB25_LOW_BYTE_COUNTER
MB25_HIGH_BYTE_COUNTER

Definition at line 1059 of file iphase.h.

enum ia_suni

Enumerator:

SUNI_MASTER_RESET
SUNI_MASTER_CONFIG
SUNI_MASTER_INTR_STAT
SUNI_RESERVED1
SUNI_MASTER_CLK_MONITOR
SUNI_MASTER_CONTROL
SUNI_RSOP_CONTROL
SUNI_RSOP_STATUS
SUNI_RSOP_SECTION_BIP8L
SUNI_RSOP_SECTION_BIP8M
SUNI_TSOP_CONTROL
SUNI_TSOP_DIAG
SUNI_RLOP_CS
SUNI_RLOP_INTR
SUNI_RLOP_LINE_BIP24L
SUNI_RLOP_LINE_BIP24
SUNI_RLOP_LINE_BIP24M
SUNI_RLOP_LINE_FEBEL
SUNI_RLOP_LINE_FEBE
SUNI_RLOP_LINE_FEBEM
SUNI_TLOP_CONTROL
SUNI_TLOP_DISG
SUNI_RPOP_CS
SUNI_RPOP_INTR
SUNI_RPOP_RESERVED
SUNI_RPOP_INTR_ENA
SUNI_RPOP_PATH_SIG
SUNI_RPOP_BIP8L
SUNI_RPOP_BIP8M
SUNI_RPOP_FEBEL
SUNI_RPOP_FEBEM
SUNI_TPOP_CNTRL_DAIG
SUNI_TPOP_POINTER_CTRL
SUNI_TPOP_SOURCER_CTRL
SUNI_TPOP_ARB_PRTL
SUNI_TPOP_ARB_PRTM
SUNI_TPOP_RESERVED2
SUNI_TPOP_PATH_SIG
SUNI_TPOP_PATH_STATUS
SUNI_RACP_CS
SUNI_RACP_INTR
SUNI_RACP_HDR_PATTERN
SUNI_RACP_HDR_MASK
SUNI_RACP_CORR_HCS
SUNI_RACP_UNCORR_HCS
SUNI_TACP_CONTROL
SUNI_TACP_IDLE_HDR_PAT
SUNI_TACP_IDLE_PAY_PAY
SUNI_RESERVED_TEST

Definition at line 887 of file iphase.h.

enum suni_pm7345

Enumerator:

SUNI_CONFIG
SUNI_INTR_ENBL
SUNI_INTR_STAT
SUNI_CONTROL
SUNI_ID_RESET
SUNI_DATA_LINK_CTRL
SUNI_RBOC_CONF_INTR_ENBL
SUNI_RBOC_STAT
SUNI_DS3_FRM_CFG
SUNI_DS3_FRM_INTR_ENBL
SUNI_DS3_FRM_INTR_STAT
SUNI_DS3_FRM_STAT
SUNI_RFDL_CFG
SUNI_RFDL_ENBL_STAT
SUNI_RFDL_STAT
SUNI_RFDL_DATA
SUNI_PMON_CHNG
SUNI_PMON_INTR_ENBL_STAT
SUNI_PMON_LCV_EVT_CNT_LSB
SUNI_PMON_LCV_EVT_CNT_MSB
SUNI_PMON_FBE_EVT_CNT_LSB
SUNI_PMON_FBE_EVT_CNT_MSB
SUNI_PMON_SEZ_DET_CNT_LSB
SUNI_PMON_SEZ_DET_CNT_MSB
SUNI_PMON_PE_EVT_CNT_LSB
SUNI_PMON_PE_EVT_CNT_MSB
SUNI_PMON_PPE_EVT_CNT_LSB
SUNI_PMON_PPE_EVT_CNT_MSB
SUNI_PMON_FEBE_EVT_CNT_LSB
SUNI_PMON_FEBE_EVT_CNT_MSB
SUNI_DS3_TRAN_CFG
SUNI_DS3_TRAN_DIAG
SUNI_XFDL_CFG
SUNI_XFDL_INTR_ST
SUNI_XFDL_XMIT_DATA
SUNI_XBOC_CODE
SUNI_SPLR_CFG
SUNI_SPLR_INTR_EN
SUNI_SPLR_INTR_ST
SUNI_SPLR_STATUS
SUNI_SPLT_CFG
SUNI_SPLT_CNTL
SUNI_SPLT_DIAG_G1
SUNI_SPLT_F1
SUNI_CPPM_LOC_METERS
SUNI_CPPM_CHG_OF_CPPM_PERF_METR
SUNI_CPPM_B1_ERR_CNT_LSB
SUNI_CPPM_B1_ERR_CNT_MSB
SUNI_CPPM_FRAMING_ERR_CNT_LSB
SUNI_CPPM_FRAMING_ERR_CNT_MSB
SUNI_CPPM_FEBE_CNT_LSB
SUNI_CPPM_FEBE_CNT_MSB
SUNI_CPPM_HCS_ERR_CNT_LSB
SUNI_CPPM_HCS_ERR_CNT_MSB
SUNI_CPPM_IDLE_UN_CELL_CNT_LSB
SUNI_CPPM_IDLE_UN_CELL_CNT_MSB
SUNI_CPPM_RCV_CELL_CNT_LSB
SUNI_CPPM_RCV_CELL_CNT_MSB
SUNI_CPPM_XMIT_CELL_CNT_LSB
SUNI_CPPM_XMIT_CELL_CNT_MSB
SUNI_RXCP_CTRL
SUNI_RXCP_FCTRL
SUNI_RXCP_INTR_EN_STS
SUNI_RXCP_IDLE_PAT_H1
SUNI_RXCP_IDLE_PAT_H2
SUNI_RXCP_IDLE_PAT_H3
SUNI_RXCP_IDLE_PAT_H4
SUNI_RXCP_IDLE_MASK_H1
SUNI_RXCP_IDLE_MASK_H2
SUNI_RXCP_IDLE_MASK_H3
SUNI_RXCP_IDLE_MASK_H4
SUNI_RXCP_CELL_PAT_H1
SUNI_RXCP_CELL_PAT_H2
SUNI_RXCP_CELL_PAT_H3
SUNI_RXCP_CELL_PAT_H4
SUNI_RXCP_CELL_MASK_H1
SUNI_RXCP_CELL_MASK_H2
SUNI_RXCP_CELL_MASK_H3
SUNI_RXCP_CELL_MASK_H4
SUNI_RXCP_HCS_CS
SUNI_RXCP_LCD_CNT_THRESHOLD
SUNI_TXCP_CTRL
SUNI_TXCP_INTR_EN_STS
SUNI_TXCP_IDLE_PAT_H1
SUNI_TXCP_IDLE_PAT_H2
SUNI_TXCP_IDLE_PAT_H3
SUNI_TXCP_IDLE_PAT_H4
SUNI_TXCP_IDLE_PAT_H5
SUNI_TXCP_IDLE_PAYLOAD
SUNI_E3_FRM_FRAM_OPTIONS
SUNI_E3_FRM_MAINT_OPTIONS
SUNI_E3_FRM_FRAM_INTR_ENBL
SUNI_E3_FRM_FRAM_INTR_IND_STAT
SUNI_E3_FRM_MAINT_INTR_ENBL
SUNI_E3_FRM_MAINT_INTR_IND
SUNI_E3_FRM_MAINT_STAT
SUNI_RESERVED4
SUNI_E3_TRAN_FRAM_OPTIONS
SUNI_E3_TRAN_STAT_DIAG_OPTIONS
SUNI_E3_TRAN_BIP_8_ERR_MASK
SUNI_E3_TRAN_MAINT_ADAPT_OPTS
SUNI_TTB_CTRL
SUNI_TTB_TRAIL_TRACE_ID_STAT
SUNI_TTB_IND_ADDR
SUNI_TTB_IND_DATA
SUNI_TTB_EXP_PAYLOAD_TYPE
SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT
SUNI_MASTER_TEST

Definition at line 1115 of file iphase.h.

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation