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9 #ifndef __BFIN_ASM_SERIAL_H__
10 #define __BFIN_ASM_SERIAL_H__
12 #include <linux/serial_core.h>
14 #include <mach/anomaly.h>
15 #include <mach/bfin_serial.h>
17 #if defined(CONFIG_BFIN_UART0_CTSRTS) || \
18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 defined(CONFIG_BFIN_UART3_CTSRTS)
21 # if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
22 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
24 # define CONFIG_SERIAL_BFIN_CTSRTS
38 #ifndef BFIN_UART_BF54X_STYLE
41 #ifdef CONFIG_SERIAL_BFIN_DMA
48 unsigned int tx_dma_channel;
49 unsigned int rx_dma_channel;
51 #elif ANOMALY_05000363
52 unsigned int anomaly_threshold;
54 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
55 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
61 #ifdef BFIN_UART_BF60X_STYLE
67 #define UMOD_IRDA 0x20
68 #define UMOD_MASK 0x30
69 #define WLS(x) (((x-5) & 0x03) << 8)
70 #define WLS_MASK 0x300
80 #define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
81 #define FCPOL 0x400000
82 #define RPOLC 0x800000
83 #define TPOLC 0x1000000
84 #define MRTS 0x2000000
85 #define XOFF 0x4000000
86 #define ARTS 0x8000000
87 #define ACTS 0x10000000
88 #define RFIT 0x20000000
89 #define RFRT 0x40000000
109 #define EDBO 0x80000000
114 #define WLS(x) (((x)-5) & 0x03)
115 #define WLS_MASK 0x03
123 #define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
140 #define LOOP_ENA 0x10
152 #define UMOD_IRDA 0x02
153 #define UMOD_MASK 0x02
170 #if defined(BFIN_UART_BF60X_STYLE)
171 # define OFFSET_REDIV 0x00
172 # define OFFSET_CTL 0x04
173 # define OFFSET_STAT 0x08
174 # define OFFSET_SCR 0x0C
175 # define OFFSET_CLK 0x10
176 # define OFFSET_IER 0x14
177 # define OFFSET_IER_SET 0x18
178 # define OFFSET_IER_CLEAR 0x1C
179 # define OFFSET_RBR 0x20
180 # define OFFSET_THR 0x24
181 #elif defined(BFIN_UART_BF54X_STYLE)
182 # define OFFSET_DLL 0x00
183 # define OFFSET_DLH 0x04
184 # define OFFSET_GCTL 0x08
185 # define OFFSET_LCR 0x0C
186 # define OFFSET_MCR 0x10
187 # define OFFSET_LSR 0x14
188 # define OFFSET_MSR 0x18
189 # define OFFSET_SCR 0x1C
190 # define OFFSET_IER_SET 0x20
191 # define OFFSET_IER_CLEAR 0x24
192 # define OFFSET_THR 0x28
193 # define OFFSET_RBR 0x2C
195 # define OFFSET_THR 0x00
196 # define OFFSET_RBR 0x00
197 # define OFFSET_DLL 0x00
198 # define OFFSET_DLH 0x04
199 # define OFFSET_IER 0x04
200 # define OFFSET_IIR 0x08
201 # define OFFSET_LCR 0x0C
202 # define OFFSET_MCR 0x10
203 # define OFFSET_LSR 0x14
204 # define OFFSET_MSR 0x18
205 # define OFFSET_SCR 0x1C
206 # define OFFSET_GCTL 0x24
215 #define __BFP(m) u16 m; u16 __pad_##m
217 #if defined(BFIN_UART_BF60X_STYLE)
233 #elif defined(BFIN_UART_BF54X_STYLE)
270 #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
277 #ifdef BFIN_UART_BF60X_STYLE
279 #define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
280 #define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
281 #define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
282 #define UART_GET_GCTL(p) UART_GET_CTL(p)
283 #define UART_GET_LCR(p) UART_GET_CTL(p)
284 #define UART_GET_MCR(p) UART_GET_CTL(p)
286 #define UART_GET_STAT(p) \
289 unsigned long flags; \
290 flags = hard_local_irq_save(); \
291 __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
292 hard_local_irq_restore(flags); \
296 #define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
298 #define UART_GET_MSR(p) UART_GET_STAT(p)
300 #define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
301 #define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
302 #define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
303 #define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
304 #define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
305 #define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
306 #define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
308 #define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
309 #define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
310 #define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
312 #define UART_CLEAR_DLAB(p)
313 #define UART_SET_DLAB(p)
315 #define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
316 #define UART_GET_LSR(p) UART_GET_STAT(p)
317 #define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
320 #define BFIN_UART_CTSRTS_HARD
321 #define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
322 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
323 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
324 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
325 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
326 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
330 #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
331 #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
332 #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
333 #define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
334 #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
335 #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
336 #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
337 #define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
339 #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
340 #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
341 #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
342 #define UART_PUT_CLK(p, v) do \
344 UART_PUT_DLL(p, v & 0xFF); \
345 UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
347 #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
348 #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
349 #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
351 #ifdef BFIN_UART_BF54X_STYLE
353 #define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
354 #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
355 #define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
357 #define UART_CLEAR_DLAB(p)
358 #define UART_SET_DLAB(p)
360 #define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
361 #define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
362 #define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
365 #define BFIN_UART_CTSRTS_HARD
366 #define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
367 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
368 #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
369 #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
370 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
371 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
375 #define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
376 #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
377 #define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
378 #define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
380 #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
381 #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
383 #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
384 #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
399 static inline void UART_CLEAR_LSR(
void *
p)
410 static inline void UART_PUT_LSR(
void *p,
uint16_t val)
416 #define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
417 #define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
418 #define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
419 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
420 #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
426 #ifndef BFIN_UART_TX_FIFO_SIZE
427 # define BFIN_UART_TX_FIFO_SIZE 2