#include <linux/serial_core.h>
#include <linux/spinlock.h>
#include <mach/anomaly.h>
#include <mach/bfin_serial.h>

Data Structures
struct	bfin_serial_port

struct	bfin_uart_regs

Macros
#define	WLS(x) (((x)-5) & 0x03) /* Word Length Select */

#define	WLS_MASK 0x03 /* Word length Select Mask */

#define	WLS_OFFSET 0 /* Word length Select Offset */

#define	STB 0x04 /* Stop Bits */

#define	PEN 0x08 /* Parity Enable */

#define	EPS 0x10 /* Even Parity Select */

#define	STP 0x20 /* Stick Parity */

#define	SB 0x40 /* Set Break */

#define	DLAB 0x80 /* Divisor Latch Access */

#define	LCR_MASK (SB \| STP \| EPS \| PEN \| STB \| WLS_MASK)

#define	DR 0x01 /* Data Ready */

#define	OE 0x02 /* Overrun Error */

#define	PE 0x04 /* Parity Error */

#define	FE 0x08 /* Framing Error */

#define	BI 0x10 /* Break Interrupt */

#define	THRE 0x20 /* THR Empty */

#define	TEMT 0x40 /* TSR and UART_THR Empty */

#define	TFI 0x80 /* Transmission Finished Indicator */

#define	XOFF 0x01 /* Transmitter Off */

#define	MRTS 0x02 /* Manual Request To Send */

#define	RFIT 0x04 /* Receive FIFO IRQ Threshold */

#define	RFRT 0x08 /* Receive FIFO RTS Threshold */

#define	LOOP_ENA 0x10 /* Loopback Mode Enable */

#define	FCPOL 0x20 /* Flow Control Pin Polarity */

#define	ARTS 0x40 /* Automatic Request To Send */

#define	ACTS 0x80 /* Automatic Clear To Send */

#define	SCTS 0x01 /* Sticky CTS */

#define	CTS 0x10 /* Clear To Send */

#define	RFCS 0x20 /* Receive FIFO Count Status */

#define	UCEN 0x01 /* Enable UARTx Clocks */

#define	UMOD_IRDA 0x02 /* Enable IrDA Mode */

#define	UMOD_MASK 0x02 /* Uart Mode Mask */

#define	TPOLC 0x04 /* IrDA TX Polarity Change */

#define	RPOLC 0x08 /* IrDA RX Polarity Change */

#define	FPE 0x10 /* Force Parity Error On Transmit */

#define	FFE 0x20 /* Force Framing Error On Transmit */

#define	ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */

#define	ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */

#define	ELSI 0x04 /* Enable RX Status Interrupt */

#define	EDSSI 0x08 /* Enable Modem Status Interrupt */

#define	EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */

#define	ETFI 0x20 /* Enable Transmission Finished Interrupt */

#define	ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */

#define	OFFSET_THR 0x00 /* Transmit Holding register */

#define	OFFSET_RBR 0x00 /* Receive Buffer register */

#define	OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */

#define	OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */

#define	OFFSET_IER 0x04 /* Interrupt Enable Register */

#define	OFFSET_IIR 0x08 /* Interrupt Identification Register */

#define	OFFSET_LCR 0x0C /* Line Control Register */

#define	OFFSET_MCR 0x10 /* Modem Control Register */

#define	OFFSET_LSR 0x14 /* Line Status Register */

#define	OFFSET_MSR 0x18 /* Modem Status Register */

#define	OFFSET_SCR 0x1C /* SCR Scratch Register */

#define	OFFSET_GCTL 0x24 /* Global Control Register */

#define	__BFP(m) u16 m; u16 __pad_##m

#define	port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)

#define	UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)

#define	UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)

#define	UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)

#define	UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) \| UART_GET_DLL(p))

#define	UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)

#define	UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)

#define	UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)

#define	UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)

#define	UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)

#define	UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)

#define	UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)

#define	UART_PUT_CLK(p, v)

#define	UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)

#define	UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)

#define	UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)

#define	UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))

#define	UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)

#define	UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)

#define	UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) \| (v))

#define	UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)

#define	UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) \| DLAB); SSYNC(); } while (0)

#define	get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)

#define	put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))

#define	UART_GET_CTS(x) gpio_get_value((x)->cts_pin)

#define	UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)

#define	UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)

#define	UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)

#define	UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)

#define	BFIN_UART_TX_FIFO_SIZE 2

Macro Definition Documentation

#define __BFP ( m ) u16 m; u16 __pad_##m

Definition at line 215 of file bfin_serial.h.

#define ACTS 0x80 /* Automatic Clear To Send */

Definition at line 143 of file bfin_serial.h.

#define ARTS 0x40 /* Automatic Request To Send */

Definition at line 142 of file bfin_serial.h.

#define BFIN_UART_TX_FIFO_SIZE 2

Definition at line 427 of file bfin_serial.h.

#define BI 0x10 /* Break Interrupt */

Definition at line 130 of file bfin_serial.h.

#define CTS 0x10 /* Clear To Send */

Definition at line 147 of file bfin_serial.h.

#define DLAB 0x80 /* Divisor Latch Access */

Definition at line 122 of file bfin_serial.h.

#define DR 0x01 /* Data Ready */

Definition at line 126 of file bfin_serial.h.

#define EDSSI 0x08 /* Enable Modem Status Interrupt */

Definition at line 165 of file bfin_serial.h.

#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */

Definition at line 166 of file bfin_serial.h.

#define ELSI 0x04 /* Enable RX Status Interrupt */

Definition at line 164 of file bfin_serial.h.

#define EPS 0x10 /* Even Parity Select */

Definition at line 119 of file bfin_serial.h.

#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */

Definition at line 162 of file bfin_serial.h.

#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */

Definition at line 168 of file bfin_serial.h.

#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */

Definition at line 163 of file bfin_serial.h.

#define ETFI 0x20 /* Enable Transmission Finished Interrupt */

Definition at line 167 of file bfin_serial.h.

#define FCPOL 0x20 /* Flow Control Pin Polarity */

Definition at line 141 of file bfin_serial.h.

#define FE 0x08 /* Framing Error */

Definition at line 129 of file bfin_serial.h.

#define FFE 0x20 /* Force Framing Error On Transmit */

Definition at line 157 of file bfin_serial.h.

#define FPE 0x10 /* Force Parity Error On Transmit */

Definition at line 156 of file bfin_serial.h.

#define get_lsr_cache ( uart ) (((struct bfin_serial_port *)(uart))->lsr)

Definition at line 383 of file bfin_serial.h.

#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)

Definition at line 123 of file bfin_serial.h.

#define LOOP_ENA 0x10 /* Loopback Mode Enable */

Definition at line 140 of file bfin_serial.h.

#define MRTS 0x02 /* Manual Request To Send */

Definition at line 137 of file bfin_serial.h.

#define OE 0x02 /* Overrun Error */

Definition at line 127 of file bfin_serial.h.

#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */

Definition at line 198 of file bfin_serial.h.

#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */

Definition at line 197 of file bfin_serial.h.

#define OFFSET_GCTL 0x24 /* Global Control Register */

Definition at line 206 of file bfin_serial.h.

#define OFFSET_IER 0x04 /* Interrupt Enable Register */

Definition at line 199 of file bfin_serial.h.

#define OFFSET_IIR 0x08 /* Interrupt Identification Register */

Definition at line 200 of file bfin_serial.h.

#define OFFSET_LCR 0x0C /* Line Control Register */

Definition at line 201 of file bfin_serial.h.

#define OFFSET_LSR 0x14 /* Line Status Register */

Definition at line 203 of file bfin_serial.h.

#define OFFSET_MCR 0x10 /* Modem Control Register */

Definition at line 202 of file bfin_serial.h.

#define OFFSET_MSR 0x18 /* Modem Status Register */

Definition at line 204 of file bfin_serial.h.

#define OFFSET_RBR 0x00 /* Receive Buffer register */

Definition at line 196 of file bfin_serial.h.

#define OFFSET_SCR 0x1C /* SCR Scratch Register */

Definition at line 205 of file bfin_serial.h.

#define OFFSET_THR 0x00 /* Transmit Holding register */

Definition at line 195 of file bfin_serial.h.

#define PE 0x04 /* Parity Error */

Definition at line 128 of file bfin_serial.h.

#define PEN 0x08 /* Parity Enable */

Definition at line 118 of file bfin_serial.h.

#define port_membase ( uart ) (((struct bfin_serial_port *)(uart))->port.membase)

Definition at line 270 of file bfin_serial.h.

#define put_lsr_cache	(	uart,
		v
	)	(((struct bfin_serial_port *)(uart))->lsr = (v))

Definition at line 384 of file bfin_serial.h.

#define RFCS 0x20 /* Receive FIFO Count Status */

Definition at line 148 of file bfin_serial.h.

#define RFIT 0x04 /* Receive FIFO IRQ Threshold */

Definition at line 138 of file bfin_serial.h.

#define RFRT 0x08 /* Receive FIFO RTS Threshold */

Definition at line 139 of file bfin_serial.h.

#define RPOLC 0x08 /* IrDA RX Polarity Change */

Definition at line 155 of file bfin_serial.h.

#define SB 0x40 /* Set Break */

Definition at line 121 of file bfin_serial.h.

#define SCTS 0x01 /* Sticky CTS */

Definition at line 146 of file bfin_serial.h.

#define STB 0x04 /* Stop Bits */

Definition at line 117 of file bfin_serial.h.

#define STP 0x20 /* Stick Parity */

Definition at line 120 of file bfin_serial.h.

#define TEMT 0x40 /* TSR and UART_THR Empty */

Definition at line 132 of file bfin_serial.h.

#define TFI 0x80 /* Transmission Finished Indicator */

Definition at line 133 of file bfin_serial.h.

#define THRE 0x20 /* THR Empty */

Definition at line 131 of file bfin_serial.h.

#define TPOLC 0x04 /* IrDA TX Polarity Change */

Definition at line 154 of file bfin_serial.h.

#define UART_CLEAR_DLAB ( p ) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)

Definition at line 380 of file bfin_serial.h.

#define UART_CLEAR_IER	(	p,
		v
	)	UART_PUT_IER(p, UART_GET_IER(p) & ~(v))

Definition at line 375 of file bfin_serial.h.

#define UART_DISABLE_INTS ( x ) UART_PUT_IER(x, 0)

Definition at line 420 of file bfin_serial.h.

#define UART_DISABLE_RTS ( x ) gpio_set_value((x)->rts_pin, 1)

Definition at line 417 of file bfin_serial.h.

#define UART_ENABLE_INTS	(	x,
		v
	)	UART_PUT_IER(x, v)

Definition at line 419 of file bfin_serial.h.

#define UART_ENABLE_RTS ( x ) gpio_set_value((x)->rts_pin, 0)

Definition at line 418 of file bfin_serial.h.

#define UART_GET_CHAR ( p ) bfin_read16(port_membase(p) + OFFSET_RBR)

Definition at line 330 of file bfin_serial.h.

#define UART_GET_CLK ( p ) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))

Definition at line 333 of file bfin_serial.h.

#define UART_GET_CTS ( x ) gpio_get_value((x)->cts_pin)

Definition at line 416 of file bfin_serial.h.

#define UART_GET_DLH ( p ) bfin_read16(port_membase(p) + OFFSET_DLH)

Definition at line 332 of file bfin_serial.h.

#define UART_GET_DLL ( p ) bfin_read16(port_membase(p) + OFFSET_DLL)

Definition at line 331 of file bfin_serial.h.

#define UART_GET_GCTL ( p ) bfin_read16(port_membase(p) + OFFSET_GCTL)

Definition at line 334 of file bfin_serial.h.

#define UART_GET_IER ( p ) bfin_read16(port_membase(p) + OFFSET_IER)

Definition at line 376 of file bfin_serial.h.

#define UART_GET_LCR ( p ) bfin_read16(port_membase(p) + OFFSET_LCR)

Definition at line 335 of file bfin_serial.h.

#define UART_GET_MCR ( p ) bfin_read16(port_membase(p) + OFFSET_MCR)

Definition at line 336 of file bfin_serial.h.

#define UART_GET_MSR ( p ) bfin_read16(port_membase(p) + OFFSET_MSR)

Definition at line 337 of file bfin_serial.h.

#define UART_PUT_CHAR	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_THR, v)

Definition at line 339 of file bfin_serial.h.

#define UART_PUT_CLK	(	p,
		v
	)

Value:

do \
{\
UART_PUT_DLL(p, v & 0xFF); \
UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);

Definition at line 342 of file bfin_serial.h.

#define UART_PUT_DLH	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_DLH, v)

Definition at line 341 of file bfin_serial.h.

#define UART_PUT_DLL	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_DLL, v)

Definition at line 340 of file bfin_serial.h.

#define UART_PUT_GCTL	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_GCTL, v)

Definition at line 347 of file bfin_serial.h.

#define UART_PUT_IER	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_IER, v)

Definition at line 377 of file bfin_serial.h.

#define UART_PUT_LCR	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_LCR, v)

Definition at line 348 of file bfin_serial.h.

#define UART_PUT_MCR	(	p,
		v
	)	bfin_write16(port_membase(p) + OFFSET_MCR, v)

Definition at line 349 of file bfin_serial.h.

#define UART_SET_DLAB ( p ) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)

Definition at line 381 of file bfin_serial.h.

#define UART_SET_IER	(	p,
		v
	)	UART_PUT_IER(p, UART_GET_IER(p) \| (v))

Definition at line 378 of file bfin_serial.h.

#define UCEN 0x01 /* Enable UARTx Clocks */

Definition at line 151 of file bfin_serial.h.

#define UMOD_IRDA 0x02 /* Enable IrDA Mode */

Definition at line 152 of file bfin_serial.h.

#define UMOD_MASK 0x02 /* Uart Mode Mask */

Definition at line 153 of file bfin_serial.h.

#define WLS ( x ) (((x)-5) & 0x03) /* Word Length Select */

Definition at line 114 of file bfin_serial.h.

#define WLS_MASK 0x03 /* Word length Select Mask */

Definition at line 115 of file bfin_serial.h.

#define WLS_OFFSET 0 /* Word length Select Offset */

Definition at line 116 of file bfin_serial.h.

#define XOFF 0x01 /* Transmitter Off */

Definition at line 136 of file bfin_serial.h.

Data Structures

Macros

Macro Definition Documentation