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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/atomic.h>#include <linux/device.h>#include <linux/kobject.h>#include <linux/completion.h>#include <linux/workqueue.h>#include <linux/debugfs.h>Go to the source code of this file.
Data Structures | |
| struct | edac_mc_layer |
| struct | dimm_info |
| struct | rank_info |
| struct | csrow_info |
| struct | errcount_attribute_data |
| struct | mem_ctl_info |
Enumerations | |
| enum | dev_type { DEV_UNKNOWN = 0, DEV_X1, DEV_X2, DEV_X4, DEV_X8, DEV_X16, DEV_X32, DEV_X64 } |
| enum | hw_event_mc_err_type { HW_EVENT_ERR_CORRECTED, HW_EVENT_ERR_UNCORRECTED, HW_EVENT_ERR_FATAL } |
| enum | mem_type { MEM_EMPTY = 0, MEM_RESERVED, MEM_UNKNOWN, MEM_FPM, MEM_EDO, MEM_BEDO, MEM_SDR, MEM_RDR, MEM_DDR, MEM_RDDR, MEM_RMBS, MEM_DDR2, MEM_FB_DDR2, MEM_RDDR2, MEM_XDR, MEM_DDR3, MEM_RDDR3 } |
| enum | edac_type { EDAC_UNKNOWN = 0, EDAC_NONE, EDAC_RESERVED, EDAC_PARITY, EDAC_EC, EDAC_SECDED, EDAC_S2ECD2ED, EDAC_S4ECD4ED, EDAC_S8ECD8ED, EDAC_S16ECD16ED } |
| enum | scrub_type { SCRUB_UNKNOWN = 0, SCRUB_NONE, SCRUB_SW_PROG, SCRUB_SW_SRC, SCRUB_SW_PROG_SRC, SCRUB_SW_TUNABLE, SCRUB_HW_PROG, SCRUB_HW_SRC, SCRUB_HW_PROG_SRC, SCRUB_HW_TUNABLE } |
| enum | edac_mc_layer_type { EDAC_MC_LAYER_BRANCH, EDAC_MC_LAYER_CHANNEL, EDAC_MC_LAYER_SLOT, EDAC_MC_LAYER_CHIP_SELECT } |
Functions | |
| int | edac_handler_set (void) |
| void | edac_atomic_assert_error (void) |
| struct bus_type * | edac_get_sysfs_subsys (void) |
| void | edac_put_sysfs_subsys (void) |
Variables | |
| int | edac_op_state |
| int | edac_err_assert |
| atomic_t | edac_handlers |
| struct bus_type | edac_subsys |
| #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) |
EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array for the element given by [layer0,layer1,layer2] position
: a struct edac_mc_layer array, describing how many elements were allocated for each layer : Number of layers at the array : layer0 position : layer1 position. Unused if n_layers < 2 : layer2 position. Unused if n_layers < 3
For 1 layer, this macro returns &var[layer0] - &var For 2 layers, this macro is similar to allocate a bi-dimensional array and to return "&var[layer0][layer1] - &var" For 3 layers, this macro is similar to allocate a tri-dimensional array and to return "&var[layer0][layer1][layer2] - &var"
A loop could be used here to make it more generic, but, as we only have 3 layers, this is a little faster. By design, layers can never be 0 or more than 3. If that ever happens, a NULL is returned, causing an OOPS during the memory allocation routine, with would point to the developer that he's doing something wrong.
| #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) |
| #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) |
| #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) |
| #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) |
| #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) |
| #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) |
| #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) |
| #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) |
| #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) |
| #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) |
| #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) |
| #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) |
| #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) |
| #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) |
| #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) |
| #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) |
| #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) |
| enum edac_mc_layer_type |
enum edac_mc_layer - memory controller hierarchy layer
: memory layer is named "branch" : memory layer is named "channel" : memory layer is named "slot" : memory layer is named "chip select"
This enum is used by the drivers to tell edac_mc_sysfs what name should be used when describing a memory stick location.
| enum edac_type |
enum edac-type - Error Detection and Correction capabilities and mode : Unknown if ECC is available : Doesn't support ECC : Reserved ECC type : Detects parity errors : Error Checking - no correction : Single bit error correction, Double detection : Chipkill x2 devices - do these exist? : Chipkill x4 devices : Chipkill x8 devices : Chipkill x16 devices
| enum hw_event_mc_err_type |
enum hw_event_mc_err_type - type of the detected error
: Corrected Error - Indicates that an ECC corrected error was detected : Uncorrected Error - Indicates an error that can't be corrected by ECC, but it is not fatal (maybe it is on an unused memory area, or the memory controller could recover from it for example, by re-trying the operation). : Fatal Error - Uncorrected error that could not be recovered.
| enum mem_type |
enum mem_type - memory types. For a more detailed reference, please see http://en.wikipedia.org/wiki/DRAM
Empty csrow : Reserved csrow type : Unknown csrow type : FPM - Fast Page Mode, used on systems up to 1995. : EDO - Extended data out, used on systems up to 1998. : BEDO - Burst Extended data out, an EDO variant. : SDR - Single data rate SDRAM http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory They use 3 pins for chip select: Pins 0 and 2 are for rank 0; pins 1 and 3 are for rank 1, if the memory is dual-rank. : Registered SDR SDRAM : Double data rate SDRAM http://en.wikipedia.org/wiki/DDR_SDRAM : Registered Double data rate SDRAM This is a variant of the DDR memories. A registered memory has a buffer inside it, hiding part of the memory details to the memory controller. : Rambus DRAM, used on a few Pentium III/IV controllers. : DDR2 RAM, as described at JEDEC JESD79-2F. Those memories are labed as "PC2-" instead of "PC" to differenciate from DDR. : Fully-Buffered DDR2, as described at JEDEC Std No. 205 and JESD206. Those memories are accessed per DIMM slot, and not by a chip select signal. : Registered DDR2 RAM This is a variant of the DDR2 memories. : Rambus XDR It is an evolution of the original RAMBUS memories, created to compete with DDR2. Weren't used on any x86 arch, but cell_edac PPC memory controller uses it. : DDR3 RAM : Registered DDR3 RAM This is a variant of the DDR3 memories.
| enum scrub_type |
enum scrub_type - scrubbing capabilities Unknown if scrubber is available : No scrubber : SW progressive (sequential) scrubbing : Software scrub only errors : Progressive software scrub from an error : Software scrub frequency is tunable : HW progressive (sequential) scrubbing : Hardware scrub only errors : Progressive hardware scrub from an error SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
Definition at line 48 of file edac_stub.c.
Definition at line 65 of file edac_stub.c.
Definition at line 36 of file edac_stub.c.
Definition at line 85 of file edac_stub.c.
| int edac_err_assert |
Definition at line 27 of file edac_stub.c.
| atomic_t edac_handlers |
Definition at line 24 of file edac_stub.c.
| int edac_op_state |
Definition at line 21 of file edac_stub.c.
Definition at line 58 of file edac_stub.c.
1.8.2