dbx500-prcmu.h File Reference

#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>
#include <linux/mfd/db8500-prcmu.h>

Go to the source code of this file.

Macros
#define	PRCMU_WAKEUP(_name)   (BIT(PRCMU_WAKEUP_INDEX_##_name))
#define	EPOD_ID_SVAMMDSP   0
#define	EPOD_ID_SVAPIPE   1
#define	EPOD_ID_SIAMMDSP   2
#define	EPOD_ID_SIAPIPE   3
#define	EPOD_ID_SGA   4
#define	EPOD_ID_B2R2_MCDE   5
#define	EPOD_ID_ESRAM12   6
#define	EPOD_ID_ESRAM34   7
#define	NUM_EPOD_ID   8
#define	EPOD_STATE_NO_CHANGE   0x00
#define	EPOD_STATE_OFF   0x01
#define	EPOD_STATE_RAMRET   0x02
#define	EPOD_STATE_ON_CLK_OFF   0x03
#define	EPOD_STATE_ON   0x04
#define	PRCMU_CLKSRC_CLK38M   0x00
#define	PRCMU_CLKSRC_ACLK   0x01
#define	PRCMU_CLKSRC_SYSCLK   0x02
#define	PRCMU_CLKSRC_LCDCLK   0x03
#define	PRCMU_CLKSRC_SDMMCCLK   0x04
#define	PRCMU_CLKSRC_TVCLK   0x05
#define	PRCMU_CLKSRC_TIMCLK   0x06
#define	PRCMU_CLKSRC_CLK009   0x07
#define	PRCMU_CLKSRC_SIAMMDSPCLK   0x40
#define	PRCMU_CLKSRC_I2CCLK   0x41
#define	PRCMU_CLKSRC_MSP02CLK   0x42
#define	PRCMU_CLKSRC_ARMPLL_OBSCLK   0x43
#define	PRCMU_CLKSRC_HSIRXCLK   0x44
#define	PRCMU_CLKSRC_HSITXCLK   0x45
#define	PRCMU_CLKSRC_ARMCLKFIX   0x46
#define	PRCMU_CLKSRC_HDMICLK   0x47
#define	ESRAM0_DEEP_SLEEP_STATE_OFF   1
#define	ESRAM0_DEEP_SLEEP_STATE_RET   2
#define	PRCMU_QOS_APE_OPP   1
#define	PRCMU_QOS_DDR_OPP   2
#define	PRCMU_QOS_ARM_OPP   3
#define	PRCMU_QOS_DEFAULT_VALUE   -1

Enumerations
enum	prcmu_wakeup_index {   PRCMU_WAKEUP_INDEX_RTC, PRCMU_WAKEUP_INDEX_RTT0, PRCMU_WAKEUP_INDEX_RTT1, PRCMU_WAKEUP_INDEX_HSI0,   PRCMU_WAKEUP_INDEX_HSI1, PRCMU_WAKEUP_INDEX_USB, PRCMU_WAKEUP_INDEX_ABB, PRCMU_WAKEUP_INDEX_ABB_FIFO,   PRCMU_WAKEUP_INDEX_ARM, PRCMU_WAKEUP_INDEX_CD_IRQ, NUM_PRCMU_WAKEUP_INDICES }
enum	prcmu_clock {   PRCMU_SGACLK, PRCMU_UARTCLK, PRCMU_MSP02CLK, PRCMU_MSP1CLK,   PRCMU_I2CCLK, PRCMU_SDMMCCLK, PRCMU_SPARE1CLK, PRCMU_SLIMCLK,   PRCMU_PER1CLK, PRCMU_PER2CLK, PRCMU_PER3CLK, PRCMU_PER5CLK,   PRCMU_PER6CLK, PRCMU_PER7CLK, PRCMU_LCDCLK, PRCMU_BMLCLK,   PRCMU_HSITXCLK, PRCMU_HSIRXCLK, PRCMU_HDMICLK, PRCMU_APEATCLK,   PRCMU_APETRACECLK, PRCMU_MCDECLK, PRCMU_IPI2CCLK, PRCMU_DSIALTCLK,   PRCMU_DMACLK, PRCMU_B2R2CLK, PRCMU_TVCLK, PRCMU_SSPCLK,   PRCMU_RNGCLK, PRCMU_UICCCLK, PRCMU_PWMCLK, PRCMU_IRDACLK,   PRCMU_IRRCCLK, PRCMU_SIACLK, PRCMU_SVACLK, PRCMU_ACLK,   PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, PRCMU_CDCLK, PRCMU_TIMCLK,   PRCMU_PLLSOC0, PRCMU_PLLSOC1, PRCMU_ARMSS, PRCMU_PLLDDR,   PRCMU_PLLDSI, PRCMU_DSI0CLK, PRCMU_DSI1CLK, PRCMU_DSI0ESCCLK,   PRCMU_DSI1ESCCLK, PRCMU_DSI2ESCCLK }
enum	ape_opp {   APE_OPP_INIT = 0x00, APE_NO_CHANGE = 0x01, APE_100_OPP = 0x02, APE_50_OPP = 0x03,   APE_50_PARTLY_25_OPP = 0xFF }
enum	arm_opp {   ARM_OPP_INIT = 0x00, ARM_NO_CHANGE = 0x01, ARM_100_OPP = 0x02, ARM_50_OPP = 0x03,   ARM_MAX_OPP = 0x04, ARM_MAX_FREQ100OPP = 0x05, ARM_EXTCLK = 0x07 }
enum	ddr_opp { DDR_100_OPP = 0x00, DDR_50_OPP = 0x01, DDR_25_OPP = 0x02 }
enum	ddr_pwrst { DDR_PWR_STATE_UNCHANGED = 0x00, DDR_PWR_STATE_ON = 0x01, DDR_PWR_STATE_OFFLOWLAT = 0x02, DDR_PWR_STATE_OFFHIGHLAT = 0x03 }

Macro Definition Documentation

#define EPOD_ID_B2R2_MCDE   5

Definition at line 52 of file dbx500-prcmu.h.

#define EPOD_ID_ESRAM12   6

Definition at line 53 of file dbx500-prcmu.h.

#define EPOD_ID_ESRAM34   7

Definition at line 54 of file dbx500-prcmu.h.

#define EPOD_ID_SGA   4

Definition at line 51 of file dbx500-prcmu.h.

#define EPOD_ID_SIAMMDSP   2

Definition at line 49 of file dbx500-prcmu.h.

#define EPOD_ID_SIAPIPE   3

Definition at line 50 of file dbx500-prcmu.h.

#define EPOD_ID_SVAMMDSP   0

Definition at line 47 of file dbx500-prcmu.h.

#define EPOD_ID_SVAPIPE   1

Definition at line 48 of file dbx500-prcmu.h.

#define EPOD_STATE_NO_CHANGE   0x00

Definition at line 66 of file dbx500-prcmu.h.

#define EPOD_STATE_OFF   0x01

Definition at line 67 of file dbx500-prcmu.h.

#define EPOD_STATE_ON   0x04

Definition at line 70 of file dbx500-prcmu.h.

#define EPOD_STATE_ON_CLK_OFF   0x03

Definition at line 69 of file dbx500-prcmu.h.

#define EPOD_STATE_RAMRET   0x02

Definition at line 68 of file dbx500-prcmu.h.

#define ESRAM0_DEEP_SLEEP_STATE_OFF   1

Definition at line 200 of file dbx500-prcmu.h.

#define ESRAM0_DEEP_SLEEP_STATE_RET   2

Definition at line 201 of file dbx500-prcmu.h.

#define NUM_EPOD_ID   8

Definition at line 55 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_ACLK   0x01

Definition at line 76 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_ARMCLKFIX   0x46

Definition at line 90 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_ARMPLL_OBSCLK   0x43

Definition at line 87 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_CLK009   0x07

Definition at line 82 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_CLK38M   0x00

Definition at line 75 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_HDMICLK   0x47

Definition at line 91 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_HSIRXCLK   0x44

Definition at line 88 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_HSITXCLK   0x45

Definition at line 89 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_I2CCLK   0x41

Definition at line 85 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_LCDCLK   0x03

Definition at line 78 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_MSP02CLK   0x42

Definition at line 86 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_SDMMCCLK   0x04

Definition at line 79 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_SIAMMDSPCLK   0x40

Definition at line 84 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_SYSCLK   0x02

Definition at line 77 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_TIMCLK   0x06

Definition at line 81 of file dbx500-prcmu.h.

#define PRCMU_CLKSRC_TVCLK   0x05

Definition at line 80 of file dbx500-prcmu.h.

#define PRCMU_QOS_APE_OPP   1

Definition at line 699 of file dbx500-prcmu.h.

#define PRCMU_QOS_ARM_OPP   3

Definition at line 701 of file dbx500-prcmu.h.

#define PRCMU_QOS_DDR_OPP   2

Definition at line 700 of file dbx500-prcmu.h.

#define PRCMU_QOS_DEFAULT_VALUE   -1

Definition at line 702 of file dbx500-prcmu.h.

#define PRCMU_WAKEUP

(

_name

)

(BIT(PRCMU_WAKEUP_INDEX_##_name))

Definition at line 29 of file dbx500-prcmu.h.

Enumeration Type Documentation

enum ape_opp

enum ape_opp - APE OPP states definition : : The APE operating point is unchanged : The new APE operating point is ape100opp : 50% : 50%, except some clocks at 25%.

Enumerator:

APE_OPP_INIT
APE_NO_CHANGE
APE_100_OPP
APE_50_OPP
APE_50_PARTLY_25_OPP

Definition at line 157 of file dbx500-prcmu.h.

enum arm_opp

enum arm_opp - ARM OPP states definition : : The ARM operating point is unchanged : The new ARM operating point is arm100opp : The new ARM operating point is arm50opp : Operating point is "max" (more than 100) : Set max opp if available, else 100 : The new ARM operating point is armExtClk

Enumerator:

ARM_OPP_INIT
ARM_NO_CHANGE
ARM_100_OPP
ARM_50_OPP
ARM_MAX_OPP
ARM_MAX_FREQ100OPP
ARM_EXTCLK

Definition at line 175 of file dbx500-prcmu.h.

enum ddr_opp

enum ddr_opp - DDR OPP states definition : The new DDR operating point is ddr100opp : The new DDR operating point is ddr50opp : The new DDR operating point is ddr25opp

Enumerator:

DDR_100_OPP
DDR_50_OPP
DDR_25_OPP

Definition at line 191 of file dbx500-prcmu.h.

enum ddr_pwrst

enum ddr_pwrst - DDR power states definition : SDRAM and DDR controller state is unchanged : : :

Enumerator:

DDR_PWR_STATE_UNCHANGED
DDR_PWR_STATE_ON
DDR_PWR_STATE_OFFLOWLAT
DDR_PWR_STATE_OFFHIGHLAT

Definition at line 210 of file dbx500-prcmu.h.

enum prcmu_clock

Enumerator:

PRCMU_SGACLK
PRCMU_UARTCLK
PRCMU_MSP02CLK
PRCMU_MSP1CLK
PRCMU_I2CCLK
PRCMU_SDMMCCLK
PRCMU_SPARE1CLK
PRCMU_SLIMCLK
PRCMU_PER1CLK
PRCMU_PER2CLK
PRCMU_PER3CLK
PRCMU_PER5CLK
PRCMU_PER6CLK
PRCMU_PER7CLK
PRCMU_LCDCLK
PRCMU_BMLCLK
PRCMU_HSITXCLK
PRCMU_HSIRXCLK
PRCMU_HDMICLK
PRCMU_APEATCLK
PRCMU_APETRACECLK
PRCMU_MCDECLK
PRCMU_IPI2CCLK
PRCMU_DSIALTCLK
PRCMU_DMACLK
PRCMU_B2R2CLK
PRCMU_TVCLK
PRCMU_SSPCLK
PRCMU_RNGCLK
PRCMU_UICCCLK
PRCMU_PWMCLK
PRCMU_IRDACLK
PRCMU_IRRCCLK
PRCMU_SIACLK
PRCMU_SVACLK
PRCMU_ACLK
PRCMU_NUM_REG_CLOCKS
PRCMU_SYSCLK
PRCMU_CDCLK
PRCMU_TIMCLK
PRCMU_PLLSOC0
PRCMU_PLLSOC1
PRCMU_ARMSS
PRCMU_PLLDDR
PRCMU_PLLDSI
PRCMU_DSI0CLK
PRCMU_DSI1CLK
PRCMU_DSI0ESCCLK
PRCMU_DSI1ESCCLK
PRCMU_DSI2ESCCLK

Definition at line 96 of file dbx500-prcmu.h.

enum prcmu_wakeup_index

Enumerator:

PRCMU_WAKEUP_INDEX_RTC
PRCMU_WAKEUP_INDEX_RTT0
PRCMU_WAKEUP_INDEX_RTT1
PRCMU_WAKEUP_INDEX_HSI0
PRCMU_WAKEUP_INDEX_HSI1
PRCMU_WAKEUP_INDEX_USB
PRCMU_WAKEUP_INDEX_ABB
PRCMU_WAKEUP_INDEX_ABB_FIFO
PRCMU_WAKEUP_INDEX_ARM
PRCMU_WAKEUP_INDEX_CD_IRQ
NUM_PRCMU_WAKEUP_INDICES

Definition at line 16 of file dbx500-prcmu.h.