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dbx500-prcmu.h
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1 /*
2  * Copyright (C) ST Ericsson SA 2011
3  *
4  * License Terms: GNU General Public License v2
5  *
6  * STE Ux500 PRCMU API
7  */
8 #ifndef __MACH_PRCMU_H
9 #define __MACH_PRCMU_H
10 
11 #include <linux/interrupt.h>
12 #include <linux/notifier.h>
13 #include <linux/err.h>
14 
15 /* PRCMU Wakeup defines */
28 };
29 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
30 
31 /* EPOD (power domain) IDs */
32 
33 /*
34  * DB8500 EPODs
35  * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36  * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37  * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38  * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39  * - EPOD_ID_SGA: power domain for SGA
40  * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41  * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42  * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43  * - NUM_EPOD_ID: number of power domains
44  *
45  * TODO: These should be prefixed.
46  */
47 #define EPOD_ID_SVAMMDSP 0
48 #define EPOD_ID_SVAPIPE 1
49 #define EPOD_ID_SIAMMDSP 2
50 #define EPOD_ID_SIAPIPE 3
51 #define EPOD_ID_SGA 4
52 #define EPOD_ID_B2R2_MCDE 5
53 #define EPOD_ID_ESRAM12 6
54 #define EPOD_ID_ESRAM34 7
55 #define NUM_EPOD_ID 8
56 
57 /*
58  * state definition for EPOD (power domain)
59  * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
60  * - EPOD_STATE_OFF: The EPOD is switched off
61  * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
62  * retention
63  * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
64  * - EPOD_STATE_ON: Same as above, but with clock enabled
65  */
66 #define EPOD_STATE_NO_CHANGE 0x00
67 #define EPOD_STATE_OFF 0x01
68 #define EPOD_STATE_RAMRET 0x02
69 #define EPOD_STATE_ON_CLK_OFF 0x03
70 #define EPOD_STATE_ON 0x04
71 
72 /*
73  * CLKOUT sources
74  */
75 #define PRCMU_CLKSRC_CLK38M 0x00
76 #define PRCMU_CLKSRC_ACLK 0x01
77 #define PRCMU_CLKSRC_SYSCLK 0x02
78 #define PRCMU_CLKSRC_LCDCLK 0x03
79 #define PRCMU_CLKSRC_SDMMCCLK 0x04
80 #define PRCMU_CLKSRC_TVCLK 0x05
81 #define PRCMU_CLKSRC_TIMCLK 0x06
82 #define PRCMU_CLKSRC_CLK009 0x07
83 /* These are only valid for CLKOUT1: */
84 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
85 #define PRCMU_CLKSRC_I2CCLK 0x41
86 #define PRCMU_CLKSRC_MSP02CLK 0x42
87 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
88 #define PRCMU_CLKSRC_HSIRXCLK 0x44
89 #define PRCMU_CLKSRC_HSITXCLK 0x45
90 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
91 #define PRCMU_CLKSRC_HDMICLK 0x47
92 
93 /*
94  * Clock identifiers.
95  */
147 };
148 
157 enum ape_opp {
158  APE_OPP_INIT = 0x00,
160  APE_100_OPP = 0x02,
161  APE_50_OPP = 0x03,
163 };
164 
175 enum arm_opp {
176  ARM_OPP_INIT = 0x00,
178  ARM_100_OPP = 0x02,
179  ARM_50_OPP = 0x03,
180  ARM_MAX_OPP = 0x04,
182  ARM_EXTCLK = 0x07
183 };
184 
191 enum ddr_opp {
192  DDR_100_OPP = 0x00,
193  DDR_50_OPP = 0x01,
194  DDR_25_OPP = 0x02,
195 };
196 
197 /*
198  * Definitions for controlling ESRAM0 in deep sleep.
199  */
200 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
201 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
202 
210 enum ddr_pwrst {
215 };
216 
217 #include <linux/mfd/db8500-prcmu.h>
218 
219 #if defined(CONFIG_UX500_SOC_DB8500)
220 
221 #include <mach/id.h>
222 
223 static inline void __init prcmu_early_init(void)
224 {
225  return db8500_prcmu_early_init();
226 }
227 
228 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
229  bool keep_ap_pll)
230 {
231  return db8500_prcmu_set_power_state(state, keep_ulp_clk,
232  keep_ap_pll);
233 }
234 
235 static inline u8 prcmu_get_power_state_result(void)
236 {
238 }
239 
240 static inline int prcmu_gic_decouple(void)
241 {
242  return db8500_prcmu_gic_decouple();
243 }
244 
245 static inline int prcmu_gic_recouple(void)
246 {
247  return db8500_prcmu_gic_recouple();
248 }
249 
250 static inline bool prcmu_gic_pending_irq(void)
251 {
253 }
254 
255 static inline bool prcmu_is_cpu_in_wfi(int cpu)
256 {
257  return db8500_prcmu_is_cpu_in_wfi(cpu);
258 }
259 
260 static inline int prcmu_copy_gic_settings(void)
261 {
263 }
264 
265 static inline bool prcmu_pending_irq(void)
266 {
267  return db8500_prcmu_pending_irq();
268 }
269 
270 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
271 {
272  return db8500_prcmu_set_epod(epod_id, epod_state);
273 }
274 
275 static inline void prcmu_enable_wakeups(u32 wakeups)
276 {
278 }
279 
280 static inline void prcmu_disable_wakeups(void)
281 {
282  prcmu_enable_wakeups(0);
283 }
284 
285 static inline void prcmu_config_abb_event_readout(u32 abb_events)
286 {
288 }
289 
290 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
291 {
293 }
294 
298 
299 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
300 
301 static inline int prcmu_request_clock(u8 clock, bool enable)
302 {
303  return db8500_prcmu_request_clock(clock, enable);
304 }
305 
306 unsigned long prcmu_clock_rate(u8 clock);
307 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
308 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
309 
310 static inline int prcmu_set_ddr_opp(u8 opp)
311 {
312  return db8500_prcmu_set_ddr_opp(opp);
313 }
314 static inline int prcmu_get_ddr_opp(void)
315 {
316  return db8500_prcmu_get_ddr_opp();
317 }
318 
319 static inline int prcmu_set_arm_opp(u8 opp)
320 {
321  return db8500_prcmu_set_arm_opp(opp);
322 }
323 
324 static inline int prcmu_get_arm_opp(void)
325 {
326  return db8500_prcmu_get_arm_opp();
327 }
328 
329 static inline int prcmu_set_ape_opp(u8 opp)
330 {
331  return db8500_prcmu_set_ape_opp(opp);
332 }
333 
334 static inline int prcmu_get_ape_opp(void)
335 {
336  return db8500_prcmu_get_ape_opp();
337 }
338 
339 static inline void prcmu_system_reset(u16 reset_code)
340 {
341  return db8500_prcmu_system_reset(reset_code);
342 }
343 
344 static inline u16 prcmu_get_reset_code(void)
345 {
347 }
348 
349 int prcmu_ac_wake_req(void);
350 void prcmu_ac_sleep_req(void);
351 static inline void prcmu_modem_reset(void)
352 {
353  return db8500_prcmu_modem_reset();
354 }
355 
356 static inline bool prcmu_is_ac_wake_requested(void)
357 {
359 }
360 
361 static inline int prcmu_set_display_clocks(void)
362 {
364 }
365 
366 static inline int prcmu_disable_dsipll(void)
367 {
369 }
370 
371 static inline int prcmu_enable_dsipll(void)
372 {
374 }
375 
376 static inline int prcmu_config_esram0_deep_sleep(u8 state)
377 {
379 }
380 
381 static inline int prcmu_config_hotdog(u8 threshold)
382 {
383  return db8500_prcmu_config_hotdog(threshold);
384 }
385 
386 static inline int prcmu_config_hotmon(u8 low, u8 high)
387 {
388  return db8500_prcmu_config_hotmon(low, high);
389 }
390 
391 static inline int prcmu_start_temp_sense(u16 cycles32k)
392 {
393  return db8500_prcmu_start_temp_sense(cycles32k);
394 }
395 
396 static inline int prcmu_stop_temp_sense(void)
397 {
399 }
400 
401 static inline u32 prcmu_read(unsigned int reg)
402 {
403  return db8500_prcmu_read(reg);
404 }
405 
406 static inline void prcmu_write(unsigned int reg, u32 value)
407 {
408  db8500_prcmu_write(reg, value);
409 }
410 
411 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
412 {
413  db8500_prcmu_write_masked(reg, mask, value);
414 }
415 
416 static inline int prcmu_enable_a9wdog(u8 id)
417 {
418  return db8500_prcmu_enable_a9wdog(id);
419 }
420 
421 static inline int prcmu_disable_a9wdog(u8 id)
422 {
423  return db8500_prcmu_disable_a9wdog(id);
424 }
425 
426 static inline int prcmu_kick_a9wdog(u8 id)
427 {
428  return db8500_prcmu_kick_a9wdog(id);
429 }
430 
431 static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
432 {
433  return db8500_prcmu_load_a9wdog(id, timeout);
434 }
435 
436 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
437 {
438  return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
439 }
440 #else
441 
442 static inline void __init prcmu_early_init(void) {}
443 
444 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
445  bool keep_ap_pll)
446 {
447  return 0;
448 }
449 
450 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
451 {
452  return 0;
453 }
454 
455 static inline void prcmu_enable_wakeups(u32 wakeups) {}
456 
457 static inline void prcmu_disable_wakeups(void) {}
458 
459 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
460 {
461  return -ENOSYS;
462 }
463 
464 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
465 {
466  return -ENOSYS;
467 }
468 
469 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
470  u8 size)
471 {
472  return -ENOSYS;
473 }
474 
475 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
476 {
477  return 0;
478 }
479 
480 static inline int prcmu_request_clock(u8 clock, bool enable)
481 {
482  return 0;
483 }
484 
485 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
486 {
487  return 0;
488 }
489 
490 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
491 {
492  return 0;
493 }
494 
495 static inline unsigned long prcmu_clock_rate(u8 clock)
496 {
497  return 0;
498 }
499 
500 static inline int prcmu_set_ape_opp(u8 opp)
501 {
502  return 0;
503 }
504 
505 static inline int prcmu_get_ape_opp(void)
506 {
507  return APE_100_OPP;
508 }
509 
510 static inline int prcmu_set_arm_opp(u8 opp)
511 {
512  return 0;
513 }
514 
515 static inline int prcmu_get_arm_opp(void)
516 {
517  return ARM_100_OPP;
518 }
519 
520 static inline int prcmu_set_ddr_opp(u8 opp)
521 {
522  return 0;
523 }
524 
525 static inline int prcmu_get_ddr_opp(void)
526 {
527  return DDR_100_OPP;
528 }
529 
530 static inline void prcmu_system_reset(u16 reset_code) {}
531 
532 static inline u16 prcmu_get_reset_code(void)
533 {
534  return 0;
535 }
536 
537 static inline int prcmu_ac_wake_req(void)
538 {
539  return 0;
540 }
541 
542 static inline void prcmu_ac_sleep_req(void) {}
543 
544 static inline void prcmu_modem_reset(void) {}
545 
546 static inline bool prcmu_is_ac_wake_requested(void)
547 {
548  return false;
549 }
550 
551 static inline int prcmu_set_display_clocks(void)
552 {
553  return 0;
554 }
555 
556 static inline int prcmu_disable_dsipll(void)
557 {
558  return 0;
559 }
560 
561 static inline int prcmu_enable_dsipll(void)
562 {
563  return 0;
564 }
565 
566 static inline int prcmu_config_esram0_deep_sleep(u8 state)
567 {
568  return 0;
569 }
570 
571 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
572 
573 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
574 {
575  *buf = NULL;
576 }
577 
578 static inline int prcmu_config_hotdog(u8 threshold)
579 {
580  return 0;
581 }
582 
583 static inline int prcmu_config_hotmon(u8 low, u8 high)
584 {
585  return 0;
586 }
587 
588 static inline int prcmu_start_temp_sense(u16 cycles32k)
589 {
590  return 0;
591 }
592 
593 static inline int prcmu_stop_temp_sense(void)
594 {
595  return 0;
596 }
597 
598 static inline u32 prcmu_read(unsigned int reg)
599 {
600  return 0;
601 }
602 
603 static inline void prcmu_write(unsigned int reg, u32 value) {}
604 
605 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
606 
607 #endif
608 
609 static inline void prcmu_set(unsigned int reg, u32 bits)
610 {
611  prcmu_write_masked(reg, bits, bits);
612 }
613 
614 static inline void prcmu_clear(unsigned int reg, u32 bits)
615 {
616  prcmu_write_masked(reg, bits, 0);
617 }
618 
619 #if defined(CONFIG_UX500_SOC_DB8500)
620 
624 static inline void prcmu_enable_spi2(void)
625 {
626  if (cpu_is_u8500())
628 }
629 
633 static inline void prcmu_disable_spi2(void)
634 {
635  if (cpu_is_u8500())
637 }
638 
643 static inline void prcmu_enable_stm_mod_uart(void)
644 {
645  if (cpu_is_u8500()) {
646  prcmu_set(DB8500_PRCM_GPIOCR,
649  }
650 }
651 
656 static inline void prcmu_disable_stm_mod_uart(void)
657 {
658  if (cpu_is_u8500()) {
659  prcmu_clear(DB8500_PRCM_GPIOCR,
662  }
663 }
664 
668 static inline void prcmu_enable_stm_ape(void)
669 {
670  if (cpu_is_u8500()) {
671  prcmu_set(DB8500_PRCM_GPIOCR,
673  }
674 }
675 
679 static inline void prcmu_disable_stm_ape(void)
680 {
681  if (cpu_is_u8500()) {
682  prcmu_clear(DB8500_PRCM_GPIOCR,
684  }
685 }
686 
687 #else
688 
689 static inline void prcmu_enable_spi2(void) {}
690 static inline void prcmu_disable_spi2(void) {}
691 static inline void prcmu_enable_stm_mod_uart(void) {}
692 static inline void prcmu_disable_stm_mod_uart(void) {}
693 static inline void prcmu_enable_stm_ape(void) {}
694 static inline void prcmu_disable_stm_ape(void) {}
695 
696 #endif
697 
698 /* PRCMU QoS APE OPP class */
699 #define PRCMU_QOS_APE_OPP 1
700 #define PRCMU_QOS_DDR_OPP 2
701 #define PRCMU_QOS_ARM_OPP 3
702 #define PRCMU_QOS_DEFAULT_VALUE -1
703 
704 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER
705 
706 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
707 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
708 void prcmu_qos_force_opp(int, s32);
709 int prcmu_qos_requirement(int pm_qos_class);
710 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
711 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
712 void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
713 int prcmu_qos_add_notifier(int prcmu_qos_class,
714  struct notifier_block *notifier);
715 int prcmu_qos_remove_notifier(int prcmu_qos_class,
716  struct notifier_block *notifier);
717 
718 #else
719 
720 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
721 {
722  return 0;
723 }
724 
725 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
726 
727 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
728 
729 static inline int prcmu_qos_requirement(int prcmu_qos_class)
730 {
731  return 0;
732 }
733 
734 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
735  char *name, s32 value)
736 {
737  return 0;
738 }
739 
740 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
741  char *name, s32 new_value)
742 {
743  return 0;
744 }
745 
746 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
747 {
748 }
749 
750 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
751  struct notifier_block *notifier)
752 {
753  return 0;
754 }
755 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
756  struct notifier_block *notifier)
757 {
758  return 0;
759 }
760 
761 #endif
762 
763 #endif /* __MACH_PRCMU_H */