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intc-sh7372.c
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1 /*
2  * sh7372 processor support - INTC hardware block
3  *
4  * Copyright (C) 2010 Magnus Damm
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18  */
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/irq.h>
24 #include <linux/io.h>
25 #include <linux/sh_intc.h>
26 #include <mach/intc.h>
27 #include <mach/irqs.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 
31 enum {
32  UNUSED_INTCA = 0,
33 
34  /* interrupt sources INTCA */
35  DIRC,
36  CRYPT_STD,
37  IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
38  AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
39  MFI_MFIM, MFI_MFIS,
40  BBIF1, BBIF2,
41  USBHSDMAC0_USHDMI,
42  _3DG_SGX540,
43  CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
44  KEYSC_KEY,
45  SCIFA0, SCIFA1, SCIFA2, SCIFA3,
46  MSIOF2, MSIOF1,
47  SCIFA4, SCIFA5, SCIFB,
48  FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
49  SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
50  SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
51  IRREM,
52  IRDA,
53  TPU0,
54  TTI20,
55  DDM,
56  SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
57  RWDT0,
58  DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
59  DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
60  DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
61  DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
62  DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
63  DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
64  SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
65  HDMI,
66  SPU2_SPU0, SPU2_SPU1,
67  FSI, FMSI,
68  MIPI_HSI,
69  IPMMU_IPMMUD,
70  CEC_1, CEC_2,
71  AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
72  MFIS2,
73  CPORTR2S,
74  CMT14, CMT15,
75  MMC_MMC_ERR, MMC_MMC_NOR,
76  IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
77  IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
78  USB0_USB0I1, USB0_USB0I0,
79  USB1_USB1I1, USB1_USB1I0,
80  USBHSDMAC1_USHDMI,
81 
82  /* interrupt groups INTCA */
83  DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
84  AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
85 };
86 
87 static struct intc_vect intca_vectors[] __initdata = {
88  INTC_VECT(DIRC, 0x0560),
89  INTC_VECT(CRYPT_STD, 0x0700),
90  INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
91  INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
92  INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
93  INTC_VECT(AP_ARM_COMMRX, 0x0860),
94  INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
95  INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
96  INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
97  INTC_VECT(_3DG_SGX540, 0x0a60),
98  INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
99  INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
100  INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
101  INTC_VECT(KEYSC_KEY, 0x0be0),
102  INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
103  INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
104  INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
105  INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
106  INTC_VECT(SCIFB, 0x0d60),
107  INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
108  INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
109  INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
110  INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
111  INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
112  INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
113  INTC_VECT(IRREM, 0x0f60),
114  INTC_VECT(IRDA, 0x0480),
115  INTC_VECT(TPU0, 0x04a0),
116  INTC_VECT(TTI20, 0x1100),
117  INTC_VECT(DDM, 0x1140),
118  INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
119  INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
120  INTC_VECT(RWDT0, 0x1280),
121  INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
122  INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
123  INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
124  INTC_VECT(DMAC1_2_DADERR, 0x20c0),
125  INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
126  INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
127  INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
128  INTC_VECT(DMAC2_2_DADERR, 0x21c0),
129  INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
130  INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
131  INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
132  INTC_VECT(DMAC3_2_DADERR, 0x22c0),
133  INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
134  INTC_VECT(SHWYSTAT_COM, 0x1340),
135  INTC_VECT(HDMI, 0x17e0),
136  INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
137  INTC_VECT(FSI, 0x1840),
138  INTC_VECT(FMSI, 0x1860),
139  INTC_VECT(MIPI_HSI, 0x18e0),
140  INTC_VECT(IPMMU_IPMMUD, 0x1920),
141  INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
142  INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
143  INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
144  INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
145  INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
146  INTC_VECT(MFIS2, 0x1a00),
147  INTC_VECT(CPORTR2S, 0x1a20),
148  INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
149  INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
150  INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
151  INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
152  INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
153  INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
154  INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
155  INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
156  INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
157 };
158 
159 static struct intc_group intca_groups[] __initdata = {
160  INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
161  DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
162  INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
163  DMAC1_2_DEI5, DMAC1_2_DADERR),
164  INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
165  DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
166  INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
167  DMAC2_2_DEI5, DMAC2_2_DADERR),
168  INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
169  DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
170  INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
171  DMAC3_2_DEI5, DMAC3_2_DADERR),
172  INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
173  INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
174  AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
175  INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
176  INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
177  FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
178  INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
179  INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
180  SDHI0_SDHI0I2, SDHI0_SDHI0I3),
181  INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
182  SDHI1_SDHI1I2),
183  INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
184  SDHI2_SDHI2I2, SDHI2_SDHI2I3),
185  INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
186 };
187 
188 static struct intc_mask_reg intca_mask_registers[] __initdata = {
189  { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
190  { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
191  AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
192  { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
193  { 0, CRYPT_STD, DIRC, 0,
194  DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
195  { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
196  { 0, 0, 0, 0,
197  BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
198  { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
199  { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
200  DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
201  { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
202  { DDM, 0, 0, 0,
203  0, 0, 0, 0 } },
204  { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
205  { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
206  SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
207  { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
208  { SCIFB, SCIFA5, SCIFA4, MSIOF1,
209  0, 0, MSIOF2, 0 } },
210  { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
211  { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
212  FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
213  { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
214  { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
215  TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
216  { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
217  { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
218  CMT2, 0, 0, _3DG_SGX540 } },
219  { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
220  { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
221  0, 0, 0, 0 } },
222  { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
223  { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
224  0, 0, IRREM, 0 } },
225  { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
226  { 0, 0, TPU0, 0,
227  0, 0, 0, 0 } },
228  { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
229  { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
230  0, CMT3, 0, RWDT0 } },
231  { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
232  { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
233  0, 0, 0, 0 } },
234  { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
235  { 0, 0, 0, 0,
236  0, 0, 0, HDMI } },
237  { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
238  { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
239  0, 0, 0, MIPI_HSI } },
240  { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
241  { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
242  AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
243  AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
244  { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
245  { MFIS2, CPORTR2S, CMT14, CMT15,
246  0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
247  { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
248  { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
249  IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
250  { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
251  { 0, 0, 0, 0,
252  USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
253  { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
254  { USBHSDMAC1_USHDMI, 0, 0, 0,
255  0, 0, 0, 0 } },
256 };
257 
258 static struct intc_prio_reg intca_prio_registers[] __initdata = {
259  { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
260  { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
261  { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
262  CMT1_CMT11, AP_ARM1 } },
263  { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
264  CMT1_CMT12, 0 } },
265  { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
266  MFI_MFIM, 0 } },
267  { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
268  _3DG_SGX540, CMT1_CMT10 } },
269  { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
270  SCIFA2, SCIFA3 } },
271  { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
272  FLCTL, SDHI0 } },
273  { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
274  0/* MSU */, IIC1 } },
275  { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
276  0/* MSUG */, TTI20 } },
277  { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
278  { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
279  { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
280  { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
281  { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
282  { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
283  { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
284  { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
285  { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
286  { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
287  CEC_1, CEC_2 } },
288  { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
289  { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
290  CMT14, CMT15 } },
291  { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
292  MMC_MMC_ERR, MMC_MMC_NOR } },
293  { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
294  IIC4_WAITI4, IIC4_DTEI4 } },
295  { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
296  IIC3_WAITI3, IIC3_DTEI3 } },
297  { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
298  0/*TXI*/, 0/*TEI*/} },
299  { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
300  USB1_USB1I1, USB1_USB1I0 } },
301  { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
302 };
303 
304 static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
305  intca_vectors, intca_groups,
306  intca_mask_registers, intca_prio_registers,
307  NULL);
308 
309 INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
310  INTC_VECT, "sh7372-intca-irq-lo");
311 
312 INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
313  INTC_VECT, "sh7372-intca-irq-hi");
314 
315 enum {
316  UNUSED_INTCS = 0,
317  ENABLED_INTCS,
318 
319  /* interrupt sources INTCS */
320 
321  /* IRQ0S - IRQ31S */
322  VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
323  RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
324  CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
325  /* MFI */
326  /* BBIF2 */
327  VPU,
328  TSIF1,
329  /* 3DG */
330  _2DDMAC,
331  IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
332  IPMMU_IPMMUR, IPMMU_IPMMUR2,
333  RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
334  /* KEYSC */
335  /* TTI20 */
336  MSIOF,
337  IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
338  TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
339  CMT0,
340  TSIF0,
341  /* CMT2 */
342  LMB,
343  CTI,
344  /* RWDT0 */
345  ICB,
346  JPU_JPEG,
347  LCDC,
348  LCRC,
349  RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
350  RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
351  ISP,
352  LCDC1,
353  CSIRX,
354  DSITX_DSITX0,
355  DSITX_DSITX1,
356  /* SPU2 */
357  /* FSI */
358  /* FMSI */
359  /* HDMI */
360  TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
361  CMT4,
362  DSITX1_DSITX1_0,
363  DSITX1_DSITX1_1,
364  MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
365  CPORTS2R,
366  /* CEC */
367  JPU6E,
368 
369  /* interrupt groups INTCS */
370  RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
371  RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
372 };
373 
374 static struct intc_vect intcs_vectors[] = {
375  /* IRQ0S - IRQ31S */
376  INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
377  INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
378  INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
379  INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
380  INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
381  INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
382  /* MFI */
383  /* BBIF2 */
384  INTCS_VECT(VPU, 0x980),
385  INTCS_VECT(TSIF1, 0x9a0),
386  /* 3DG */
387  INTCS_VECT(_2DDMAC, 0xa00),
388  INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
389  INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
390  INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
391  INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
392  INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
393  /* KEYSC */
394  /* TTI20 */
395  INTCS_VECT(MSIOF, 0x0d20),
396  INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
397  INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
398  INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
399  INTCS_VECT(TMU_TUNI2, 0xec0),
400  INTCS_VECT(CMT0, 0xf00),
401  INTCS_VECT(TSIF0, 0xf20),
402  /* CMT2 */
403  INTCS_VECT(LMB, 0xf60),
404  INTCS_VECT(CTI, 0x400),
405  /* RWDT0 */
406  INTCS_VECT(ICB, 0x480),
407  INTCS_VECT(JPU_JPEG, 0x560),
408  INTCS_VECT(LCDC, 0x580),
409  INTCS_VECT(LCRC, 0x5a0),
410  INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
411  INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
412  INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
413  INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
414  INTCS_VECT(ISP, 0x1720),
415  INTCS_VECT(LCDC1, 0x1780),
416  INTCS_VECT(CSIRX, 0x17a0),
417  INTCS_VECT(DSITX_DSITX0, 0x17c0),
418  INTCS_VECT(DSITX_DSITX1, 0x17e0),
419  /* SPU2 */
420  /* FSI */
421  /* FMSI */
422  /* HDMI */
423  INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
424  INTCS_VECT(TMU1_TUNI2, 0x1940),
425  INTCS_VECT(CMT4, 0x1980),
426  INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
427  INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
428  INTCS_VECT(MFIS2_INTCS, 0x1a00),
429  INTCS_VECT(CPORTS2R, 0x1a20),
430  /* CEC */
431  INTCS_VECT(JPU6E, 0x1a80),
432 };
433 
434 static struct intc_group intcs_groups[] __initdata = {
435  INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
436  RTDMAC_1_DEI2, RTDMAC_1_DEI3),
437  INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
438  INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
439  INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
440  INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
441  INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
442  INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
443  INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
444  RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
445  INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
446  RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
447  INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
448  INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
449 };
450 
451 static struct intc_mask_reg intcs_mask_registers[] = {
452  { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
453  { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
454  VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
455  { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
456  { 0, 0, 0, VPU,
457  0, 0, 0, 0 } },
458  { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
459  { 0, 0, 0, _2DDMAC,
460  0, 0, 0, ICB } },
461  { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
462  { 0, 0, 0, CTI,
463  JPU_JPEG, 0, LCRC, LCDC } },
464  { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
465  { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
466  RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
467  { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
468  { 0, 0, MSIOF, 0,
469  0, 0, 0, 0 } },
470  { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
471  { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
472  0, 0, 0, 0 } },
473  { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
474  { 0, 0, 0, CMT0,
475  IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
476  { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
477  { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
478  0, 0, 0, 0 } },
479  { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
480  { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
481  0, TSIF1, LMB, TSIF0 } },
482  { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
483  { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
484  RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
485  { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
486  { 0, ISP, 0, 0,
487  LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
488  { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
489  { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
490  CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
491  { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
492  { MFIS2_INTCS, CPORTS2R, 0, 0,
493  JPU6E, 0, 0, 0 } },
494 };
495 
496 /* Priority is needed for INTCA to receive the INTCS interrupt */
497 static struct intc_prio_reg intcs_prio_registers[] = {
498  { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
499  { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
500  { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
501  { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
502  { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
503  TMU_TUNI2, TSIF1 } },
504  { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
505  { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
506  { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
507  { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
508  { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
509  { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
510  { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
511  { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
512  { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
513  { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
514  { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
515  DSITX1_DSITX1_1, 0 } },
516  { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
517  0, 0 } },
518  { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
519 };
520 
521 static struct resource intcs_resources[] __initdata = {
522  [0] = {
523  .start = 0xffd20000,
524  .end = 0xffd201ff,
525  .flags = IORESOURCE_MEM,
526  },
527  [1] = {
528  .start = 0xffd50000,
529  .end = 0xffd501ff,
530  .flags = IORESOURCE_MEM,
531  }
532 };
533 
534 static struct intc_desc intcs_desc __initdata = {
535  .name = "sh7372-intcs",
536  .force_enable = ENABLED_INTCS,
537  .skip_syscore_suspend = true,
538  .resource = intcs_resources,
539  .num_resources = ARRAY_SIZE(intcs_resources),
540  .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
541  intcs_prio_registers, NULL, NULL),
542 };
543 
544 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
545 {
546  void __iomem *reg = (void *)irq_get_handler_data(irq);
547  unsigned int evtcodeas = ioread32(reg);
548 
549  generic_handle_irq(intcs_evt2irq(evtcodeas));
550 }
551 
552 static void __iomem *intcs_ffd2;
553 static void __iomem *intcs_ffd5;
554 
555 void __init sh7372_init_irq(void)
556 {
557  void __iomem *intevtsa;
558  int n;
559 
560  intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
561  intevtsa = intcs_ffd2 + 0x100;
562  intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
563 
564  register_intc_controller(&intca_desc);
565  register_intc_controller(&intca_irq_pins_lo_desc);
566  register_intc_controller(&intca_irq_pins_hi_desc);
567  register_intc_controller(&intcs_desc);
568 
569  /* setup dummy cascade chip for INTCS */
570  n = evt2irq(0xf80);
571  irq_alloc_desc_at(n, numa_node_id());
572  irq_set_chip_and_handler_name(n, &dummy_irq_chip,
573  handle_level_irq, "level");
574  set_irq_flags(n, IRQF_VALID); /* yuck */
575 
576  /* demux using INTEVTSA */
577  irq_set_handler_data(n, (void *)intevtsa);
578  irq_set_chained_handler(n, intcs_demux);
579 
580  /* unmask INTCS in INTAMASK */
581  iowrite16(0, intcs_ffd2 + 0x104);
582 }
583 
584 static unsigned short ffd2[0x200];
585 static unsigned short ffd5[0x100];
586 
587 void sh7372_intcs_suspend(void)
588 {
589  int k;
590 
591  for (k = 0x00; k <= 0x30; k += 4)
592  ffd2[k] = __raw_readw(intcs_ffd2 + k);
593 
594  for (k = 0x80; k <= 0xb0; k += 4)
595  ffd2[k] = __raw_readb(intcs_ffd2 + k);
596 
597  for (k = 0x180; k <= 0x188; k += 4)
598  ffd2[k] = __raw_readb(intcs_ffd2 + k);
599 
600  for (k = 0x00; k <= 0x3c; k += 4)
601  ffd5[k] = __raw_readw(intcs_ffd5 + k);
602 
603  for (k = 0x80; k <= 0x9c; k += 4)
604  ffd5[k] = __raw_readb(intcs_ffd5 + k);
605 }
606 
607 void sh7372_intcs_resume(void)
608 {
609  int k;
610 
611  for (k = 0x00; k <= 0x30; k += 4)
612  __raw_writew(ffd2[k], intcs_ffd2 + k);
613 
614  for (k = 0x80; k <= 0xb0; k += 4)
615  __raw_writeb(ffd2[k], intcs_ffd2 + k);
616 
617  for (k = 0x180; k <= 0x188; k += 4)
618  __raw_writeb(ffd2[k], intcs_ffd2 + k);
619 
620  for (k = 0x00; k <= 0x3c; k += 4)
621  __raw_writew(ffd5[k], intcs_ffd5 + k);
622 
623  for (k = 0x80; k <= 0x9c; k += 4)
624  __raw_writeb(ffd5[k], intcs_ffd5 + k);
625 }
626 
627 #define E694_BASE IOMEM(0xe6940000)
628 #define E695_BASE IOMEM(0xe6950000)
629 
630 static unsigned short e694[0x200];
631 static unsigned short e695[0x200];
632 
633 void sh7372_intca_suspend(void)
634 {
635  int k;
636 
637  for (k = 0x00; k <= 0x38; k += 4)
638  e694[k] = __raw_readw(E694_BASE + k);
639 
640  for (k = 0x80; k <= 0xb4; k += 4)
641  e694[k] = __raw_readb(E694_BASE + k);
642 
643  for (k = 0x180; k <= 0x1b4; k += 4)
644  e694[k] = __raw_readb(E694_BASE + k);
645 
646  for (k = 0x00; k <= 0x50; k += 4)
647  e695[k] = __raw_readw(E695_BASE + k);
648 
649  for (k = 0x80; k <= 0xa8; k += 4)
650  e695[k] = __raw_readb(E695_BASE + k);
651 
652  for (k = 0x180; k <= 0x1a8; k += 4)
653  e695[k] = __raw_readb(E695_BASE + k);
654 }
655 
656 void sh7372_intca_resume(void)
657 {
658  int k;
659 
660  for (k = 0x00; k <= 0x38; k += 4)
661  __raw_writew(e694[k], E694_BASE + k);
662 
663  for (k = 0x80; k <= 0xb4; k += 4)
664  __raw_writeb(e694[k], E694_BASE + k);
665 
666  for (k = 0x180; k <= 0x1b4; k += 4)
667  __raw_writeb(e694[k], E694_BASE + k);
668 
669  for (k = 0x00; k <= 0x50; k += 4)
670  __raw_writew(e695[k], E695_BASE + k);
671 
672  for (k = 0x80; k <= 0xa8; k += 4)
673  __raw_writeb(e695[k], E695_BASE + k);
674 
675  for (k = 0x180; k <= 0x1a8; k += 4)
676  __raw_writeb(e695[k], E695_BASE + k);
677 }
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