#include <linux/types.h>
#include <linux/iova.h>
#include <linux/io.h>
#include <linux/dma_remapping.h>
#include <asm/cacheflush.h>
#include <asm/iommu.h>

Data Structures
struct	qi_desc

struct	q_inval

struct	iommu_flush

struct	intel_iommu

Macros
#define	DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */

#define	DMAR_CAP_REG 0x8 /* Hardware supported capabilities */

#define	DMAR_ECAP_REG 0x10 /* Extended capabilities supported */

#define	DMAR_GCMD_REG 0x18 /* Global command register */

#define	DMAR_GSTS_REG 0x1c /* Global status register */

#define	DMAR_RTADDR_REG 0x20 /* Root entry table */

#define	DMAR_CCMD_REG 0x28 /* Context command reg */

#define	DMAR_FSTS_REG 0x34 /* Fault Status register */

#define	DMAR_FECTL_REG 0x38 /* Fault control register */

#define	DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */

#define	DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */

#define	DMAR_FEUADDR_REG 0x44 /* Upper address register */

#define	DMAR_AFLOG_REG 0x58 /* Advanced Fault control */

#define	DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */

#define	DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */

#define	DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */

#define	DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */

#define	DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */

#define	DMAR_IQH_REG 0x80 /* Invalidation queue head register */

#define	DMAR_IQT_REG 0x88 /* Invalidation queue tail register */

#define	DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */

#define	DMAR_IQA_REG 0x90 /* Invalidation queue addr register */

#define	DMAR_ICS_REG 0x98 /* Invalidation complete status register */

#define	DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */

#define	OFFSET_STRIDE (9)

#define	DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)

#define	DMAR_VER_MINOR(v) ((v) & 0x0f)

#define	cap_read_drain(c) (((c) >> 55) & 1)

#define	cap_write_drain(c) (((c) >> 54) & 1)

#define	cap_max_amask_val(c) (((c) >> 48) & 0x3f)

#define	cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)

#define	cap_pgsel_inv(c) (((c) >> 39) & 1)

#define	cap_super_page_val(c) (((c) >> 34) & 0xf)

#define	cap_super_offset(c)

#define	cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)

#define	cap_max_fault_reg_offset(c) (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)

#define	cap_zlr(c) (((c) >> 22) & 1)

#define	cap_isoch(c) (((c) >> 23) & 1)

#define	cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)

#define	cap_sagaw(c) (((c) >> 8) & 0x1f)

#define	cap_caching_mode(c) (((c) >> 7) & 1)

#define	cap_phmr(c) (((c) >> 6) & 1)

#define	cap_plmr(c) (((c) >> 5) & 1)

#define	cap_rwbf(c) (((c) >> 4) & 1)

#define	cap_afl(c) (((c) >> 3) & 1)

#define	cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))

#define	ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)

#define	ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)

#define	ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)

#define	ecap_coherent(e) ((e) & 0x1)

#define	ecap_qis(e) ((e) & 0x2)

#define	ecap_pass_through(e) ((e >> 6) & 0x1)

#define	ecap_eim_support(e) ((e >> 4) & 0x1)

#define	ecap_ir_support(e) ((e >> 3) & 0x1)

#define	ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)

#define	ecap_max_handle_mask(e) ((e >> 20) & 0xf)

#define	ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */

#define	DMA_TLB_FLUSH_GRANU_OFFSET 60

#define	DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)

#define	DMA_TLB_DSI_FLUSH (((u64)2) << 60)

#define	DMA_TLB_PSI_FLUSH (((u64)3) << 60)

#define	DMA_TLB_IIRG(type) ((type >> 60) & 7)

#define	DMA_TLB_IAIG(val) (((val) >> 57) & 7)

#define	DMA_TLB_READ_DRAIN (((u64)1) << 49)

#define	DMA_TLB_WRITE_DRAIN (((u64)1) << 48)

#define	DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)

#define	DMA_TLB_IVT (((u64)1) << 63)

#define	DMA_TLB_IH_NONLEAF (((u64)1) << 6)

#define	DMA_TLB_MAX_SIZE (0x3f)

#define	DMA_CCMD_INVL_GRANU_OFFSET 61

#define	DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)

#define	DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)

#define	DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)

#define	DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)

#define	DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)

#define	DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))

#define	DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)

#define	DMA_ID_TLB_ADDR(addr) (addr)

#define	DMA_ID_TLB_ADDR_MASK(mask) (mask)

#define	DMA_PMEN_EPM (((u32)1)<<31)

#define	DMA_PMEN_PRS (((u32)1)<<0)

#define	DMA_GCMD_TE (((u32)1) << 31)

#define	DMA_GCMD_SRTP (((u32)1) << 30)

#define	DMA_GCMD_SFL (((u32)1) << 29)

#define	DMA_GCMD_EAFL (((u32)1) << 28)

#define	DMA_GCMD_WBF (((u32)1) << 27)

#define	DMA_GCMD_QIE (((u32)1) << 26)

#define	DMA_GCMD_SIRTP (((u32)1) << 24)

#define	DMA_GCMD_IRE (((u32) 1) << 25)

#define	DMA_GCMD_CFI (((u32) 1) << 23)

#define	DMA_GSTS_TES (((u32)1) << 31)

#define	DMA_GSTS_RTPS (((u32)1) << 30)

#define	DMA_GSTS_FLS (((u32)1) << 29)

#define	DMA_GSTS_AFLS (((u32)1) << 28)

#define	DMA_GSTS_WBFS (((u32)1) << 27)

#define	DMA_GSTS_QIES (((u32)1) << 26)

#define	DMA_GSTS_IRTPS (((u32)1) << 24)

#define	DMA_GSTS_IRES (((u32)1) << 25)

#define	DMA_GSTS_CFIS (((u32)1) << 23)

#define	DMA_CCMD_ICC (((u64)1) << 63)

#define	DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)

#define	DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)

#define	DMA_CCMD_DEVICE_INVL (((u64)3) << 61)

#define	DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)

#define	DMA_CCMD_MASK_NOBIT 0

#define	DMA_CCMD_MASK_1BIT 1

#define	DMA_CCMD_MASK_2BIT 2

#define	DMA_CCMD_MASK_3BIT 3

#define	DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)

#define	DMA_CCMD_DID(d) ((u64)((d) & 0xffff))

#define	DMA_FECTL_IM (((u32)1) << 31)

#define	DMA_FSTS_PPF ((u32)2)

#define	DMA_FSTS_PFO ((u32)1)

#define	DMA_FSTS_IQE (1 << 4)

#define	DMA_FSTS_ICE (1 << 5)

#define	DMA_FSTS_ITE (1 << 6)

#define	dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)

#define	DMA_FRCD_F (((u32)1) << 31)

#define	dma_frcd_type(d) ((d >> 30) & 1)

#define	dma_frcd_fault_reason(c) (c & 0xff)

#define	dma_frcd_source_id(c) (c & 0xffff)

#define	dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))

#define	IOMMU_WAIT_OP(iommu, offset, op, cond, sts)

#define	QI_LENGTH 256 /* queue length */

#define	QI_CC_TYPE 0x1

#define	QI_IOTLB_TYPE 0x2

#define	QI_DIOTLB_TYPE 0x3

#define	QI_IEC_TYPE 0x4

#define	QI_IWD_TYPE 0x5

#define	QI_IEC_SELECTIVE (((u64)1) << 4)

#define	QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))

#define	QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))

#define	QI_IWD_STATUS_DATA(d) (((u64)d) << 32)

#define	QI_IWD_STATUS_WRITE (((u64)1) << 5)

#define	QI_IOTLB_DID(did) (((u64)did) << 16)

#define	QI_IOTLB_DR(dr) (((u64)dr) << 7)

#define	QI_IOTLB_DW(dw) (((u64)dw) << 6)

#define	QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))

#define	QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)

#define	QI_IOTLB_IH(ih) (((u64)ih) << 6)

#define	QI_IOTLB_AM(am) (((u8)am))

#define	QI_CC_FM(fm) (((u64)fm) << 48)

#define	QI_CC_SID(sid) (((u64)sid) << 32)

#define	QI_CC_DID(did) (((u64)did) << 16)

#define	QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))

#define	QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)

#define	QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)

#define	QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)

#define	QI_DEV_IOTLB_SIZE 1

#define	QI_DEV_IOTLB_MAX_INVS 32

Enumerations
enum	{ QI_FREE, QI_IN_USE, QI_DONE, QI_ABORT }

enum	{ SR_DMAR_FECTL_REG, SR_DMAR_FEDATA_REG, SR_DMAR_FEADDR_REG, SR_DMAR_FEUADDR_REG, MAX_SR_DMAR_REGS }

Functions
struct dmar_drhd_unit *	dmar_find_matched_drhd_unit (struct pci_dev *dev)

int	dmar_find_matched_atsr_unit (struct pci_dev *dev)

int	alloc_iommu (struct dmar_drhd_unit *drhd)

void	free_iommu (struct intel_iommu *iommu)

int	dmar_enable_qi (struct intel_iommu *iommu)

void	dmar_disable_qi (struct intel_iommu *iommu)

int	dmar_reenable_qi (struct intel_iommu *iommu)

void	qi_global_iec (struct intel_iommu *iommu)

void	qi_flush_context (struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, u64 type)

void	qi_flush_iotlb (struct intel_iommu *iommu, u16 did, u64 addr, unsigned int size_order, u64 type)

void	qi_flush_dev_iotlb (struct intel_iommu *iommu, u16 sid, u16 qdep, u64 addr, unsigned mask)

int	qi_submit_sync (struct qi_desc desc, struct intel_iommu iommu)

int	dmar_ir_support (void)

Macro Definition Documentation

#define cap_afl ( c ) (((c) >> 3) & 1)

Definition at line 112 of file intel-iommu.h.

#define cap_caching_mode ( c ) (((c) >> 7) & 1)

Definition at line 108 of file intel-iommu.h.

#define cap_fault_reg_offset ( c ) ((((c) >> 24) & 0x3ff) * 16)

Definition at line 100 of file intel-iommu.h.

#define cap_isoch ( c ) (((c) >> 23) & 1)

Definition at line 105 of file intel-iommu.h.

#define cap_max_amask_val ( c ) (((c) >> 48) & 0x3f)

Definition at line 92 of file intel-iommu.h.

#define cap_max_fault_reg_offset ( c ) (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)

Definition at line 101 of file intel-iommu.h.

#define cap_mgaw ( c ) ((((c) >> 16) & 0x3f) + 1)

Definition at line 106 of file intel-iommu.h.

#define cap_ndoms ( c ) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))

Definition at line 113 of file intel-iommu.h.

#define cap_num_fault_regs ( c ) ((((c) >> 40) & 0xff) + 1)

Definition at line 93 of file intel-iommu.h.

#define cap_pgsel_inv ( c ) (((c) >> 39) & 1)

Definition at line 94 of file intel-iommu.h.

#define cap_phmr ( c ) (((c) >> 6) & 1)

Definition at line 109 of file intel-iommu.h.

#define cap_plmr ( c ) (((c) >> 5) & 1)

Definition at line 110 of file intel-iommu.h.

#define cap_read_drain ( c ) (((c) >> 55) & 1)

Definition at line 90 of file intel-iommu.h.

#define cap_rwbf ( c ) (((c) >> 4) & 1)

Definition at line 111 of file intel-iommu.h.

#define cap_sagaw ( c ) (((c) >> 8) & 0x1f)

Definition at line 107 of file intel-iommu.h.

#define cap_super_offset ( c )

Value:

(((find_first_bit(&cap_super_page_val(c), 4)) \

* OFFSET_STRIDE) + 21)

Definition at line 97 of file intel-iommu.h.

#define cap_super_page_val ( c ) (((c) >> 34) & 0xf)

Definition at line 96 of file intel-iommu.h.

#define cap_write_drain ( c ) (((c) >> 54) & 1)

Definition at line 91 of file intel-iommu.h.

#define cap_zlr ( c ) (((c) >> 22) & 1)

Definition at line 104 of file intel-iommu.h.

#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)

Definition at line 187 of file intel-iommu.h.

#define DMA_CCMD_DID ( d ) ((u64)((d) & 0xffff))

Definition at line 194 of file intel-iommu.h.

#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)

Definition at line 186 of file intel-iommu.h.

#define DMA_CCMD_FM ( m ) (((u64)((m) & 0x3)) << 32)

Definition at line 188 of file intel-iommu.h.

#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)

Definition at line 185 of file intel-iommu.h.

#define DMA_CCMD_ICC (((u64)1) << 63)

Definition at line 184 of file intel-iommu.h.

#define DMA_CCMD_INVL_GRANU_OFFSET 61

Definition at line 146 of file intel-iommu.h.

#define DMA_CCMD_MASK_1BIT 1

Definition at line 190 of file intel-iommu.h.

#define DMA_CCMD_MASK_2BIT 2

Definition at line 191 of file intel-iommu.h.

#define DMA_CCMD_MASK_3BIT 3

Definition at line 192 of file intel-iommu.h.

#define DMA_CCMD_MASK_NOBIT 0

Definition at line 189 of file intel-iommu.h.

#define DMA_CCMD_SID ( s ) (((u64)((s) & 0xffff)) << 16)

Definition at line 193 of file intel-iommu.h.

#define DMA_FECTL_IM (((u32)1) << 31)

Definition at line 197 of file intel-iommu.h.

#define DMA_FRCD_F (((u32)1) << 31)

Definition at line 208 of file intel-iommu.h.

#define dma_frcd_fault_reason ( c ) (c & 0xff)

Definition at line 210 of file intel-iommu.h.

#define dma_frcd_page_addr ( d ) (d & (((u64)-1) << PAGE_SHIFT))

Definition at line 213 of file intel-iommu.h.

#define dma_frcd_source_id ( c ) (c & 0xffff)

Definition at line 211 of file intel-iommu.h.

#define dma_frcd_type ( d ) ((d >> 30) & 1)

Definition at line 209 of file intel-iommu.h.

#define dma_fsts_fault_record_index ( s ) (((s) >> 8) & 0xff)

Definition at line 205 of file intel-iommu.h.

#define DMA_FSTS_ICE (1 << 5)

Definition at line 203 of file intel-iommu.h.

#define DMA_FSTS_IQE (1 << 4)

Definition at line 202 of file intel-iommu.h.

#define DMA_FSTS_ITE (1 << 6)

Definition at line 204 of file intel-iommu.h.

#define DMA_FSTS_PFO ((u32)1)

Definition at line 201 of file intel-iommu.h.

#define DMA_FSTS_PPF ((u32)2)

Definition at line 200 of file intel-iommu.h.

#define DMA_GCMD_CFI (((u32) 1) << 23)

Definition at line 170 of file intel-iommu.h.

#define DMA_GCMD_EAFL (((u32)1) << 28)

Definition at line 165 of file intel-iommu.h.

#define DMA_GCMD_IRE (((u32) 1) << 25)

Definition at line 169 of file intel-iommu.h.

#define DMA_GCMD_QIE (((u32)1) << 26)

Definition at line 167 of file intel-iommu.h.

#define DMA_GCMD_SFL (((u32)1) << 29)

Definition at line 164 of file intel-iommu.h.

#define DMA_GCMD_SIRTP (((u32)1) << 24)

Definition at line 168 of file intel-iommu.h.

#define DMA_GCMD_SRTP (((u32)1) << 30)

Definition at line 163 of file intel-iommu.h.

#define DMA_GCMD_TE (((u32)1) << 31)

Definition at line 162 of file intel-iommu.h.

#define DMA_GCMD_WBF (((u32)1) << 27)

Definition at line 166 of file intel-iommu.h.

#define DMA_GSTS_AFLS (((u32)1) << 28)

Definition at line 176 of file intel-iommu.h.

#define DMA_GSTS_CFIS (((u32)1) << 23)

Definition at line 181 of file intel-iommu.h.

#define DMA_GSTS_FLS (((u32)1) << 29)

Definition at line 175 of file intel-iommu.h.

#define DMA_GSTS_IRES (((u32)1) << 25)

Definition at line 180 of file intel-iommu.h.

#define DMA_GSTS_IRTPS (((u32)1) << 24)

Definition at line 179 of file intel-iommu.h.

#define DMA_GSTS_QIES (((u32)1) << 26)

Definition at line 178 of file intel-iommu.h.

#define DMA_GSTS_RTPS (((u32)1) << 30)

Definition at line 174 of file intel-iommu.h.

#define DMA_GSTS_TES (((u32)1) << 31)

Definition at line 173 of file intel-iommu.h.

#define DMA_GSTS_WBFS (((u32)1) << 27)

Definition at line 177 of file intel-iommu.h.

#define DMA_ID_TLB_ADDR ( addr ) (addr)

Definition at line 154 of file intel-iommu.h.

#define DMA_ID_TLB_ADDR_MASK ( mask ) (mask)

Definition at line 155 of file intel-iommu.h.

#define DMA_ID_TLB_DID ( id ) (((u64)((id & 0xffff) << 16)))

Definition at line 152 of file intel-iommu.h.

#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)

Definition at line 148 of file intel-iommu.h.

#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)

Definition at line 147 of file intel-iommu.h.

#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)

Definition at line 153 of file intel-iommu.h.

#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)

Definition at line 149 of file intel-iommu.h.

#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)

Definition at line 150 of file intel-iommu.h.

#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)

Definition at line 151 of file intel-iommu.h.

#define DMA_PMEN_EPM (((u32)1)<<31)

Definition at line 158 of file intel-iommu.h.

#define DMA_PMEN_PRS (((u32)1)<<0)

Definition at line 159 of file intel-iommu.h.

#define DMA_TLB_DID ( id ) (((u64)((id) & 0xffff)) << 32)

Definition at line 140 of file intel-iommu.h.

#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)

Definition at line 134 of file intel-iommu.h.

#define DMA_TLB_FLUSH_GRANU_OFFSET 60

Definition at line 132 of file intel-iommu.h.

#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)

Definition at line 133 of file intel-iommu.h.

#define DMA_TLB_IAIG ( val ) (((val) >> 57) & 7)

Definition at line 137 of file intel-iommu.h.

#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)

Definition at line 142 of file intel-iommu.h.

#define DMA_TLB_IIRG ( type ) ((type >> 60) & 7)

Definition at line 136 of file intel-iommu.h.

#define DMA_TLB_IVT (((u64)1) << 63)

Definition at line 141 of file intel-iommu.h.

#define DMA_TLB_MAX_SIZE (0x3f)

Definition at line 143 of file intel-iommu.h.

#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)

Definition at line 135 of file intel-iommu.h.

#define DMA_TLB_READ_DRAIN (((u64)1) << 49)

Definition at line 138 of file intel-iommu.h.

#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)

Definition at line 139 of file intel-iommu.h.

#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */

Definition at line 48 of file intel-iommu.h.

#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */

Definition at line 37 of file intel-iommu.h.

#define DMAR_CCMD_REG 0x28 /* Context command reg */

Definition at line 42 of file intel-iommu.h.

#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */

Definition at line 38 of file intel-iommu.h.

#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */

Definition at line 46 of file intel-iommu.h.

#define DMAR_FECTL_REG 0x38 /* Fault control register */

Definition at line 44 of file intel-iommu.h.

#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */

Definition at line 45 of file intel-iommu.h.

#define DMAR_FEUADDR_REG 0x44 /* Upper address register */

Definition at line 47 of file intel-iommu.h.

#define DMAR_FSTS_REG 0x34 /* Fault Status register */

Definition at line 43 of file intel-iommu.h.

#define DMAR_GCMD_REG 0x18 /* Global command register */

Definition at line 39 of file intel-iommu.h.

#define DMAR_GSTS_REG 0x1c /* Global status register */

Definition at line 40 of file intel-iommu.h.

#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */

Definition at line 58 of file intel-iommu.h.

#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */

Definition at line 56 of file intel-iommu.h.

#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */

Definition at line 57 of file intel-iommu.h.

#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */

Definition at line 54 of file intel-iommu.h.

#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */

Definition at line 55 of file intel-iommu.h.

#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */

Definition at line 59 of file intel-iommu.h.

#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */

Definition at line 52 of file intel-iommu.h.

#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */

Definition at line 53 of file intel-iommu.h.

#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */

Definition at line 50 of file intel-iommu.h.

#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */

Definition at line 51 of file intel-iommu.h.

#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */

Definition at line 49 of file intel-iommu.h.

#define DMAR_RTADDR_REG 0x20 /* Root entry table */

Definition at line 41 of file intel-iommu.h.

#define DMAR_VER_MAJOR ( v ) (((v) & 0xf0) >> 4)

Definition at line 84 of file intel-iommu.h.

#define DMAR_VER_MINOR ( v ) ((v) & 0x0f)

Definition at line 85 of file intel-iommu.h.

#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */

Definition at line 36 of file intel-iommu.h.

#define ecap_coherent ( e ) ((e) & 0x1)

Definition at line 122 of file intel-iommu.h.

#define ecap_dev_iotlb_support ( e ) (((e) >> 2) & 0x1)

Definition at line 127 of file intel-iommu.h.

#define ecap_eim_support ( e ) ((e >> 4) & 0x1)

Definition at line 125 of file intel-iommu.h.

#define ecap_iotlb_offset ( e ) ((((e) >> 8) & 0x3ff) * 16)

Definition at line 119 of file intel-iommu.h.

#define ecap_ir_support ( e ) ((e >> 3) & 0x1)

Definition at line 126 of file intel-iommu.h.

#define ecap_max_handle_mask ( e ) ((e >> 20) & 0xf)

Definition at line 128 of file intel-iommu.h.

#define ecap_max_iotlb_offset ( e ) (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)

Definition at line 120 of file intel-iommu.h.

#define ecap_niotlb_iunits ( e ) ((((e) >> 24) & 0xff) + 1)

Definition at line 118 of file intel-iommu.h.

#define ecap_pass_through ( e ) ((e >> 6) & 0x1)

Definition at line 124 of file intel-iommu.h.

#define ecap_qis ( e ) ((e) & 0x2)

Definition at line 123 of file intel-iommu.h.

#define ecap_sc_support ( e ) ((e >> 7) & 0x1) /* Snooping Control */

Definition at line 129 of file intel-iommu.h.

#define IOMMU_WAIT_OP	(	iommu,
		offset,
		op,
		cond,
		sts
	)

Value:

do {                                    \
	cycles_t start_time = get_cycles();                \
    while (1) {                         \
        sts = op(iommu->reg + offset);              \
        if (cond)                       \
            break;                      \
        if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
            panic("DMAR hardware is malfunctioning\n"); \
        cpu_relax();                        \
    }                               \
} while (0)

Definition at line 215 of file intel-iommu.h.

#define OFFSET_STRIDE (9)

Definition at line 61 of file intel-iommu.h.

#define QI_CC_DID ( did ) (((u64)did) << 16)

Definition at line 260 of file intel-iommu.h.

#define QI_CC_FM ( fm ) (((u64)fm) << 48)

Definition at line 258 of file intel-iommu.h.

#define QI_CC_GRAN ( gran ) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))

Definition at line 261 of file intel-iommu.h.

#define QI_CC_SID ( sid ) (((u64)sid) << 32)

Definition at line 259 of file intel-iommu.h.

#define QI_CC_TYPE 0x1

Definition at line 237 of file intel-iommu.h.

#define QI_DEV_IOTLB_ADDR ( addr ) ((u64)(addr) & VTD_PAGE_MASK)

Definition at line 265 of file intel-iommu.h.

#define QI_DEV_IOTLB_MAX_INVS 32

Definition at line 267 of file intel-iommu.h.

#define QI_DEV_IOTLB_QDEP ( qdep ) (((qdep) & 0x1f) << 16)

Definition at line 264 of file intel-iommu.h.

#define QI_DEV_IOTLB_SID ( sid ) ((u64)((sid) & 0xffff) << 32)

Definition at line 263 of file intel-iommu.h.

#define QI_DEV_IOTLB_SIZE 1

Definition at line 266 of file intel-iommu.h.

#define QI_DIOTLB_TYPE 0x3

Definition at line 239 of file intel-iommu.h.

#define QI_IEC_IIDEX ( idx ) (((u64)(idx & 0xffff) << 32))

Definition at line 244 of file intel-iommu.h.

#define QI_IEC_IM ( m ) (((u64)(m & 0x1f) << 27))

Definition at line 245 of file intel-iommu.h.

#define QI_IEC_SELECTIVE (((u64)1) << 4)

Definition at line 243 of file intel-iommu.h.

#define QI_IEC_TYPE 0x4

Definition at line 240 of file intel-iommu.h.

#define QI_IOTLB_ADDR ( addr ) (((u64)addr) & VTD_PAGE_MASK)

Definition at line 254 of file intel-iommu.h.

#define QI_IOTLB_AM ( am ) (((u8)am))

Definition at line 256 of file intel-iommu.h.

#define QI_IOTLB_DID ( did ) (((u64)did) << 16)

Definition at line 250 of file intel-iommu.h.

#define QI_IOTLB_DR ( dr ) (((u64)dr) << 7)

Definition at line 251 of file intel-iommu.h.

#define QI_IOTLB_DW ( dw ) (((u64)dw) << 6)

Definition at line 252 of file intel-iommu.h.

#define QI_IOTLB_GRAN ( gran ) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))

Definition at line 253 of file intel-iommu.h.

#define QI_IOTLB_IH ( ih ) (((u64)ih) << 6)

Definition at line 255 of file intel-iommu.h.

#define QI_IOTLB_TYPE 0x2

Definition at line 238 of file intel-iommu.h.

#define QI_IWD_STATUS_DATA ( d ) (((u64)d) << 32)

Definition at line 247 of file intel-iommu.h.

#define QI_IWD_STATUS_WRITE (((u64)1) << 5)

Definition at line 248 of file intel-iommu.h.

#define QI_IWD_TYPE 0x5

Definition at line 241 of file intel-iommu.h.

#define QI_LENGTH 256 /* queue length */

Definition at line 228 of file intel-iommu.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

QI_FREE
QI_IN_USE
QI_DONE
QI_ABORT

Definition at line 230 of file intel-iommu.h.

anonymous enum

Enumerator:

SR_DMAR_FECTL_REG
SR_DMAR_FEDATA_REG
SR_DMAR_FEADDR_REG
SR_DMAR_FEUADDR_REG
MAX_SR_DMAR_REGS

Definition at line 301 of file intel-iommu.h.

Function Documentation

int alloc_iommu ( struct dmar_drhd_unit * drhd )

Definition at line 643 of file dmar.c.

void dmar_disable_qi ( struct intel_iommu * iommu )

Definition at line 948 of file dmar.c.

int dmar_enable_qi ( struct intel_iommu * iommu )

Definition at line 1013 of file dmar.c.

int dmar_find_matched_atsr_unit ( struct pci_dev * dev )

Definition at line 3529 of file intel-iommu.c.

struct dmar_drhd_unit* dmar_find_matched_drhd_unit ( struct pci_dev * dev )

read

Definition at line 392 of file dmar.c.

int dmar_ir_support ( void )

Definition at line 1342 of file dmar.c.

int dmar_reenable_qi ( struct intel_iommu * iommu )

Definition at line 1317 of file dmar.c.

void free_iommu ( struct intel_iommu * iommu )

Definition at line 708 of file dmar.c.

void qi_flush_context	(	struct intel_iommu *	iommu,
		u16	did,
		u16	sid,
		u8	fm,
		u64	type
	)

Definition at line 890 of file dmar.c.

void qi_flush_dev_iotlb	(	struct intel_iommu *	iommu,
		u16	sid,
		u16	qdep,
		u64	addr,
		unsigned	mask
	)

Definition at line 924 of file dmar.c.

void qi_flush_iotlb	(	struct intel_iommu *	iommu,
		u16	did,
		u64	addr,
		unsigned int	size_order,
		u64	type
	)

Definition at line 902 of file dmar.c.

void qi_global_iec ( struct intel_iommu * iommu )

Definition at line 879 of file dmar.c.

int qi_submit_sync	(	struct qi_desc *	desc,
		struct intel_iommu *	iommu
	)

Definition at line 800 of file dmar.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation