|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Data Structures | |
| union | intel_mid_dma_ctl_lo |
| union | intel_mid_dma_ctl_hi |
| union | intel_mid_dma_cfg_lo |
| union | intel_mid_dma_cfg_hi |
| struct | intel_mid_dma_chan |
| struct | middma_device |
| struct | intel_mid_dma_desc |
| struct | intel_mid_dma_lli |
Macros | |
| #define | INTEL_MID_DMA_DRIVER_VERSION "1.1.0" |
| #define | REG_BIT0 0x00000001 |
| #define | REG_BIT8 0x00000100 |
| #define | INT_MASK_WE 0x8 |
| #define | CLEAR_DONE 0xFFFFEFFF |
| #define | UNMASK_INTR_REG(chan_num) ((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num)) |
| #define | MASK_INTR_REG(chan_num) (REG_BIT8 << chan_num) |
| #define | ENABLE_CHANNEL(chan_num) ((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num)) |
| #define | DISABLE_CHANNEL(chan_num) (REG_BIT8 << chan_num) |
| #define | DESCS_PER_CHANNEL 16 |
| #define | DMA_REG_SIZE 0x400 |
| #define | DMA_CH_SIZE 0x58 |
| #define | SAR 0x00 /* Source Address Register*/ |
| #define | DAR 0x08 /* Destination Address Register*/ |
| #define | LLP 0x10 /* Linked List Pointer Register*/ |
| #define | CTL_LOW 0x18 /* Control Register*/ |
| #define | CTL_HIGH 0x1C /* Control Register*/ |
| #define | CFG_LOW 0x40 /* Configuration Register Low*/ |
| #define | CFG_HIGH 0x44 /* Configuration Register high*/ |
| #define | STATUS_TFR 0x2E8 |
| #define | STATUS_BLOCK 0x2F0 |
| #define | STATUS_ERR 0x308 |
| #define | RAW_TFR 0x2C0 |
| #define | RAW_BLOCK 0x2C8 |
| #define | RAW_ERR 0x2E0 |
| #define | MASK_TFR 0x310 |
| #define | MASK_BLOCK 0x318 |
| #define | MASK_SRC_TRAN 0x320 |
| #define | MASK_DST_TRAN 0x328 |
| #define | MASK_ERR 0x330 |
| #define | CLEAR_TFR 0x338 |
| #define | CLEAR_BLOCK 0x340 |
| #define | CLEAR_SRC_TRAN 0x348 |
| #define | CLEAR_DST_TRAN 0x350 |
| #define | CLEAR_ERR 0x358 |
| #define | INTR_STATUS 0x360 |
| #define | DMA_CFG 0x398 |
| #define | DMA_CHAN_EN 0x3A0 |
Enumerations | |
| enum | intel_mid_dma_state { RUNNING = 0, SUSPENDED } |
Functions | |
| struct intel_mid_dma_lli | __attribute__ ((packed)) |
| int | dma_resume (struct device *dev) |
Variables | |
| dma_addr_t | sar |
| dma_addr_t | dar |
| dma_addr_t | llp |
| u32 | ctl_lo |
| u32 | ctl_hi |
| #define CFG_HIGH 0x44 /* Configuration Register high*/ |
Definition at line 61 of file intel_mid_dma_regs.h.
| #define CFG_LOW 0x40 /* Configuration Register Low*/ |
Definition at line 60 of file intel_mid_dma_regs.h.
| #define CLEAR_BLOCK 0x340 |
Definition at line 78 of file intel_mid_dma_regs.h.
| #define CLEAR_DONE 0xFFFFEFFF |
Definition at line 37 of file intel_mid_dma_regs.h.
| #define CLEAR_DST_TRAN 0x350 |
Definition at line 80 of file intel_mid_dma_regs.h.
| #define CLEAR_ERR 0x358 |
Definition at line 81 of file intel_mid_dma_regs.h.
| #define CLEAR_SRC_TRAN 0x348 |
Definition at line 79 of file intel_mid_dma_regs.h.
| #define CLEAR_TFR 0x338 |
Definition at line 77 of file intel_mid_dma_regs.h.
| #define CTL_HIGH 0x1C /* Control Register*/ |
Definition at line 59 of file intel_mid_dma_regs.h.
| #define CTL_LOW 0x18 /* Control Register*/ |
Definition at line 58 of file intel_mid_dma_regs.h.
| #define DAR 0x08 /* Destination Address Register*/ |
Definition at line 56 of file intel_mid_dma_regs.h.
| #define DESCS_PER_CHANNEL 16 |
Definition at line 48 of file intel_mid_dma_regs.h.
Definition at line 45 of file intel_mid_dma_regs.h.
| #define DMA_CFG 0x398 |
Definition at line 84 of file intel_mid_dma_regs.h.
| #define DMA_CH_SIZE 0x58 |
Definition at line 52 of file intel_mid_dma_regs.h.
| #define DMA_CHAN_EN 0x3A0 |
Definition at line 85 of file intel_mid_dma_regs.h.
| #define DMA_REG_SIZE 0x400 |
Definition at line 51 of file intel_mid_dma_regs.h.
Definition at line 42 of file intel_mid_dma_regs.h.
| #define INT_MASK_WE 0x8 |
Definition at line 36 of file intel_mid_dma_regs.h.
| #define INTEL_MID_DMA_DRIVER_VERSION "1.1.0" |
Definition at line 32 of file intel_mid_dma_regs.h.
| #define INTR_STATUS 0x360 |
Definition at line 83 of file intel_mid_dma_regs.h.
| #define LLP 0x10 /* Linked List Pointer Register*/ |
Definition at line 57 of file intel_mid_dma_regs.h.
| #define MASK_BLOCK 0x318 |
Definition at line 72 of file intel_mid_dma_regs.h.
| #define MASK_DST_TRAN 0x328 |
Definition at line 74 of file intel_mid_dma_regs.h.
| #define MASK_ERR 0x330 |
Definition at line 75 of file intel_mid_dma_regs.h.
Definition at line 40 of file intel_mid_dma_regs.h.
| #define MASK_SRC_TRAN 0x320 |
Definition at line 73 of file intel_mid_dma_regs.h.
| #define MASK_TFR 0x310 |
Definition at line 71 of file intel_mid_dma_regs.h.
| #define RAW_BLOCK 0x2C8 |
Definition at line 68 of file intel_mid_dma_regs.h.
| #define RAW_ERR 0x2E0 |
Definition at line 69 of file intel_mid_dma_regs.h.
| #define RAW_TFR 0x2C0 |
Definition at line 67 of file intel_mid_dma_regs.h.
| #define REG_BIT0 0x00000001 |
Definition at line 34 of file intel_mid_dma_regs.h.
| #define REG_BIT8 0x00000100 |
Definition at line 35 of file intel_mid_dma_regs.h.
| #define SAR 0x00 /* Source Address Register*/ |
Definition at line 55 of file intel_mid_dma_regs.h.
| #define STATUS_BLOCK 0x2F0 |
Definition at line 64 of file intel_mid_dma_regs.h.
| #define STATUS_ERR 0x308 |
Definition at line 65 of file intel_mid_dma_regs.h.
| #define STATUS_TFR 0x2E8 |
Definition at line 63 of file intel_mid_dma_regs.h.
Definition at line 38 of file intel_mid_dma_regs.h.
| enum intel_mid_dma_state |
Definition at line 203 of file intel_mid_dma_regs.h.
|
read |
Definition at line 171 of file esd_usb2.c.
dma_resume - PCI resume function
: PCI device structure
This function is called by OS when a power event occurs
Definition at line 1359 of file intel_mid_dma.c.
| u32 ctl_hi |
Definition at line 281 of file intel_mid_dma_regs.h.
| u32 ctl_lo |
Definition at line 280 of file intel_mid_dma_regs.h.
| dma_addr_t dar |
Definition at line 278 of file intel_mid_dma_regs.h.
| dma_addr_t llp |
Definition at line 279 of file intel_mid_dma_regs.h.
| dma_addr_t sar |
Definition at line 277 of file intel_mid_dma_regs.h.
1.8.2