Linux Kernel
3.7.1
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#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/pm.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/sfi.h>
#include <linux/module.h>
#include <asm/mrst.h>
#include <asm/intel_scu_ipc.h>
Go to the source code of this file.
Data Structures | |
struct | intel_scu_ipc_dev |
Macros | |
#define | IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ |
#define | IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ |
#define | IPCMSG_FW_UPDATE 0xFE /* Firmware update */ |
#define | IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ |
#define | IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ |
#define | IPC_CMD_PCNTRL_W 0 /* Register write */ |
#define | IPC_CMD_PCNTRL_R 1 /* Register read */ |
#define | IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ |
#define | IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ |
#define | IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ |
#define | IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ |
#define | IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ |
#define | IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ |
#define | IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ |
#define | IPC_READ_BUFFER 0x90 |
#define | IPC_I2C_CNTRL_ADDR 0 |
#define | I2C_DATA_ADDR 0x04 |
#define | IPC_I2C_WRITE 1 /* I2C Write command */ |
#define | IPC_I2C_READ 2 /* I2C Read command */ |
#define I2C_DATA_ADDR 0x04 |
Definition at line 89 of file intel_scu_ipc.c.
#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ |
Definition at line 61 of file intel_scu_ipc.c.
Definition at line 41 of file intel_scu_ipc.c.
Definition at line 40 of file intel_scu_ipc.c.
Definition at line 39 of file intel_scu_ipc.c.
#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ |
Definition at line 65 of file intel_scu_ipc.c.
#define IPC_I2C_CNTRL_ADDR 0 |
Definition at line 88 of file intel_scu_ipc.c.
#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ |
Definition at line 66 of file intel_scu_ipc.c.
Definition at line 440 of file intel_scu_ipc.c.
Definition at line 439 of file intel_scu_ipc.c.
#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ |
Definition at line 62 of file intel_scu_ipc.c.
#define IPC_READ_BUFFER 0x90 |
Definition at line 86 of file intel_scu_ipc.c.
Definition at line 63 of file intel_scu_ipc.c.
#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ |
Definition at line 33 of file intel_scu_ipc.c.
#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ |
Definition at line 36 of file intel_scu_ipc.c.
#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ |
Definition at line 34 of file intel_scu_ipc.c.
#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ |
Definition at line 35 of file intel_scu_ipc.c.
#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ |
Definition at line 32 of file intel_scu_ipc.c.
EXPORT_SYMBOL | ( | intel_scu_ipc_ioread8 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_ioread16 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_ioread32 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_iowrite8 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_iowrite16 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_iowrite32 | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_readv | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_writev | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_update_register | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_simple_command | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_command | ) |
EXPORT_SYMBOL | ( | intel_scu_ipc_i2c_cntrl | ) |
intel_scu_ipc_command - command with data : command : sub type : input data : input length in dwords : output data : output length in dwords
Issue a command to the SCU which involves data transfers. Do the data copies under the lock but leave it for the caller to interpret
Definition at line 413 of file intel_scu_ipc.c.
intel_scu_ipc_i2c_cntrl - I2C read/write operations : I2C address + command bits : data to read/write
Perform an an I2C read/write operation via the SCU. All locking is handled for the caller. This function may sleep.
Returns an error code or 0 on success.
This has to be in the IPC driver for the locking.
Definition at line 454 of file intel_scu_ipc.c.
intel_scu_ipc_ioread16 - read a word via the SCU : register on SCU : return pointer for read word
Read a register pair. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 236 of file intel_scu_ipc.c.
intel_scu_ipc_ioread32 - read a dword via the SCU : register on SCU : return pointer for read dword
Read four registers. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 253 of file intel_scu_ipc.c.
intel_scu_ipc_ioread8 - read a word via the SCU : register on SCU : return pointer for read byte
Read a single register. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 220 of file intel_scu_ipc.c.
intel_scu_ipc_iowrite16 - write a word via the SCU : register on SCU : word to write
Write two registers. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 286 of file intel_scu_ipc.c.
intel_scu_ipc_iowrite32 - write a dword via the SCU : register on SCU : dword to write
Write four registers. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 303 of file intel_scu_ipc.c.
intel_scu_ipc_iowrite8 - write a byte via the SCU : register on SCU : byte to write
Write a single register. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
This function may sleep.
Definition at line 270 of file intel_scu_ipc.c.
intel_scu_ipc_readvv - read a set of registers : register list : bytes to return : length of array
Read registers. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
The largest array length permitted by the hardware is 5 items.
This function may sleep.
Definition at line 323 of file intel_scu_ipc.c.
intel_scu_ipc_simple_command - send a simple command : command : sub type
Issue a simple command to the SCU. Do not use this interface if you must then access data as any data values may be overwritten by another SCU access by the time this function returns.
This function may sleep. Locking for SCU accesses is handled for the caller.
Definition at line 384 of file intel_scu_ipc.c.
intel_scu_ipc_update_register - r/m/w a register : register address : bits to update : mask of bits to update
Read-modify-write power control unit register. The first data argument must be register value and second is mask value mask is a bitmap that indicates which bits to update. 0 = masked. Don't modify this bit, 1 = modify this bit. returns 0 on success or an error code.
This function may sleep. Locking between SCU accesses is handled for the caller.
Definition at line 365 of file intel_scu_ipc.c.
intel_scu_ipc_writev - write a set of registers : register list : bytes to write : length of array
Write registers. Returns 0 on success or an error code. All locking between SCU accesses is handled for the caller.
The largest array length permitted by the hardware is 5 items.
This function may sleep.
Definition at line 343 of file intel_scu_ipc.c.
MODULE_AUTHOR | ( | "Sreedhara DS <sreedhara.ds@intel.com>" | ) |
MODULE_DEVICE_TABLE | ( | pci | , |
pci_ids | |||
) |
module_exit | ( | intel_scu_ipc_exit | ) |
module_init | ( | intel_scu_ipc_init | ) |
MODULE_LICENSE | ( | "GPL" | ) |