intel_scu_ipc.c

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/*
 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
 *
 * (C) Copyright 2008-2010 Intel Corporation
 * Author: Sreedhara DS ([email protected])
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 *
 * SCU running in ARC processor communicates with other entity running in IA
 * core through IPC mechanism which in turn messaging between IA core ad SCU.
 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
 * along with other APIs.
 */
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/pm.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/sfi.h>
#include <linux/module.h>
#include <asm/mrst.h>
#include <asm/intel_scu_ipc.h>

/* IPC defines the following message types */
#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */

/* Command id associated with message IPCMSG_PCNTRL */
#define IPC_CMD_PCNTRL_W      0 /* Register write */
#define IPC_CMD_PCNTRL_R      1 /* Register read */
#define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */

/*
 * IPC register summary
 *
 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
 * To read or write information to the SCU, driver writes to IPC-1 memory
 * mapped registers (base address 0xFF11C000). The following is the IPC
 * mechanism
 *
 * 1. IA core cDMI interface claims this transaction and converts it to a
 *    Transaction Layer Packet (TLP) message which is sent across the cDMI.
 *
 * 2. South Complex cDMI block receives this message and writes it to
 *    the IPC-1 register block, causing an interrupt to the SCU
 *
 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
 *    message handler is called within firmware.
 */

#define IPC_BASE_ADDR     0xFF11C000    /* IPC1 base register address */
#define IPC_MAX_ADDR      0x100     /* Maximum IPC regisers */
#define IPC_WWBUF_SIZE    20        /* IPC Write buffer Size */
#define IPC_RWBUF_SIZE    20        /* IPC Read buffer Size */
#define IPC_I2C_BASE      0xFF12B000    /* I2C control register base address */
#define IPC_I2C_MAX_ADDR  0x10      /* Maximum I2C regisers */

static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
static void ipc_remove(struct pci_dev *pdev);

struct intel_scu_ipc_dev {
    struct pci_dev *pdev;
    void __iomem *ipc_base;
    void __iomem *i2c_base;
};

static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */

static int platform;        /* Platform type */

/*
 * IPC Read Buffer (Read Only):
 * 16 byte buffer for receiving data from SCU, if IPC command
 * processing results in response data
 */
#define IPC_READ_BUFFER     0x90

#define IPC_I2C_CNTRL_ADDR  0
#define I2C_DATA_ADDR       0x04

static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */

/*
 * Command Register (Write Only):
 * A write to this register results in an interrupt to the SCU core processor
 * Format:
 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
 */
static inline void ipc_command(u32 cmd) /* Send ipc command */
{
    writel(cmd, ipcdev.ipc_base);
}

/*
 * IPC Write Buffer (Write Only):
 * 16-byte buffer for sending data associated with IPC command to
 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
 */
static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
{
    writel(data, ipcdev.ipc_base + 0x80 + offset);
}

/*
 * Status Register (Read Only):
 * Driver will read this register to get the ready/busy status of the IPC
 * block and error status of the IPC command that was just processed by SCU
 * Format:
 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
 */

static inline u8 ipc_read_status(void)
{
    return __raw_readl(ipcdev.ipc_base + 0x04);
}

static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
{
    return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}

static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
{
    return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}

static inline int busy_loop(void) /* Wait till scu status is busy */
{
    u32 status = 0;
    u32 loop_count = 0;

    status = ipc_read_status();
    while (status & 1) {
        udelay(1); /* scu processing time is in few u secods */
        status = ipc_read_status();
        loop_count++;
        /* break if scu doesn't reset busy bit after huge retry */
        if (loop_count > 100000) {
            dev_err(&ipcdev.pdev->dev, "IPC timed out");
            return -ETIMEDOUT;
        }
    }
    if ((status >> 1) & 1)
        return -EIO;

    return 0;
}

/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
{
    int nc;
    u32 offset = 0;
    int err;
    u8 cbuf[IPC_WWBUF_SIZE] = { };
    u32 *wbuf = (u32 *)&cbuf;

    mutex_lock(&ipclock);

    memset(cbuf, 0, sizeof(cbuf));

    if (ipcdev.pdev == NULL) {
        mutex_unlock(&ipclock);
        return -ENODEV;
    }

    for (nc = 0; nc < count; nc++, offset += 2) {
        cbuf[offset] = addr[nc];
        cbuf[offset + 1] = addr[nc] >> 8;
    }

    if (id == IPC_CMD_PCNTRL_R) {
        for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
            ipc_data_writel(wbuf[nc], offset);
        ipc_command((count*2) << 16 |  id << 12 | 0 << 8 | op);
    } else if (id == IPC_CMD_PCNTRL_W) {
        for (nc = 0; nc < count; nc++, offset += 1)
            cbuf[offset] = data[nc];
        for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
            ipc_data_writel(wbuf[nc], offset);
        ipc_command((count*3) << 16 |  id << 12 | 0 << 8 | op);
    } else if (id == IPC_CMD_PCNTRL_M) {
        cbuf[offset] = data[0];
        cbuf[offset + 1] = data[1];
        ipc_data_writel(wbuf[0], 0); /* Write wbuff */
        ipc_command(4 << 16 |  id << 12 | 0 << 8 | op);
    }

    err = busy_loop();
    if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
        /* Workaround: values are read as 0 without memcpy_fromio */
        memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
        for (nc = 0; nc < count; nc++)
            data[nc] = ipc_data_readb(nc);
    }
    mutex_unlock(&ipclock);
    return err;
}

int intel_scu_ipc_ioread8(u16 addr, u8 *data)
{
    return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
}
EXPORT_SYMBOL(intel_scu_ipc_ioread8);

int intel_scu_ipc_ioread16(u16 addr, u16 *data)
{
    u16 x[2] = {addr, addr + 1 };
    return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
}
EXPORT_SYMBOL(intel_scu_ipc_ioread16);

int intel_scu_ipc_ioread32(u16 addr, u32 *data)
{
    u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
    return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
}
EXPORT_SYMBOL(intel_scu_ipc_ioread32);

int intel_scu_ipc_iowrite8(u16 addr, u8 data)
{
    return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
}
EXPORT_SYMBOL(intel_scu_ipc_iowrite8);

int intel_scu_ipc_iowrite16(u16 addr, u16 data)
{
    u16 x[2] = {addr, addr + 1 };
    return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
}
EXPORT_SYMBOL(intel_scu_ipc_iowrite16);

int intel_scu_ipc_iowrite32(u16 addr, u32 data)
{
    u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
    return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
}
EXPORT_SYMBOL(intel_scu_ipc_iowrite32);

int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
{
    return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
}
EXPORT_SYMBOL(intel_scu_ipc_readv);

int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
{
    return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
}
EXPORT_SYMBOL(intel_scu_ipc_writev);


int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
{
    u8 data[2] = { bits, mask };
    return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
}
EXPORT_SYMBOL(intel_scu_ipc_update_register);

int intel_scu_ipc_simple_command(int cmd, int sub)
{
    int err;

    mutex_lock(&ipclock);
    if (ipcdev.pdev == NULL) {
        mutex_unlock(&ipclock);
        return -ENODEV;
    }
    ipc_command(sub << 12 | cmd);
    err = busy_loop();
    mutex_unlock(&ipclock);
    return err;
}
EXPORT_SYMBOL(intel_scu_ipc_simple_command);

int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
                            u32 *out, int outlen)
{
    int i, err;

    mutex_lock(&ipclock);
    if (ipcdev.pdev == NULL) {
        mutex_unlock(&ipclock);
        return -ENODEV;
    }

    for (i = 0; i < inlen; i++)
        ipc_data_writel(*in++, 4 * i);

    ipc_command((inlen << 16) | (sub << 12) | cmd);
    err = busy_loop();

    for (i = 0; i < outlen; i++)
        *out++ = ipc_data_readl(4 * i);

    mutex_unlock(&ipclock);
    return err;
}
EXPORT_SYMBOL(intel_scu_ipc_command);

/*I2C commands */
#define IPC_I2C_WRITE 1 /* I2C Write command */
#define IPC_I2C_READ  2 /* I2C Read command */

int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
{
    u32 cmd = 0;

    mutex_lock(&ipclock);
    if (ipcdev.pdev == NULL) {
        mutex_unlock(&ipclock);
        return -ENODEV;
    }
    cmd = (addr >> 24) & 0xFF;
    if (cmd == IPC_I2C_READ) {
        writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
        /* Write not getting updated without delay */
        mdelay(1);
        *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
    } else if (cmd == IPC_I2C_WRITE) {
        writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
        mdelay(1);
        writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
    } else {
        dev_err(&ipcdev.pdev->dev,
            "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);

        mutex_unlock(&ipclock);
        return -EIO;
    }
    mutex_unlock(&ipclock);
    return 0;
}
EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);

/*
 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
 * When ioc bit is set to 1, caller api must wait for interrupt handler called
 * which in turn unlocks the caller api. Currently this is not used
 *
 * This is edge triggered so we need take no action to clear anything
 */
static irqreturn_t ioc(int irq, void *dev_id)
{
    return IRQ_HANDLED;
}

static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
    int err;
    resource_size_t pci_resource;

    if (ipcdev.pdev)        /* We support only one SCU */
        return -EBUSY;

    ipcdev.pdev = pci_dev_get(dev);

    err = pci_enable_device(dev);
    if (err)
        return err;

    err = pci_request_regions(dev, "intel_scu_ipc");
    if (err)
        return err;

    pci_resource = pci_resource_start(dev, 0);
    if (!pci_resource)
        return -ENOMEM;

    if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
        return -EBUSY;

    ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
    if (!ipcdev.ipc_base)
        return -ENOMEM;

    ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
    if (!ipcdev.i2c_base) {
        iounmap(ipcdev.ipc_base);
        return -ENOMEM;
    }

    intel_scu_devices_create();

    return 0;
}

static void ipc_remove(struct pci_dev *pdev)
{
    free_irq(pdev->irq, &ipcdev);
    pci_release_regions(pdev);
    pci_dev_put(ipcdev.pdev);
    iounmap(ipcdev.ipc_base);
    iounmap(ipcdev.i2c_base);
    ipcdev.pdev = NULL;
    intel_scu_devices_destroy();
}

static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
    {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
    { 0,}
};
MODULE_DEVICE_TABLE(pci, pci_ids);

static struct pci_driver ipc_driver = {
    .name = "intel_scu_ipc",
    .id_table = pci_ids,
    .probe = ipc_probe,
    .remove = ipc_remove,
};


static int __init intel_scu_ipc_init(void)
{
    platform = mrst_identify_cpu();
    if (platform == 0)
        return -ENODEV;
    return  pci_register_driver(&ipc_driver);
}

static void __exit intel_scu_ipc_exit(void)
{
    pci_unregister_driver(&ipc_driver);
}

MODULE_AUTHOR("Sreedhara DS <[email protected]>");
MODULE_DESCRIPTION("Intel SCU IPC driver");
MODULE_LICENSE("GPL");

module_init(intel_scu_ipc_init);
module_exit(intel_scu_ipc_exit);