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ips.h
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1 /*****************************************************************************/
2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 1999 IBM Corporation */
9 /* Copyright (C) 2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions should be mailed to: */
46 /* [email protected] */
47 /* */
48 /*****************************************************************************/
49 
50 #ifndef _IPS_H_
51  #define _IPS_H_
52 
53 #include <linux/nmi.h>
54  #include <asm/uaccess.h>
55  #include <asm/io.h>
56 
57  /*
58  * Some handy macros
59  */
60  #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
61  #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
62  #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
63  (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
64  (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
65  #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
66  (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
67  (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
68  #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
69  #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
70  #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
71  (IPS_IS_TROMBONE(ha) && \
72  (ips_force_i2o))) ? 1 : 0)
73  #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
74  ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
75  (ips_force_memio))) ? 1 : 0)
76 
77  #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
78  #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
79  #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
80  sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
81 
82  #define IPS_PRINTK(level, pcidev, format, arg...) \
83  dev_printk(level , &((pcidev)->dev) , format , ## arg)
84 
85  #define MDELAY(n) \
86  do { \
87  mdelay(n); \
88  touch_nmi_watchdog(); \
89  } while (0)
90 
91  #ifndef min
92  #define min(x,y) ((x) < (y) ? x : y)
93  #endif
94 
95  #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
96  #define __iomem
97  #endif
98 
99  #define pci_dma_hi32(a) ((a >> 16) >> 16)
100  #define pci_dma_lo32(a) (a & 0xffffffff)
101 
102  #if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
103  #define IPS_ENABLE_DMA64 (1)
104  #else
105  #define IPS_ENABLE_DMA64 (0)
106  #endif
107 
108  /*
109  * Adapter address map equates
110  */
111  #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
112  #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
113  #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
114  #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
115  #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
116  #define IPS_REG_SQER 0x28 /* Status Q End Reg */
117  #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
118  #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
119  #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
120  #define IPS_REG_CBSP 0x07 /* CBSP register */
121  #define IPS_REG_FLAP 0x18 /* Flash address port */
122  #define IPS_REG_FLDP 0x1C /* Flash data port */
123  #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
124  #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
125  #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
126  #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
127  #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
128  #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
129  #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
130  #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
131 
132  /*
133  * Adapter register bit equates
134  */
135  #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
136  #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
137  #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
138  #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
139  #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
140  #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
141  #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
142  #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
143  #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
144  #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
145  #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
146  #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
147  #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
148  #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
149 
150  /*
151  * Adapter Command ID Equates
152  */
153  #define IPS_CMD_GET_LD_INFO 0x19
154  #define IPS_CMD_GET_SUBSYS 0x40
155  #define IPS_CMD_READ_CONF 0x38
156  #define IPS_CMD_RW_NVRAM_PAGE 0xBC
157  #define IPS_CMD_READ 0x02
158  #define IPS_CMD_WRITE 0x03
159  #define IPS_CMD_FFDC 0xD7
160  #define IPS_CMD_ENQUIRY 0x05
161  #define IPS_CMD_FLUSH 0x0A
162  #define IPS_CMD_READ_SG 0x82
163  #define IPS_CMD_WRITE_SG 0x83
164  #define IPS_CMD_DCDB 0x04
165  #define IPS_CMD_DCDB_SG 0x84
166  #define IPS_CMD_EXTENDED_DCDB 0x95
167  #define IPS_CMD_EXTENDED_DCDB_SG 0x96
168  #define IPS_CMD_CONFIG_SYNC 0x58
169  #define IPS_CMD_ERROR_TABLE 0x17
170  #define IPS_CMD_DOWNLOAD 0x20
171  #define IPS_CMD_RW_BIOSFW 0x22
172  #define IPS_CMD_GET_VERSION_INFO 0xC6
173  #define IPS_CMD_RESET_CHANNEL 0x1A
174 
175  /*
176  * Adapter Equates
177  */
178  #define IPS_CSL 0xFF
179  #define IPS_POCL 0x30
180  #define IPS_NORM_STATE 0x00
181  #define IPS_MAX_ADAPTER_TYPES 3
182  #define IPS_MAX_ADAPTERS 16
183  #define IPS_MAX_IOCTL 1
184  #define IPS_MAX_IOCTL_QUEUE 8
185  #define IPS_MAX_QUEUE 128
186  #define IPS_BLKSIZE 512
187  #define IPS_MAX_SG 17
188  #define IPS_MAX_LD 8
189  #define IPS_MAX_CHANNELS 4
190  #define IPS_MAX_TARGETS 15
191  #define IPS_MAX_CHUNKS 16
192  #define IPS_MAX_CMDS 128
193  #define IPS_MAX_XFER 0x10000
194  #define IPS_NVRAM_P5_SIG 0xFFDDBB99
195  #define IPS_MAX_POST_BYTES 0x02
196  #define IPS_MAX_CONFIG_BYTES 0x02
197  #define IPS_GOOD_POST_STATUS 0x80
198  #define IPS_SEM_TIMEOUT 2000
199  #define IPS_IOCTL_COMMAND 0x0D
200  #define IPS_INTR_ON 0
201  #define IPS_INTR_IORL 1
202  #define IPS_FFDC 99
203  #define IPS_ADAPTER_ID 0xF
204  #define IPS_VENDORID_IBM 0x1014
205  #define IPS_VENDORID_ADAPTEC 0x9005
206  #define IPS_DEVICEID_COPPERHEAD 0x002E
207  #define IPS_DEVICEID_MORPHEUS 0x01BD
208  #define IPS_DEVICEID_MARCO 0x0250
209  #define IPS_SUBDEVICEID_4M 0x01BE
210  #define IPS_SUBDEVICEID_4L 0x01BF
211  #define IPS_SUBDEVICEID_4MX 0x0208
212  #define IPS_SUBDEVICEID_4LX 0x020E
213  #define IPS_SUBDEVICEID_5I2 0x0259
214  #define IPS_SUBDEVICEID_5I1 0x0258
215  #define IPS_SUBDEVICEID_6M 0x0279
216  #define IPS_SUBDEVICEID_6I 0x028C
217  #define IPS_SUBDEVICEID_7k 0x028E
218  #define IPS_SUBDEVICEID_7M 0x028F
219  #define IPS_IOCTL_SIZE 8192
220  #define IPS_STATUS_SIZE 4
221  #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
222  #define IPS_IMAGE_SIZE 500 * 1024
223  #define IPS_MEMMAP_SIZE 128
224  #define IPS_ONE_MSEC 1
225  #define IPS_ONE_SEC 1000
226 
227  /*
228  * Geometry Settings
229  */
230  #define IPS_COMP_HEADS 128
231  #define IPS_COMP_SECTORS 32
232  #define IPS_NORM_HEADS 254
233  #define IPS_NORM_SECTORS 63
234 
235  /*
236  * Adapter Basic Status Codes
237  */
238  #define IPS_BASIC_STATUS_MASK 0xFF
239  #define IPS_GSC_STATUS_MASK 0x0F
240  #define IPS_CMD_SUCCESS 0x00
241  #define IPS_CMD_RECOVERED_ERROR 0x01
242  #define IPS_INVAL_OPCO 0x03
243  #define IPS_INVAL_CMD_BLK 0x04
244  #define IPS_INVAL_PARM_BLK 0x05
245  #define IPS_BUSY 0x08
246  #define IPS_CMD_CMPLT_WERROR 0x0C
247  #define IPS_LD_ERROR 0x0D
248  #define IPS_CMD_TIMEOUT 0x0E
249  #define IPS_PHYS_DRV_ERROR 0x0F
250 
251  /*
252  * Adapter Extended Status Equates
253  */
254  #define IPS_ERR_SEL_TO 0xF0
255  #define IPS_ERR_OU_RUN 0xF2
256  #define IPS_ERR_HOST_RESET 0xF7
257  #define IPS_ERR_DEV_RESET 0xF8
258  #define IPS_ERR_RECOVERY 0xFC
259  #define IPS_ERR_CKCOND 0xFF
260 
261  /*
262  * Operating System Defines
263  */
264  #define IPS_OS_WINDOWS_NT 0x01
265  #define IPS_OS_NETWARE 0x02
266  #define IPS_OS_OPENSERVER 0x03
267  #define IPS_OS_UNIXWARE 0x04
268  #define IPS_OS_SOLARIS 0x05
269  #define IPS_OS_OS2 0x06
270  #define IPS_OS_LINUX 0x07
271  #define IPS_OS_FREEBSD 0x08
272 
273  /*
274  * Adapter Revision ID's
275  */
276  #define IPS_REVID_SERVERAID 0x02
277  #define IPS_REVID_NAVAJO 0x03
278  #define IPS_REVID_SERVERAID2 0x04
279  #define IPS_REVID_CLARINETP1 0x05
280  #define IPS_REVID_CLARINETP2 0x07
281  #define IPS_REVID_CLARINETP3 0x0D
282  #define IPS_REVID_TROMBONE32 0x0F
283  #define IPS_REVID_TROMBONE64 0x10
284 
285  /*
286  * NVRAM Page 5 Adapter Defines
287  */
288  #define IPS_ADTYPE_SERVERAID 0x01
289  #define IPS_ADTYPE_SERVERAID2 0x02
290  #define IPS_ADTYPE_NAVAJO 0x03
291  #define IPS_ADTYPE_KIOWA 0x04
292  #define IPS_ADTYPE_SERVERAID3 0x05
293  #define IPS_ADTYPE_SERVERAID3L 0x06
294  #define IPS_ADTYPE_SERVERAID4H 0x07
295  #define IPS_ADTYPE_SERVERAID4M 0x08
296  #define IPS_ADTYPE_SERVERAID4L 0x09
297  #define IPS_ADTYPE_SERVERAID4MX 0x0A
298  #define IPS_ADTYPE_SERVERAID4LX 0x0B
299  #define IPS_ADTYPE_SERVERAID5I2 0x0C
300  #define IPS_ADTYPE_SERVERAID5I1 0x0D
301  #define IPS_ADTYPE_SERVERAID6M 0x0E
302  #define IPS_ADTYPE_SERVERAID6I 0x0F
303  #define IPS_ADTYPE_SERVERAID7t 0x10
304  #define IPS_ADTYPE_SERVERAID7k 0x11
305  #define IPS_ADTYPE_SERVERAID7M 0x12
306 
307  /*
308  * Adapter Command/Status Packet Definitions
309  */
310  #define IPS_SUCCESS 0x01 /* Successfully completed */
311  #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
312  #define IPS_FAILURE 0x04 /* Completed with Error */
313 
314  /*
315  * Logical Drive Equates
316  */
317  #define IPS_LD_OFFLINE 0x02
318  #define IPS_LD_OKAY 0x03
319  #define IPS_LD_FREE 0x00
320  #define IPS_LD_SYS 0x06
321  #define IPS_LD_CRS 0x24
322 
323  /*
324  * DCDB Table Equates
325  */
326  #define IPS_NO_DISCONNECT 0x00
327  #define IPS_DISCONNECT_ALLOWED 0x80
328  #define IPS_NO_AUTO_REQSEN 0x40
329  #define IPS_DATA_NONE 0x00
330  #define IPS_DATA_UNK 0x00
331  #define IPS_DATA_IN 0x01
332  #define IPS_DATA_OUT 0x02
333  #define IPS_TRANSFER64K 0x08
334  #define IPS_NOTIMEOUT 0x00
335  #define IPS_TIMEOUT10 0x10
336  #define IPS_TIMEOUT60 0x20
337  #define IPS_TIMEOUT20M 0x30
338 
339  /*
340  * SCSI Inquiry Data Flags
341  */
342  #define IPS_SCSI_INQ_TYPE_DASD 0x00
343  #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
344  #define IPS_SCSI_INQ_LU_CONNECTED 0x00
345  #define IPS_SCSI_INQ_RD_REV2 0x02
346  #define IPS_SCSI_INQ_REV2 0x02
347  #define IPS_SCSI_INQ_REV3 0x03
348  #define IPS_SCSI_INQ_Address16 0x01
349  #define IPS_SCSI_INQ_Address32 0x02
350  #define IPS_SCSI_INQ_MedChanger 0x08
351  #define IPS_SCSI_INQ_MultiPort 0x10
352  #define IPS_SCSI_INQ_EncServ 0x40
353  #define IPS_SCSI_INQ_SoftReset 0x01
354  #define IPS_SCSI_INQ_CmdQue 0x02
355  #define IPS_SCSI_INQ_Linked 0x08
356  #define IPS_SCSI_INQ_Sync 0x10
357  #define IPS_SCSI_INQ_WBus16 0x20
358  #define IPS_SCSI_INQ_WBus32 0x40
359  #define IPS_SCSI_INQ_RelAdr 0x80
360 
361  /*
362  * SCSI Request Sense Data Flags
363  */
364  #define IPS_SCSI_REQSEN_VALID 0x80
365  #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
366  #define IPS_SCSI_REQSEN_NO_SENSE 0x00
367 
368  /*
369  * SCSI Mode Page Equates
370  */
371  #define IPS_SCSI_MP3_SoftSector 0x01
372  #define IPS_SCSI_MP3_HardSector 0x02
373  #define IPS_SCSI_MP3_Removeable 0x04
374  #define IPS_SCSI_MP3_AllocateSurface 0x08
375 
376  /*
377  * HA Flags
378  */
379 
380  #define IPS_HA_ENH_SG 0x1
381 
382  /*
383  * SCB Flags
384  */
385  #define IPS_SCB_MAP_SG 0x00008
386  #define IPS_SCB_MAP_SINGLE 0X00010
387 
388  /*
389  * Passthru stuff
390  */
391  #define IPS_COPPUSRCMD (('C'<<8) | 65)
392  #define IPS_COPPIOCCMD (('C'<<8) | 66)
393  #define IPS_NUMCTRLS (('C'<<8) | 68)
394  #define IPS_CTRLINFO (('C'<<8) | 69)
395 
396  /* flashing defines */
397  #define IPS_FW_IMAGE 0x00
398  #define IPS_BIOS_IMAGE 0x01
399  #define IPS_WRITE_FW 0x01
400  #define IPS_WRITE_BIOS 0x02
401  #define IPS_ERASE_BIOS 0x03
402  #define IPS_BIOS_HEADER 0xC0
403 
404  /* time oriented stuff */
405  #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
406  #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
407 
408  #define IPS_SECS_MIN 60
409  #define IPS_SECS_HOUR 3600
410  #define IPS_SECS_8HOURS 28800
411  #define IPS_SECS_DAY 86400
412  #define IPS_DAYS_NORMAL_YEAR 365
413  #define IPS_DAYS_LEAP_YEAR 366
414  #define IPS_EPOCH_YEAR 1970
415 
416  /*
417  * Scsi_Host Template
418  */
419  static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
420  static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
421  sector_t capacity, int geom[]);
422  static int ips_slave_configure(struct scsi_device *SDptr);
423 
424 /*
425  * Raid Command Formats
426  */
427 typedef struct {
428  uint8_t op_code;
429  uint8_t command_id;
430  uint8_t log_drv;
431  uint8_t sg_count;
432  uint32_t lba;
433  uint32_t sg_addr;
434  uint16_t sector_count;
435  uint8_t segment_4G;
436  uint8_t enhanced_sg;
437  uint32_t ccsar;
438  uint32_t cccr;
439 } IPS_IO_CMD, *PIPS_IO_CMD;
440 
441 typedef struct {
442  uint8_t op_code;
443  uint8_t command_id;
444  uint16_t reserved;
445  uint32_t reserved2;
446  uint32_t buffer_addr;
447  uint32_t reserved3;
448  uint32_t ccsar;
449  uint32_t cccr;
450 } IPS_LD_CMD, *PIPS_LD_CMD;
451 
452 typedef struct {
453  uint8_t op_code;
454  uint8_t command_id;
455  uint8_t reserved;
456  uint8_t reserved2;
457  uint32_t reserved3;
458  uint32_t buffer_addr;
459  uint32_t reserved4;
460 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
461 
462 typedef struct {
463  uint8_t op_code;
464  uint8_t command_id;
465  uint8_t channel;
466  uint8_t reserved3;
467  uint8_t reserved4;
468  uint8_t reserved5;
469  uint8_t reserved6;
470  uint8_t reserved7;
471  uint8_t reserved8;
472  uint8_t reserved9;
473  uint8_t reserved10;
474  uint8_t reserved11;
475  uint8_t reserved12;
476  uint8_t reserved13;
477  uint8_t reserved14;
478  uint8_t adapter_flag;
479 } IPS_RESET_CMD, *PIPS_RESET_CMD;
480 
481 typedef struct {
482  uint8_t op_code;
483  uint8_t command_id;
484  uint16_t reserved;
485  uint32_t reserved2;
486  uint32_t dcdb_address;
487  uint16_t reserved3;
488  uint8_t segment_4G;
489  uint8_t enhanced_sg;
490  uint32_t ccsar;
491  uint32_t cccr;
492 } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
493 
494 typedef struct {
495  uint8_t op_code;
496  uint8_t command_id;
497  uint8_t channel;
498  uint8_t source_target;
499  uint32_t reserved;
500  uint32_t reserved2;
501  uint32_t reserved3;
502  uint32_t ccsar;
503  uint32_t cccr;
504 } IPS_CS_CMD, *PIPS_CS_CMD;
505 
506 typedef struct {
507  uint8_t op_code;
508  uint8_t command_id;
509  uint8_t log_drv;
510  uint8_t control;
511  uint32_t reserved;
512  uint32_t reserved2;
513  uint32_t reserved3;
514  uint32_t ccsar;
515  uint32_t cccr;
516 } IPS_US_CMD, *PIPS_US_CMD;
517 
518 typedef struct {
519  uint8_t op_code;
520  uint8_t command_id;
521  uint8_t reserved;
522  uint8_t state;
523  uint32_t reserved2;
524  uint32_t reserved3;
525  uint32_t reserved4;
526  uint32_t ccsar;
527  uint32_t cccr;
528 } IPS_FC_CMD, *PIPS_FC_CMD;
529 
530 typedef struct {
531  uint8_t op_code;
532  uint8_t command_id;
533  uint8_t reserved;
534  uint8_t desc;
535  uint32_t reserved2;
536  uint32_t buffer_addr;
537  uint32_t reserved3;
538  uint32_t ccsar;
539  uint32_t cccr;
540 } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
541 
542 typedef struct {
543  uint8_t op_code;
544  uint8_t command_id;
545  uint8_t page;
546  uint8_t write;
547  uint32_t reserved;
548  uint32_t buffer_addr;
549  uint32_t reserved2;
550  uint32_t ccsar;
551  uint32_t cccr;
552 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
553 
554 typedef struct
555 {
556  uint8_t op_code;
557  uint8_t command_id;
558  uint16_t reserved;
559  uint32_t count;
560  uint32_t buffer_addr;
561  uint32_t reserved2;
562 } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
563 
564 typedef struct {
565  uint8_t op_code;
566  uint8_t command_id;
567  uint8_t reset_count;
568  uint8_t reset_type;
569  uint8_t second;
570  uint8_t minute;
571  uint8_t hour;
572  uint8_t day;
573  uint8_t reserved1[4];
574  uint8_t month;
575  uint8_t yearH;
576  uint8_t yearL;
577  uint8_t reserved2;
578 } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
579 
580 typedef struct {
581  uint8_t op_code;
582  uint8_t command_id;
583  uint8_t type;
584  uint8_t direction;
585  uint32_t count;
586  uint32_t buffer_addr;
587  uint8_t total_packets;
588  uint8_t packet_num;
589  uint16_t reserved;
590 } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
591 
592 typedef struct {
593  uint8_t op_code;
594  uint8_t command_id;
595  uint8_t type;
596  uint8_t direction;
597  uint32_t count;
598  uint32_t buffer_addr;
599  uint32_t offset;
600 } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
601 
602 typedef union {
603  IPS_IO_CMD basic_io;
604  IPS_LD_CMD logical_info;
605  IPS_IOCTL_CMD ioctl_info;
606  IPS_DCDB_CMD dcdb;
607  IPS_CS_CMD config_sync;
608  IPS_US_CMD unlock_stripe;
609  IPS_FC_CMD flush_cache;
610  IPS_STATUS_CMD status;
611  IPS_NVRAM_CMD nvram;
612  IPS_FFDC_CMD ffdc;
613  IPS_FLASHFW_CMD flashfw;
614  IPS_FLASHBIOS_CMD flashbios;
615  IPS_VERSION_INFO version_info;
616  IPS_RESET_CMD reset;
617 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
618 
619 typedef struct {
620  uint8_t logical_id;
621  uint8_t reserved;
622  uint8_t raid_level;
623  uint8_t state;
624  uint32_t sector_count;
625 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
626 
627 typedef struct {
628  uint8_t no_of_log_drive;
629  uint8_t reserved[3];
630  IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
631 } IPS_LD_INFO, *PIPS_LD_INFO;
632 
633 typedef struct {
634  uint8_t device_address;
635  uint8_t cmd_attribute;
636  uint16_t transfer_length;
637  uint32_t buffer_pointer;
638  uint8_t cdb_length;
639  uint8_t sense_length;
640  uint8_t sg_count;
641  uint8_t reserved;
642  uint8_t scsi_cdb[12];
643  uint8_t sense_info[64];
644  uint8_t scsi_status;
645  uint8_t reserved2[3];
646 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
647 
648 typedef struct {
649  uint8_t device_address;
650  uint8_t cmd_attribute;
651  uint8_t cdb_length;
652  uint8_t reserved_for_LUN;
653  uint32_t transfer_length;
654  uint32_t buffer_pointer;
655  uint16_t sg_count;
656  uint8_t sense_length;
657  uint8_t scsi_status;
658  uint32_t reserved;
659  uint8_t scsi_cdb[16];
660  uint8_t sense_info[56];
661 } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
662 
663 typedef union {
664  struct {
665  volatile uint8_t reserved;
666  volatile uint8_t command_id;
667  volatile uint8_t basic_status;
668  volatile uint8_t extended_status;
669  } fields;
670 
671  volatile uint32_t value;
672 } IPS_STATUS, *PIPS_STATUS;
673 
674 typedef struct {
675  IPS_STATUS status[IPS_MAX_CMDS + 1];
676  volatile PIPS_STATUS p_status_start;
677  volatile PIPS_STATUS p_status_end;
678  volatile PIPS_STATUS p_status_tail;
679  volatile uint32_t hw_status_start;
680  volatile uint32_t hw_status_tail;
681 } IPS_ADAPTER, *PIPS_ADAPTER;
682 
683 typedef struct {
684  uint8_t ucLogDriveCount;
685  uint8_t ucMiscFlag;
686  uint8_t ucSLTFlag;
687  uint8_t ucBSTFlag;
688  uint8_t ucPwrChgCnt;
689  uint8_t ucWrongAdrCnt;
690  uint8_t ucUnidentCnt;
691  uint8_t ucNVramDevChgCnt;
692  uint8_t CodeBlkVersion[8];
693  uint8_t BootBlkVersion[8];
694  uint32_t ulDriveSize[IPS_MAX_LD];
695  uint8_t ucConcurrentCmdCount;
696  uint8_t ucMaxPhysicalDevices;
697  uint16_t usFlashRepgmCount;
698  uint8_t ucDefunctDiskCount;
699  uint8_t ucRebuildFlag;
700  uint8_t ucOfflineLogDrvCount;
701  uint8_t ucCriticalDrvCount;
702  uint16_t usConfigUpdateCount;
703  uint8_t ucBlkFlag;
704  uint8_t reserved;
705  uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
706 } IPS_ENQ, *PIPS_ENQ;
707 
708 typedef struct {
709  uint8_t ucInitiator;
710  uint8_t ucParameters;
711  uint8_t ucMiscFlag;
712  uint8_t ucState;
713  uint32_t ulBlockCount;
714  uint8_t ucDeviceId[28];
715 } IPS_DEVSTATE, *PIPS_DEVSTATE;
716 
717 typedef struct {
718  uint8_t ucChn;
719  uint8_t ucTgt;
720  uint16_t ucReserved;
721  uint32_t ulStartSect;
722  uint32_t ulNoOfSects;
723 } IPS_CHUNK, *PIPS_CHUNK;
724 
725 typedef struct {
726  uint16_t ucUserField;
727  uint8_t ucState;
728  uint8_t ucRaidCacheParam;
729  uint8_t ucNoOfChunkUnits;
730  uint8_t ucStripeSize;
731  uint8_t ucParams;
732  uint8_t ucReserved;
733  uint32_t ulLogDrvSize;
734  IPS_CHUNK chunk[IPS_MAX_CHUNKS];
735 } IPS_LD, *PIPS_LD;
736 
737 typedef struct {
738  uint8_t board_disc[8];
739  uint8_t processor[8];
740  uint8_t ucNoChanType;
741  uint8_t ucNoHostIntType;
742  uint8_t ucCompression;
743  uint8_t ucNvramType;
744  uint32_t ulNvramSize;
745 } IPS_HARDWARE, *PIPS_HARDWARE;
746 
747 typedef struct {
748  uint8_t ucLogDriveCount;
749  uint8_t ucDateD;
750  uint8_t ucDateM;
751  uint8_t ucDateY;
752  uint8_t init_id[4];
753  uint8_t host_id[12];
754  uint8_t time_sign[8];
755  uint32_t UserOpt;
756  uint16_t user_field;
757  uint8_t ucRebuildRate;
758  uint8_t ucReserve;
759  IPS_HARDWARE hardware_disc;
760  IPS_LD logical_drive[IPS_MAX_LD];
761  IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
762  uint8_t reserved[512];
763 } IPS_CONF, *PIPS_CONF;
764 
765 typedef struct {
766  uint32_t signature;
767  uint8_t reserved1;
768  uint8_t adapter_slot;
769  uint16_t adapter_type;
770  uint8_t ctrl_bios[8];
771  uint8_t versioning; /* 1 = Versioning Supported, else 0 */
772  uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
773  uint8_t reserved2;
774  uint8_t operating_system;
775  uint8_t driver_high[4];
776  uint8_t driver_low[4];
777  uint8_t BiosCompatibilityID[8];
778  uint8_t ReservedForOS2[8];
779  uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
780  uint8_t bios_low[4];
781  uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
782  uint8_t Filler[60];
783 } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
784 
785 /*--------------------------------------------------------------------------*/
786 /* Data returned from a GetVersion Command */
787 /*--------------------------------------------------------------------------*/
788 
789  /* SubSystem Parameter[4] */
790 #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
791 
792 typedef struct
793 {
794  uint32_t revision;
795  uint8_t bootBlkVersion[32];
796  uint8_t bootBlkAttributes[4];
797  uint8_t codeBlkVersion[32];
798  uint8_t biosVersion[32];
799  uint8_t biosAttributes[4];
800  uint8_t compatibilityId[32];
801  uint8_t reserved[4];
802 } IPS_VERSION_DATA;
803 
804 
805 typedef struct _IPS_SUBSYS {
806  uint32_t param[128];
807 } IPS_SUBSYS, *PIPS_SUBSYS;
808 
813 /*
814  * Inquiry Data Format
815  */
816 typedef struct {
817  uint8_t DeviceType;
818  uint8_t DeviceTypeQualifier;
819  uint8_t Version;
820  uint8_t ResponseDataFormat;
821  uint8_t AdditionalLength;
822  uint8_t Reserved;
823  uint8_t Flags[2];
824  uint8_t VendorId[8];
825  uint8_t ProductId[16];
826  uint8_t ProductRevisionLevel[4];
827  uint8_t Reserved2; /* Provides NULL terminator to name */
828 } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
829 
830 /*
831  * Read Capacity Data Format
832  */
833 typedef struct {
834  uint32_t lba;
835  uint32_t len;
836 } IPS_SCSI_CAPACITY;
837 
838 /*
839  * Request Sense Data Format
840  */
841 typedef struct {
842  uint8_t ResponseCode;
843  uint8_t SegmentNumber;
844  uint8_t Flags;
845  uint8_t Information[4];
846  uint8_t AdditionalLength;
847  uint8_t CommandSpecific[4];
848  uint8_t AdditionalSenseCode;
849  uint8_t AdditionalSenseCodeQual;
850  uint8_t FRUCode;
851  uint8_t SenseKeySpecific[3];
852 } IPS_SCSI_REQSEN;
853 
854 /*
855  * Sense Data Format - Page 3
856  */
857 typedef struct {
858  uint8_t PageCode;
859  uint8_t PageLength;
860  uint16_t TracksPerZone;
861  uint16_t AltSectorsPerZone;
862  uint16_t AltTracksPerZone;
863  uint16_t AltTracksPerVolume;
864  uint16_t SectorsPerTrack;
865  uint16_t BytesPerSector;
866  uint16_t Interleave;
867  uint16_t TrackSkew;
868  uint16_t CylinderSkew;
869  uint8_t flags;
870  uint8_t reserved[3];
871 } IPS_SCSI_MODE_PAGE3;
872 
873 /*
874  * Sense Data Format - Page 4
875  */
876 typedef struct {
877  uint8_t PageCode;
878  uint8_t PageLength;
879  uint16_t CylindersHigh;
880  uint8_t CylindersLow;
881  uint8_t Heads;
882  uint16_t WritePrecompHigh;
883  uint8_t WritePrecompLow;
884  uint16_t ReducedWriteCurrentHigh;
885  uint8_t ReducedWriteCurrentLow;
886  uint16_t StepRate;
887  uint16_t LandingZoneHigh;
888  uint8_t LandingZoneLow;
889  uint8_t flags;
890  uint8_t RotationalOffset;
891  uint8_t Reserved;
892  uint16_t MediumRotationRate;
893  uint8_t Reserved2[2];
894 } IPS_SCSI_MODE_PAGE4;
895 
896 /*
897  * Sense Data Format - Page 8
898  */
899 typedef struct {
900  uint8_t PageCode;
901  uint8_t PageLength;
902  uint8_t flags;
903  uint8_t RetentPrio;
904  uint16_t DisPrefetchLen;
905  uint16_t MinPrefetchLen;
906  uint16_t MaxPrefetchLen;
907  uint16_t MaxPrefetchCeiling;
908 } IPS_SCSI_MODE_PAGE8;
909 
910 /*
911  * Sense Data Format - Block Descriptor (DASD)
912  */
913 typedef struct {
914  uint32_t NumberOfBlocks;
915  uint8_t DensityCode;
916  uint16_t BlockLengthHigh;
917  uint8_t BlockLengthLow;
918 } IPS_SCSI_MODE_PAGE_BLKDESC;
919 
920 /*
921  * Sense Data Format - Mode Page Header
922  */
923 typedef struct {
924  uint8_t DataLength;
925  uint8_t MediumType;
926  uint8_t Reserved;
927  uint8_t BlockDescLength;
928 } IPS_SCSI_MODE_PAGE_HEADER;
929 
930 typedef struct {
931  IPS_SCSI_MODE_PAGE_HEADER hdr;
932  IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
933 
934  union {
935  IPS_SCSI_MODE_PAGE3 pg3;
936  IPS_SCSI_MODE_PAGE4 pg4;
937  IPS_SCSI_MODE_PAGE8 pg8;
938  } pdata;
939 } IPS_SCSI_MODE_PAGE_DATA;
940 
941 /*
942  * Scatter Gather list format
943  */
944 typedef struct ips_sglist {
945  uint32_t address;
946  uint32_t length;
947 } IPS_STD_SG_LIST;
948 
949 typedef struct ips_enh_sglist {
950  uint32_t address_lo;
951  uint32_t address_hi;
952  uint32_t length;
953  uint32_t reserved;
954 } IPS_ENH_SG_LIST;
955 
956 typedef union {
957  void *list;
958  IPS_STD_SG_LIST *std_list;
959  IPS_ENH_SG_LIST *enh_list;
960 } IPS_SG_LIST;
961 
962 typedef struct _IPS_INFOSTR {
963  char *buffer;
964  int length;
965  int offset;
966  int pos;
967  int localpos;
968 } IPS_INFOSTR;
969 
970 typedef struct {
971  char *option_name;
972  int *option_flag;
973  int option_value;
974 } IPS_OPTION;
975 
976 /*
977  * Status Info
978  */
979 typedef struct ips_stat {
980  uint32_t residue_len;
981  void *scb_addr;
982  uint8_t padding[12 - sizeof(void *)];
983 } ips_stat_t;
984 
985 /*
986  * SCB Queue Format
987  */
988 typedef struct ips_scb_queue {
989  struct ips_scb *head;
990  struct ips_scb *tail;
991  int count;
992 } ips_scb_queue_t;
993 
994 /*
995  * Wait queue_format
996  */
997 typedef struct ips_wait_queue {
998  struct scsi_cmnd *head;
999  struct scsi_cmnd *tail;
1000  int count;
1001 } ips_wait_queue_t;
1002 
1003 typedef struct ips_copp_wait_item {
1004  struct scsi_cmnd *scsi_cmd;
1005  struct ips_copp_wait_item *next;
1006 } ips_copp_wait_item_t;
1007 
1008 typedef struct ips_copp_queue {
1009  struct ips_copp_wait_item *head;
1010  struct ips_copp_wait_item *tail;
1011  int count;
1012 } ips_copp_queue_t;
1013 
1014 /* forward decl for host structure */
1015 struct ips_ha;
1016 
1017 typedef struct {
1018  int (*reset)(struct ips_ha *);
1019  int (*issue)(struct ips_ha *, struct ips_scb *);
1020  int (*isinit)(struct ips_ha *);
1021  int (*isintr)(struct ips_ha *);
1022  int (*init)(struct ips_ha *);
1023  int (*erasebios)(struct ips_ha *);
1024  int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1025  int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1026  void (*statinit)(struct ips_ha *);
1027  int (*intr)(struct ips_ha *);
1028  void (*enableint)(struct ips_ha *);
1029  uint32_t (*statupd)(struct ips_ha *);
1030 } ips_hw_func_t;
1031 
1032 typedef struct ips_ha {
1033  uint8_t ha_id[IPS_MAX_CHANNELS+1];
1034  uint32_t dcdb_active[IPS_MAX_CHANNELS];
1035  uint32_t io_addr; /* Base I/O address */
1036  uint8_t ntargets; /* Number of targets */
1037  uint8_t nbus; /* Number of buses */
1038  uint8_t nlun; /* Number of Luns */
1039  uint16_t ad_type; /* Adapter type */
1040  uint16_t host_num; /* Adapter number */
1041  uint32_t max_xfer; /* Maximum Xfer size */
1042  uint32_t max_cmds; /* Max concurrent commands */
1043  uint32_t num_ioctl; /* Number of Ioctls */
1044  ips_stat_t sp; /* Status packer pointer */
1045  struct ips_scb *scbs; /* Array of all CCBS */
1046  struct ips_scb *scb_freelist; /* SCB free list */
1047  ips_wait_queue_t scb_waitlist; /* Pending SCB list */
1048  ips_copp_queue_t copp_waitlist; /* Pending PT list */
1049  ips_scb_queue_t scb_activelist; /* Active SCB list */
1050  IPS_IO_CMD *dummy; /* dummy command */
1051  IPS_ADAPTER *adapt; /* Adapter status area */
1052  IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
1053  dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1054  IPS_ENQ *enq; /* Adapter Enquiry data */
1055  IPS_CONF *conf; /* Adapter config data */
1056  IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
1057  IPS_SUBSYS *subsys; /* Subsystem parameters */
1058  char *ioctl_data; /* IOCTL data area */
1059  uint32_t ioctl_datasize; /* IOCTL data size */
1060  uint32_t cmd_in_progress; /* Current command in progress*/
1061  int flags; /* */
1062  uint8_t waitflag; /* are we waiting for cmd */
1063  uint8_t active;
1064  int ioctl_reset; /* IOCTL Requested Reset Flag */
1065  uint16_t reset_count; /* number of resets */
1066  time_t last_ffdc; /* last time we sent ffdc info*/
1067  uint8_t slot_num; /* PCI Slot Number */
1068  int ioctl_len; /* size of ioctl buffer */
1069  dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
1070  uint8_t bios_version[8]; /* BIOS Revision */
1071  uint32_t mem_addr; /* Memory mapped address */
1072  uint32_t io_len; /* Size of IO Address */
1073  uint32_t mem_len; /* Size of memory address */
1074  char __iomem *mem_ptr; /* Memory mapped Ptr */
1075  char __iomem *ioremap_ptr;/* ioremapped memory pointer */
1076  ips_hw_func_t func; /* hw function pointers */
1077  struct pci_dev *pcidev; /* PCI device handle */
1078  char *flash_data; /* Save Area for flash data */
1079  int flash_len; /* length of flash buffer */
1080  u32 flash_datasize; /* Save Area for flash data size */
1081  dma_addr_t flash_busaddr; /* dma address of flash buffer*/
1082  dma_addr_t enq_busaddr; /* dma address of enq struct */
1083  uint8_t requires_esl; /* Requires an EraseStripeLock */
1084 } ips_ha_t;
1085 
1086 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1087 
1088 /*
1089  * SCB Format
1090  */
1091 typedef struct ips_scb {
1092  IPS_HOST_COMMAND cmd;
1093  IPS_DCDB_TABLE dcdb;
1094  uint8_t target_id;
1095  uint8_t bus;
1096  uint8_t lun;
1097  uint8_t cdb[12];
1098  uint32_t scb_busaddr;
1099  uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
1100  uint32_t timeout;
1101  uint8_t basic_status;
1102  uint8_t extended_status;
1103  uint8_t breakup;
1104  uint8_t sg_break;
1105  uint32_t data_len;
1106  uint32_t sg_len;
1107  uint32_t flags;
1108  uint32_t op_code;
1109  IPS_SG_LIST sg_list;
1110  struct scsi_cmnd *scsi_cmd;
1111  struct ips_scb *q_next;
1112  ips_scb_callback callback;
1113  uint32_t sg_busaddr;
1114  int sg_count;
1115  dma_addr_t data_busaddr;
1116 } ips_scb_t;
1117 
1118 typedef struct ips_scb_pt {
1119  IPS_HOST_COMMAND cmd;
1120  IPS_DCDB_TABLE dcdb;
1121  uint8_t target_id;
1122  uint8_t bus;
1123  uint8_t lun;
1124  uint8_t cdb[12];
1125  uint32_t scb_busaddr;
1126  uint32_t data_busaddr;
1127  uint32_t timeout;
1128  uint8_t basic_status;
1129  uint8_t extended_status;
1130  uint16_t breakup;
1131  uint32_t data_len;
1132  uint32_t sg_len;
1133  uint32_t flags;
1134  uint32_t op_code;
1135  IPS_SG_LIST *sg_list;
1136  struct scsi_cmnd *scsi_cmd;
1137  struct ips_scb *q_next;
1138  ips_scb_callback callback;
1139 } ips_scb_pt_t;
1140 
1141 /*
1142  * Passthru Command Format
1143  */
1144 typedef struct {
1145  uint8_t CoppID[4];
1146  uint32_t CoppCmd;
1147  uint32_t PtBuffer;
1148  uint8_t *CmdBuffer;
1149  uint32_t CmdBSize;
1150  ips_scb_pt_t CoppCP;
1151  uint32_t TimeOut;
1152  uint8_t BasicStatus;
1153  uint8_t ExtendedStatus;
1154  uint8_t AdapterType;
1155  uint8_t reserved;
1156 } ips_passthru_t;
1157 
1158 #endif
1159 
1160 /* The Version Information below gets created by SED during the build process. */
1161 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1162 /* Version Info */
1163 /*************************************************************************
1164 *
1165 * VERSION.H -- version numbers and copyright notices in various formats
1166 *
1167 *************************************************************************/
1168 
1169 #define IPS_VER_MAJOR 7
1170 #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1171 #define IPS_VER_MINOR 12
1172 #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1173 #define IPS_VER_BUILD 05
1174 #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1175 #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1176  IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1177 #define IPS_RELEASE_ID 0x00020000
1178 #define IPS_BUILD_IDENT 761
1179 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1180 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1181 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1182 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1183 
1184 /* Version numbers for various adapters */
1185 #define IPS_VER_SERVERAID1 "2.25.01"
1186 #define IPS_VER_SERVERAID2 "2.88.13"
1187 #define IPS_VER_NAVAJO "2.88.13"
1188 #define IPS_VER_SERVERAID3 "6.10.24"
1189 #define IPS_VER_SERVERAID4H "7.12.02"
1190 #define IPS_VER_SERVERAID4MLx "7.12.02"
1191 #define IPS_VER_SARASOTA "7.12.02"
1192 #define IPS_VER_MARCO "7.12.02"
1193 #define IPS_VER_SEBRING "7.12.02"
1194 #define IPS_VER_KEYWEST "7.12.02"
1195 
1196 /* Compatibility IDs for various adapters */
1197 #define IPS_COMPAT_UNKNOWN ""
1198 #define IPS_COMPAT_CURRENT "KW710"
1199 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1200 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1201 #define IPS_COMPAT_NAVAJO "2.88.13"
1202 #define IPS_COMPAT_KIOWA "2.88.13"
1203 #define IPS_COMPAT_SERVERAID3H "SB610"
1204 #define IPS_COMPAT_SERVERAID3L "SB610"
1205 #define IPS_COMPAT_SERVERAID4H "KW710"
1206 #define IPS_COMPAT_SERVERAID4M "KW710"
1207 #define IPS_COMPAT_SERVERAID4L "KW710"
1208 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1209 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1210 #define IPS_COMPAT_SARASOTA "KW710"
1211 #define IPS_COMPAT_MARCO "KW710"
1212 #define IPS_COMPAT_SEBRING "KW710"
1213 #define IPS_COMPAT_TAMPA "KW710"
1214 #define IPS_COMPAT_KEYWEST "KW710"
1215 #define IPS_COMPAT_BIOS "KW710"
1216 
1217 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1218 #define IPS_COMPAT_ID_LENGTH 8
1219 
1220 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1221  char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1222  IPS_COMPAT_UNKNOWN, \
1223  IPS_COMPAT_SERVERAID1, \
1224  IPS_COMPAT_SERVERAID2, \
1225  IPS_COMPAT_NAVAJO, \
1226  IPS_COMPAT_KIOWA, \
1227  IPS_COMPAT_SERVERAID3H, \
1228  IPS_COMPAT_SERVERAID3L, \
1229  IPS_COMPAT_SERVERAID4H, \
1230  IPS_COMPAT_SERVERAID4M, \
1231  IPS_COMPAT_SERVERAID4L, \
1232  IPS_COMPAT_SERVERAID4Mx, \
1233  IPS_COMPAT_SERVERAID4Lx, \
1234  IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1235  IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1236  IPS_COMPAT_MARCO, \
1237  IPS_COMPAT_SEBRING, \
1238  IPS_COMPAT_TAMPA, \
1239  IPS_COMPAT_KEYWEST \
1240  }
1241 
1242 
1243 /*
1244  * Overrides for Emacs so that we almost follow Linus's tabbing style.
1245  * Emacs will notice this stuff at the end of the file and automatically
1246  * adjust the settings for this buffer only. This must remain at the end
1247  * of the file.
1248  * ---------------------------------------------------------------------------
1249  * Local variables:
1250  * c-indent-level: 2
1251  * c-brace-imaginary-offset: 0
1252  * c-brace-offset: -2
1253  * c-argdecl-indent: 2
1254  * c-label-offset: -2
1255  * c-continued-statement-offset: 2
1256  * c-continued-brace-offset: 0
1257  * indent-tabs-mode: nil
1258  * tab-width: 8
1259  * End:
1260  */
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