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isar.c
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1 /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
2  *
3  * isar.c ISAR (Siemens PSB 7110) specific routines
4  *
5  * Author Karsten Keil ([email protected])
6  *
7  * This file is (c) under GNU General Public License
8  *
9  */
10 
11 #include <linux/init.h>
12 #include "hisax.h"
13 #include "isar.h"
14 #include "isdnl1.h"
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 
18 #define DBG_LOADFIRM 0
19 #define DUMP_MBOXFRAME 2
20 
21 #define DLE 0x10
22 #define ETX 0x03
23 
24 #define FAXMODCNT 13
25 static const u_char faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121, 122, 145, 146};
26 static u_int modmask = 0x1fff;
27 static int frm_extra_delay = 2;
28 static int para_TOA = 6;
29 static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL"};
30 
31 static void isar_setup(struct IsdnCardState *cs);
32 static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
33 static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
34 
35 static inline int
36 waitforHIA(struct IsdnCardState *cs, int timeout)
37 {
38 
39  while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
40  udelay(1);
41  timeout--;
42  }
43  if (!timeout)
44  printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
45  return (timeout);
46 }
47 
48 
49 static int
50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
51  u_char *msg)
52 {
53  int i;
54 
55  if (!waitforHIA(cs, 4000))
56  return (0);
57 #if DUMP_MBOXFRAME
58  if (cs->debug & L1_DEB_HSCX)
59  debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
60 #endif
61  cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
62  cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
63  cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
64  if (msg && len) {
65  cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
66  for (i = 1; i < len; i++)
67  cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
68 #if DUMP_MBOXFRAME > 1
69  if (cs->debug & L1_DEB_HSCX_FIFO) {
70  char tmp[256], *t;
71 
72  i = len;
73  while (i > 0) {
74  t = tmp;
75  t += sprintf(t, "sendmbox cnt %d", len);
76  QuickHex(t, &msg[len-i], (i > 64) ? 64 : i);
77  debugl1(cs, tmp);
78  i -= 64;
79  }
80  }
81 #endif
82  }
83  cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
84  waitforHIA(cs, 10000);
85  return (1);
86 }
87 
88 /* Call only with IRQ disabled !!! */
89 static inline void
90 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
91 {
92  int i;
93 
94  cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
95  if (msg && ireg->clsb) {
96  msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
97  for (i = 1; i < ireg->clsb; i++)
98  msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
99 #if DUMP_MBOXFRAME > 1
100  if (cs->debug & L1_DEB_HSCX_FIFO) {
101  char tmp[256], *t;
102 
103  i = ireg->clsb;
104  while (i > 0) {
105  t = tmp;
106  t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
107  QuickHex(t, &msg[ireg->clsb - i], (i > 64) ? 64 : i);
108  debugl1(cs, tmp);
109  i -= 64;
110  }
111  }
112 #endif
113  }
114  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
115 }
116 
117 /* Call only with IRQ disabled !!! */
118 static inline void
119 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
120 {
121  ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
122  ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
123  ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
124 #if DUMP_MBOXFRAME
125  if (cs->debug & L1_DEB_HSCX)
126  debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
127  ireg->clsb);
128 #endif
129 }
130 
131 static int
132 waitrecmsg(struct IsdnCardState *cs, u_char *len,
133  u_char *msg, int maxdelay)
134 {
135  int timeout = 0;
136  struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
137 
138 
139  while ((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
140  (timeout++ < maxdelay))
141  udelay(1);
142  if (timeout > maxdelay) {
143  printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
144  return (0);
145  }
146  get_irq_infos(cs, ir);
147  rcv_mbox(cs, ir, msg);
148  *len = ir->clsb;
149  return (1);
150 }
151 
152 int
153 ISARVersion(struct IsdnCardState *cs, char *s)
154 {
155  int ver;
156  u_char msg[] = ISAR_MSG_HWVER;
157  u_char tmp[64];
158  u_char len;
159  u_long flags;
160  int debug;
161 
162  cs->cardmsg(cs, CARD_RESET, NULL);
163  spin_lock_irqsave(&cs->lock, flags);
164  /* disable ISAR IRQ */
165  cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
166  debug = cs->debug;
167  cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
168  if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
169  spin_unlock_irqrestore(&cs->lock, flags);
170  return (-1);
171  }
172  if (!waitrecmsg(cs, &len, tmp, 100000)) {
173  spin_unlock_irqrestore(&cs->lock, flags);
174  return (-2);
175  }
176  cs->debug = debug;
177  if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
178  if (len == 1) {
179  ver = tmp[0] & 0xf;
180  printk(KERN_INFO "%s ISAR version %d\n", s, ver);
181  } else
182  ver = -3;
183  } else
184  ver = -4;
185  spin_unlock_irqrestore(&cs->lock, flags);
186  return (ver);
187 }
188 
189 static int
190 isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
191 {
192  int cfu_ret, ret, size, cnt, debug;
193  u_char len, nom, noc;
194  u_short sadr, left, *sp;
195  u_char __user *p = buf;
196  u_char *msg, *tmpmsg, *mp, tmp[64];
197  u_long flags;
198  struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
199 
200  struct {u_short sadr;
201  u_short len;
202  u_short d_key;
203  } blk_head;
204 
205 #define BLK_HEAD_SIZE 6
206  if (1 != (ret = ISARVersion(cs, "Testing"))) {
207  printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
208  return (1);
209  }
210  debug = cs->debug;
211 #if DBG_LOADFIRM < 2
212  cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
213 #endif
214 
215  cfu_ret = copy_from_user(&size, p, sizeof(int));
216  if (cfu_ret) {
217  printk(KERN_ERR "isar_load_firmware copy_from_user ret %d\n", cfu_ret);
218  return -EFAULT;
219  }
220  p += sizeof(int);
221  printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
222  cnt = 0;
223  /* disable ISAR IRQ */
224  cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
225  if (!(msg = kmalloc(256, GFP_KERNEL))) {
226  printk(KERN_ERR"isar_load_firmware no buffer\n");
227  return (1);
228  }
229  if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
230  printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
231  kfree(msg);
232  return (1);
233  }
234  spin_lock_irqsave(&cs->lock, flags);
235  /* disable ISAR IRQ */
236  cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
237  spin_unlock_irqrestore(&cs->lock, flags);
238  while (cnt < size) {
239  if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
240  printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
241  goto reterror;
242  }
243 #ifdef __BIG_ENDIAN
244  sadr = (blk_head.sadr & 0xff) * 256 + blk_head.sadr / 256;
245  blk_head.sadr = sadr;
246  sadr = (blk_head.len & 0xff) * 256 + blk_head.len / 256;
247  blk_head.len = sadr;
248  sadr = (blk_head.d_key & 0xff) * 256 + blk_head.d_key / 256;
249  blk_head.d_key = sadr;
250 #endif /* __BIG_ENDIAN */
251  cnt += BLK_HEAD_SIZE;
252  p += BLK_HEAD_SIZE;
253  printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
254  blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
255  sadr = blk_head.sadr;
256  left = blk_head.len;
257  spin_lock_irqsave(&cs->lock, flags);
258  if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
259  printk(KERN_ERR"isar sendmsg dkey failed\n");
260  ret = 1; goto reterr_unlock;
261  }
262  if (!waitrecmsg(cs, &len, tmp, 100000)) {
263  printk(KERN_ERR"isar waitrecmsg dkey failed\n");
264  ret = 1; goto reterr_unlock;
265  }
266  if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
267  printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
268  ireg->iis, ireg->cmsb, len);
269  ret = 1; goto reterr_unlock;
270  }
271  spin_unlock_irqrestore(&cs->lock, flags);
272  while (left > 0) {
273  if (left > 126)
274  noc = 126;
275  else
276  noc = left;
277  nom = 2 * noc;
278  mp = msg;
279  *mp++ = sadr / 256;
280  *mp++ = sadr % 256;
281  left -= noc;
282  *mp++ = noc;
283  if ((ret = copy_from_user(tmpmsg, p, nom))) {
284  printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
285  goto reterror;
286  }
287  p += nom;
288  cnt += nom;
289  nom += 3;
290  sp = (u_short *)tmpmsg;
291 #if DBG_LOADFIRM
292  printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
293  noc, sadr, left);
294 #endif
295  sadr += noc;
296  while (noc) {
297 #ifdef __BIG_ENDIAN
298  *mp++ = *sp % 256;
299  *mp++ = *sp / 256;
300 #else
301  *mp++ = *sp / 256;
302  *mp++ = *sp % 256;
303 #endif /* __BIG_ENDIAN */
304  sp++;
305  noc--;
306  }
307  spin_lock_irqsave(&cs->lock, flags);
308  if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
309  printk(KERN_ERR"isar sendmsg prog failed\n");
310  ret = 1; goto reterr_unlock;
311  }
312  if (!waitrecmsg(cs, &len, tmp, 100000)) {
313  printk(KERN_ERR"isar waitrecmsg prog failed\n");
314  ret = 1; goto reterr_unlock;
315  }
316  if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
317  printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
318  ireg->iis, ireg->cmsb, len);
319  ret = 1; goto reterr_unlock;
320  }
321  spin_unlock_irqrestore(&cs->lock, flags);
322  }
323  printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
324  blk_head.len);
325  }
326  /* 10ms delay */
327  cnt = 10;
328  while (cnt--)
329  udelay(1000);
330  msg[0] = 0xff;
331  msg[1] = 0xfe;
332  ireg->bstat = 0;
333  spin_lock_irqsave(&cs->lock, flags);
334  if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
335  printk(KERN_ERR"isar sendmsg start dsp failed\n");
336  ret = 1; goto reterr_unlock;
337  }
338  if (!waitrecmsg(cs, &len, tmp, 100000)) {
339  printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
340  ret = 1; goto reterr_unlock;
341  }
342  if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
343  printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
344  ireg->iis, ireg->cmsb, len);
345  ret = 1; goto reterr_unlock;
346  } else
347  printk(KERN_DEBUG"isar start dsp success\n");
348  /* NORMAL mode entered */
349  /* Enable IRQs of ISAR */
350  cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
351  spin_unlock_irqrestore(&cs->lock, flags);
352  cnt = 1000; /* max 1s */
353  while ((!ireg->bstat) && cnt) {
354  udelay(1000);
355  cnt--;
356  }
357  if (!cnt) {
358  printk(KERN_ERR"isar no general status event received\n");
359  ret = 1; goto reterror;
360  } else {
361  printk(KERN_DEBUG"isar general status event %x\n",
362  ireg->bstat);
363  }
364  /* 10ms delay */
365  cnt = 10;
366  while (cnt--)
367  udelay(1000);
368  spin_lock_irqsave(&cs->lock, flags);
369  ireg->iis = 0;
370  if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
371  printk(KERN_ERR"isar sendmsg self tst failed\n");
372  ret = 1; goto reterr_unlock;
373  }
374  cnt = 10000; /* max 100 ms */
375  spin_unlock_irqrestore(&cs->lock, flags);
376  while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
377  udelay(10);
378  cnt--;
379  }
380  udelay(1000);
381  if (!cnt) {
382  printk(KERN_ERR"isar no self tst response\n");
383  ret = 1; goto reterror;
384  }
385  if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
386  && (ireg->par[0] == 0)) {
387  printk(KERN_DEBUG"isar selftest OK\n");
388  } else {
389  printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
390  ireg->cmsb, ireg->clsb, ireg->par[0]);
391  ret = 1; goto reterror;
392  }
393  spin_lock_irqsave(&cs->lock, flags);
394  ireg->iis = 0;
395  if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
396  printk(KERN_ERR"isar RQST SVN failed\n");
397  ret = 1; goto reterr_unlock;
398  }
399  spin_unlock_irqrestore(&cs->lock, flags);
400  cnt = 30000; /* max 300 ms */
401  while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
402  udelay(10);
403  cnt--;
404  }
405  udelay(1000);
406  if (!cnt) {
407  printk(KERN_ERR"isar no SVN response\n");
408  ret = 1; goto reterror;
409  } else {
410  if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
411  printk(KERN_DEBUG"isar software version %#x\n",
412  ireg->par[0]);
413  else {
414  printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
415  ireg->cmsb, ireg->clsb, cnt);
416  ret = 1; goto reterror;
417  }
418  }
419  spin_lock_irqsave(&cs->lock, flags);
420  cs->debug = debug;
421  isar_setup(cs);
422 
423  ret = 0;
424 reterr_unlock:
425  spin_unlock_irqrestore(&cs->lock, flags);
426 reterror:
427  cs->debug = debug;
428  if (ret)
429  /* disable ISAR IRQ */
430  cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
431  kfree(msg);
432  kfree(tmpmsg);
433  return (ret);
434 }
435 
436 #define B_LL_NOCARRIER 8
437 #define B_LL_CONNECT 9
438 #define B_LL_OK 10
439 
440 static void
441 isar_bh(struct work_struct *work)
442 {
443  struct BCState *bcs = container_of(work, struct BCState, tqueue);
444 
445  BChannel_bh(work);
446  if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
447  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
448  if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
449  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
450  if (test_and_clear_bit(B_LL_OK, &bcs->event))
451  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
452 }
453 
454 static void
455 send_DLE_ETX(struct BCState *bcs)
456 {
457  u_char dleetx[2] = {DLE, ETX};
458  struct sk_buff *skb;
459 
460  if ((skb = dev_alloc_skb(2))) {
461  memcpy(skb_put(skb, 2), dleetx, 2);
462  skb_queue_tail(&bcs->rqueue, skb);
463  schedule_event(bcs, B_RCVBUFREADY);
464  } else {
465  printk(KERN_WARNING "HiSax: skb out of memory\n");
466  }
467 }
468 
469 static inline int
470 dle_count(unsigned char *buf, int len)
471 {
472  int count = 0;
473 
474  while (len--)
475  if (*buf++ == DLE)
476  count++;
477  return count;
478 }
479 
480 static inline void
481 insert_dle(unsigned char *dest, unsigned char *src, int count) {
482  /* <DLE> in input stream have to be flagged as <DLE><DLE> */
483  while (count--) {
484  *dest++ = *src;
485  if (*src++ == DLE)
486  *dest++ = DLE;
487  }
488 }
489 
490 static void
491 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
492 {
493  u_char *ptr;
494  struct sk_buff *skb;
495  struct isar_reg *ireg = bcs->hw.isar.reg;
496 
497  if (!ireg->clsb) {
498  debugl1(cs, "isar zero len frame");
499  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
500  return;
501  }
502  switch (bcs->mode) {
503  case L1_MODE_NULL:
504  debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
505  ireg->iis, ireg->cmsb, ireg->clsb);
506  printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
507  ireg->iis, ireg->cmsb, ireg->clsb);
508  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
509  break;
510  case L1_MODE_TRANS:
511  case L1_MODE_V32:
512  if ((skb = dev_alloc_skb(ireg->clsb))) {
513  rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
514  skb_queue_tail(&bcs->rqueue, skb);
515  schedule_event(bcs, B_RCVBUFREADY);
516  } else {
517  printk(KERN_WARNING "HiSax: skb out of memory\n");
518  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
519  }
520  break;
521  case L1_MODE_HDLC:
522  if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
523  if (cs->debug & L1_DEB_WARN)
524  debugl1(cs, "isar_rcv_frame: incoming packet too large");
525  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
526  bcs->hw.isar.rcvidx = 0;
527  } else if (ireg->cmsb & HDLC_ERROR) {
528  if (cs->debug & L1_DEB_WARN)
529  debugl1(cs, "isar frame error %x len %d",
530  ireg->cmsb, ireg->clsb);
531 #ifdef ERROR_STATISTIC
532  if (ireg->cmsb & HDLC_ERR_RER)
533  bcs->err_inv++;
534  if (ireg->cmsb & HDLC_ERR_CER)
535  bcs->err_crc++;
536 #endif
537  bcs->hw.isar.rcvidx = 0;
538  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
539  } else {
540  if (ireg->cmsb & HDLC_FSD)
541  bcs->hw.isar.rcvidx = 0;
542  ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
543  bcs->hw.isar.rcvidx += ireg->clsb;
544  rcv_mbox(cs, ireg, ptr);
545  if (ireg->cmsb & HDLC_FED) {
546  if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
547  if (cs->debug & L1_DEB_WARN)
548  debugl1(cs, "isar frame to short %d",
549  bcs->hw.isar.rcvidx);
550  } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx - 2))) {
551  printk(KERN_WARNING "ISAR: receive out of memory\n");
552  } else {
553  memcpy(skb_put(skb, bcs->hw.isar.rcvidx - 2),
554  bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx - 2);
555  skb_queue_tail(&bcs->rqueue, skb);
556  schedule_event(bcs, B_RCVBUFREADY);
557  }
558  bcs->hw.isar.rcvidx = 0;
559  }
560  }
561  break;
562  case L1_MODE_FAX:
563  if (bcs->hw.isar.state != STFAX_ACTIV) {
564  if (cs->debug & L1_DEB_WARN)
565  debugl1(cs, "isar_rcv_frame: not ACTIV");
566  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
567  bcs->hw.isar.rcvidx = 0;
568  break;
569  }
570  if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
571  rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
572  bcs->hw.isar.rcvidx = ireg->clsb +
573  dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
574  if (cs->debug & L1_DEB_HSCX)
575  debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
576  ireg->clsb, bcs->hw.isar.rcvidx);
577  if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
578  insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
579  bcs->hw.isar.rcvbuf, ireg->clsb);
580  skb_queue_tail(&bcs->rqueue, skb);
581  schedule_event(bcs, B_RCVBUFREADY);
582  if (ireg->cmsb & SART_NMD) { /* ABORT */
583  if (cs->debug & L1_DEB_WARN)
584  debugl1(cs, "isar_rcv_frame: no more data");
585  bcs->hw.isar.rcvidx = 0;
586  send_DLE_ETX(bcs);
587  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
588  ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
589  0, NULL);
590  bcs->hw.isar.state = STFAX_ESCAPE;
591  schedule_event(bcs, B_LL_NOCARRIER);
592  }
593  } else {
594  printk(KERN_WARNING "HiSax: skb out of memory\n");
595  }
596  break;
597  }
598  if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
599  if (cs->debug & L1_DEB_WARN)
600  debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
601  bcs->hw.isar.cmd);
602  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
603  bcs->hw.isar.rcvidx = 0;
604  break;
605  }
606  /* PCTRL_CMD_FRH */
607  if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
608  if (cs->debug & L1_DEB_WARN)
609  debugl1(cs, "isar_rcv_frame: incoming packet too large");
610  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
611  bcs->hw.isar.rcvidx = 0;
612  } else if (ireg->cmsb & HDLC_ERROR) {
613  if (cs->debug & L1_DEB_WARN)
614  debugl1(cs, "isar frame error %x len %d",
615  ireg->cmsb, ireg->clsb);
616  bcs->hw.isar.rcvidx = 0;
617  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
618  } else {
619  if (ireg->cmsb & HDLC_FSD) {
620  bcs->hw.isar.rcvidx = 0;
621  }
622  ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
623  bcs->hw.isar.rcvidx += ireg->clsb;
624  rcv_mbox(cs, ireg, ptr);
625  if (ireg->cmsb & HDLC_FED) {
626  int len = bcs->hw.isar.rcvidx +
627  dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
628  if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
629  if (cs->debug & L1_DEB_WARN)
630  debugl1(cs, "isar frame to short %d",
631  bcs->hw.isar.rcvidx);
632  printk(KERN_WARNING "ISAR: frame to short %d\n",
633  bcs->hw.isar.rcvidx);
634  } else if (!(skb = dev_alloc_skb(len))) {
635  printk(KERN_WARNING "ISAR: receive out of memory\n");
636  } else {
637  insert_dle((u_char *)skb_put(skb, len),
638  bcs->hw.isar.rcvbuf,
639  bcs->hw.isar.rcvidx);
640  skb_queue_tail(&bcs->rqueue, skb);
641  schedule_event(bcs, B_RCVBUFREADY);
642  send_DLE_ETX(bcs);
643  schedule_event(bcs, B_LL_OK);
644  test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
645  }
646  bcs->hw.isar.rcvidx = 0;
647  }
648  }
649  if (ireg->cmsb & SART_NMD) { /* ABORT */
650  if (cs->debug & L1_DEB_WARN)
651  debugl1(cs, "isar_rcv_frame: no more data");
652  bcs->hw.isar.rcvidx = 0;
653  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
654  ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
655  bcs->hw.isar.state = STFAX_ESCAPE;
656  if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
657  send_DLE_ETX(bcs);
658  schedule_event(bcs, B_LL_NOCARRIER);
659  }
660  }
661  break;
662  default:
663  printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
664  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
665  break;
666  }
667 }
668 
669 void
670 isar_fill_fifo(struct BCState *bcs)
671 {
672  struct IsdnCardState *cs = bcs->cs;
673  int count;
674  u_char msb;
675  u_char *ptr;
676 
677  if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
678  debugl1(cs, "isar_fill_fifo");
679  if (!bcs->tx_skb)
680  return;
681  if (bcs->tx_skb->len <= 0)
682  return;
683  if (!(bcs->hw.isar.reg->bstat &
684  (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
685  return;
686  if (bcs->tx_skb->len > bcs->hw.isar.mml) {
687  msb = 0;
688  count = bcs->hw.isar.mml;
689  } else {
690  count = bcs->tx_skb->len;
691  msb = HDLC_FED;
692  }
693  ptr = bcs->tx_skb->data;
694  if (!bcs->hw.isar.txcnt) {
695  msb |= HDLC_FST;
696  if ((bcs->mode == L1_MODE_FAX) &&
697  (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
698  if (bcs->tx_skb->len > 1) {
699  if ((ptr[0] == 0xff) && (ptr[1] == 0x13))
700  /* last frame */
701  test_and_set_bit(BC_FLG_LASTDATA,
702  &bcs->Flag);
703  }
704  }
705  }
706  skb_pull(bcs->tx_skb, count);
707  bcs->tx_cnt -= count;
708  bcs->hw.isar.txcnt += count;
709  switch (bcs->mode) {
710  case L1_MODE_NULL:
711  printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
712  break;
713  case L1_MODE_TRANS:
714  case L1_MODE_V32:
715  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
716  0, count, ptr);
717  break;
718  case L1_MODE_HDLC:
719  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
720  msb, count, ptr);
721  break;
722  case L1_MODE_FAX:
723  if (bcs->hw.isar.state != STFAX_ACTIV) {
724  if (cs->debug & L1_DEB_WARN)
725  debugl1(cs, "isar_fill_fifo: not ACTIV");
726  } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
727  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
728  msb, count, ptr);
729  } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
730  sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
731  0, count, ptr);
732  } else {
733  if (cs->debug & L1_DEB_WARN)
734  debugl1(cs, "isar_fill_fifo: not FTH/FTM");
735  }
736  break;
737  default:
738  if (cs->debug)
739  debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
740  printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
741  break;
742  }
743 }
744 
745 static inline
746 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
747 {
748  if ((!dpath) || (dpath == 3))
749  return (NULL);
750  if (cs->bcs[0].hw.isar.dpath == dpath)
751  return (&cs->bcs[0]);
752  if (cs->bcs[1].hw.isar.dpath == dpath)
753  return (&cs->bcs[1]);
754  return (NULL);
755 }
756 
757 static void
758 send_frames(struct BCState *bcs)
759 {
760  if (bcs->tx_skb) {
761  if (bcs->tx_skb->len) {
762  isar_fill_fifo(bcs);
763  return;
764  } else {
765  if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
766  (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
767  u_long flags;
768  spin_lock_irqsave(&bcs->aclock, flags);
769  bcs->ackcnt += bcs->hw.isar.txcnt;
770  spin_unlock_irqrestore(&bcs->aclock, flags);
771  schedule_event(bcs, B_ACKPENDING);
772  }
773  if (bcs->mode == L1_MODE_FAX) {
774  if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
775  if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
776  test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
777  }
778  } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
779  if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
780  test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
781  test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
782  }
783  }
784  }
785  dev_kfree_skb_any(bcs->tx_skb);
786  bcs->hw.isar.txcnt = 0;
787  bcs->tx_skb = NULL;
788  }
789  }
790  if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
791  bcs->hw.isar.txcnt = 0;
792  test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
793  isar_fill_fifo(bcs);
794  } else {
795  if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
796  if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
797  if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
798  u_char dummy = 0;
799  sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
800  ISAR_HIS_SDATA, 0x01, 1, &dummy);
801  }
802  test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
803  } else {
804  schedule_event(bcs, B_LL_CONNECT);
805  }
806  }
807  test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
808  schedule_event(bcs, B_XMTBUFREADY);
809  }
810 }
811 
812 static inline void
813 check_send(struct IsdnCardState *cs, u_char rdm)
814 {
815  struct BCState *bcs;
816 
817  if (rdm & BSTAT_RDM1) {
818  if ((bcs = sel_bcs_isar(cs, 1))) {
819  if (bcs->mode) {
820  send_frames(bcs);
821  }
822  }
823  }
824  if (rdm & BSTAT_RDM2) {
825  if ((bcs = sel_bcs_isar(cs, 2))) {
826  if (bcs->mode) {
827  send_frames(bcs);
828  }
829  }
830  }
831 
832 }
833 
834 static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200",
835  "NODEF4", "300", "600", "1200", "2400",
836  "4800", "7200", "9600nt", "9600t", "12000",
837  "14400", "WRONG"};
838 static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
839  "Bell103", "V23", "Bell202", "V17", "V29",
840  "V27ter"};
841 
842 static void
843 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
844  struct IsdnCardState *cs = bcs->cs;
845  u_char ril = ireg->par[0];
846  u_char rim;
847 
848  if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
849  return;
850  if (ril > 14) {
851  if (cs->debug & L1_DEB_WARN)
852  debugl1(cs, "wrong pstrsp ril=%d", ril);
853  ril = 15;
854  }
855  switch (ireg->par[1]) {
856  case 0:
857  rim = 0;
858  break;
859  case 0x20:
860  rim = 2;
861  break;
862  case 0x40:
863  rim = 3;
864  break;
865  case 0x41:
866  rim = 4;
867  break;
868  case 0x51:
869  rim = 5;
870  break;
871  case 0x61:
872  rim = 6;
873  break;
874  case 0x71:
875  rim = 7;
876  break;
877  case 0x82:
878  rim = 8;
879  break;
880  case 0x92:
881  rim = 9;
882  break;
883  case 0xa2:
884  rim = 10;
885  break;
886  default:
887  rim = 1;
888  break;
889  }
890  sprintf(bcs->hw.isar.conmsg, "%s %s", dmril[ril], dmrim[rim]);
891  bcs->conmsg = bcs->hw.isar.conmsg;
892  if (cs->debug & L1_DEB_HSCX)
893  debugl1(cs, "pump strsp %s", bcs->conmsg);
894 }
895 
896 static void
897 isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
898  struct IsdnCardState *cs = bcs->cs;
899  u_char dps = SET_DPS(bcs->hw.isar.dpath);
900 
901  switch (devt) {
902  case PSEV_10MS_TIMER:
903  if (cs->debug & L1_DEB_HSCX)
904  debugl1(cs, "pump stev TIMER");
905  break;
906  case PSEV_CON_ON:
907  if (cs->debug & L1_DEB_HSCX)
908  debugl1(cs, "pump stev CONNECT");
909  l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
910  break;
911  case PSEV_CON_OFF:
912  if (cs->debug & L1_DEB_HSCX)
913  debugl1(cs, "pump stev NO CONNECT");
914  sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
915  l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
916  break;
917  case PSEV_V24_OFF:
918  if (cs->debug & L1_DEB_HSCX)
919  debugl1(cs, "pump stev V24 OFF");
920  break;
921  case PSEV_CTS_ON:
922  if (cs->debug & L1_DEB_HSCX)
923  debugl1(cs, "pump stev CTS ON");
924  break;
925  case PSEV_CTS_OFF:
926  if (cs->debug & L1_DEB_HSCX)
927  debugl1(cs, "pump stev CTS OFF");
928  break;
929  case PSEV_DCD_ON:
930  if (cs->debug & L1_DEB_HSCX)
931  debugl1(cs, "pump stev CARRIER ON");
932  test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
933  sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
934  break;
935  case PSEV_DCD_OFF:
936  if (cs->debug & L1_DEB_HSCX)
937  debugl1(cs, "pump stev CARRIER OFF");
938  break;
939  case PSEV_DSR_ON:
940  if (cs->debug & L1_DEB_HSCX)
941  debugl1(cs, "pump stev DSR ON");
942  break;
943  case PSEV_DSR_OFF:
944  if (cs->debug & L1_DEB_HSCX)
945  debugl1(cs, "pump stev DSR_OFF");
946  break;
947  case PSEV_REM_RET:
948  if (cs->debug & L1_DEB_HSCX)
949  debugl1(cs, "pump stev REMOTE RETRAIN");
950  break;
951  case PSEV_REM_REN:
952  if (cs->debug & L1_DEB_HSCX)
953  debugl1(cs, "pump stev REMOTE RENEGOTIATE");
954  break;
955  case PSEV_GSTN_CLR:
956  if (cs->debug & L1_DEB_HSCX)
957  debugl1(cs, "pump stev GSTN CLEAR");
958  break;
959  default:
960  if (cs->debug & L1_DEB_HSCX)
961  debugl1(cs, "unknown pump stev %x", devt);
962  break;
963  }
964 }
965 
966 static void
967 ll_deliver_faxstat(struct BCState *bcs, u_char status)
968 {
969  isdn_ctrl ic;
970  struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
971 
972  if (bcs->cs->debug & L1_DEB_HSCX)
973  debugl1(bcs->cs, "HL->LL FAXIND %x", status);
974  ic.driver = bcs->cs->myid;
975  ic.command = ISDN_STAT_FAXIND;
976  ic.arg = chanp->chan;
977  ic.parm.aux.cmd = status;
978  bcs->cs->iif.statcallb(&ic);
979 }
980 
981 static void
982 isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
983  struct IsdnCardState *cs = bcs->cs;
984  u_char dps = SET_DPS(bcs->hw.isar.dpath);
985  u_char p1;
986 
987  switch (devt) {
988  case PSEV_10MS_TIMER:
989  if (cs->debug & L1_DEB_HSCX)
990  debugl1(cs, "pump stev TIMER");
991  break;
992  case PSEV_RSP_READY:
993  if (cs->debug & L1_DEB_HSCX)
994  debugl1(cs, "pump stev RSP_READY");
995  bcs->hw.isar.state = STFAX_READY;
996  l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
997  if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
998  isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
999  } else {
1000  isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
1001  }
1002  break;
1003  case PSEV_LINE_TX_H:
1004  if (bcs->hw.isar.state == STFAX_LINE) {
1005  if (cs->debug & L1_DEB_HSCX)
1006  debugl1(cs, "pump stev LINE_TX_H");
1007  bcs->hw.isar.state = STFAX_CONT;
1008  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1009  } else {
1010  if (cs->debug & L1_DEB_WARN)
1011  debugl1(cs, "pump stev LINE_TX_H wrong st %x",
1012  bcs->hw.isar.state);
1013  }
1014  break;
1015  case PSEV_LINE_RX_H:
1016  if (bcs->hw.isar.state == STFAX_LINE) {
1017  if (cs->debug & L1_DEB_HSCX)
1018  debugl1(cs, "pump stev LINE_RX_H");
1019  bcs->hw.isar.state = STFAX_CONT;
1020  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1021  } else {
1022  if (cs->debug & L1_DEB_WARN)
1023  debugl1(cs, "pump stev LINE_RX_H wrong st %x",
1024  bcs->hw.isar.state);
1025  }
1026  break;
1027  case PSEV_LINE_TX_B:
1028  if (bcs->hw.isar.state == STFAX_LINE) {
1029  if (cs->debug & L1_DEB_HSCX)
1030  debugl1(cs, "pump stev LINE_TX_B");
1031  bcs->hw.isar.state = STFAX_CONT;
1032  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1033  } else {
1034  if (cs->debug & L1_DEB_WARN)
1035  debugl1(cs, "pump stev LINE_TX_B wrong st %x",
1036  bcs->hw.isar.state);
1037  }
1038  break;
1039  case PSEV_LINE_RX_B:
1040  if (bcs->hw.isar.state == STFAX_LINE) {
1041  if (cs->debug & L1_DEB_HSCX)
1042  debugl1(cs, "pump stev LINE_RX_B");
1043  bcs->hw.isar.state = STFAX_CONT;
1044  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1045  } else {
1046  if (cs->debug & L1_DEB_WARN)
1047  debugl1(cs, "pump stev LINE_RX_B wrong st %x",
1048  bcs->hw.isar.state);
1049  }
1050  break;
1051  case PSEV_RSP_CONN:
1052  if (bcs->hw.isar.state == STFAX_CONT) {
1053  if (cs->debug & L1_DEB_HSCX)
1054  debugl1(cs, "pump stev RSP_CONN");
1055  bcs->hw.isar.state = STFAX_ACTIV;
1056  test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
1057  sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1058  if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
1059  /* 1s Flags before data */
1060  if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
1061  del_timer(&bcs->hw.isar.ftimer);
1062  /* 1000 ms */
1063  bcs->hw.isar.ftimer.expires =
1064  jiffies + ((1000 * HZ) / 1000);
1065  test_and_set_bit(BC_FLG_LL_CONN,
1066  &bcs->Flag);
1067  add_timer(&bcs->hw.isar.ftimer);
1068  } else {
1069  schedule_event(bcs, B_LL_CONNECT);
1070  }
1071  } else {
1072  if (cs->debug & L1_DEB_WARN)
1073  debugl1(cs, "pump stev RSP_CONN wrong st %x",
1074  bcs->hw.isar.state);
1075  }
1076  break;
1077  case PSEV_FLAGS_DET:
1078  if (cs->debug & L1_DEB_HSCX)
1079  debugl1(cs, "pump stev FLAGS_DET");
1080  break;
1081  case PSEV_RSP_DISC:
1082  if (cs->debug & L1_DEB_HSCX)
1083  debugl1(cs, "pump stev RSP_DISC");
1084  if (bcs->hw.isar.state == STFAX_ESCAPE) {
1085  p1 = 5;
1086  switch (bcs->hw.isar.newcmd) {
1087  case 0:
1088  bcs->hw.isar.state = STFAX_READY;
1089  break;
1090  case PCTRL_CMD_FTM:
1091  p1 = 2;
1092  case PCTRL_CMD_FTH:
1093  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1094  PCTRL_CMD_SILON, 1, &p1);
1095  bcs->hw.isar.state = STFAX_SILDET;
1096  break;
1097  case PCTRL_CMD_FRM:
1098  if (frm_extra_delay)
1099  mdelay(frm_extra_delay);
1100  case PCTRL_CMD_FRH:
1101  p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1102  bcs->hw.isar.newmod = 0;
1103  bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1104  bcs->hw.isar.newcmd = 0;
1105  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1106  bcs->hw.isar.cmd, 1, &p1);
1107  bcs->hw.isar.state = STFAX_LINE;
1108  bcs->hw.isar.try_mod = 3;
1109  break;
1110  default:
1111  if (cs->debug & L1_DEB_HSCX)
1112  debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
1113  break;
1114  }
1115  } else if (bcs->hw.isar.state == STFAX_ACTIV) {
1116  if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
1117  schedule_event(bcs, B_LL_OK);
1118  } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
1119  send_DLE_ETX(bcs);
1120  schedule_event(bcs, B_LL_NOCARRIER);
1121  } else {
1122  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1123  }
1124  bcs->hw.isar.state = STFAX_READY;
1125  } else {
1126  bcs->hw.isar.state = STFAX_READY;
1127  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1128  }
1129  break;
1130  case PSEV_RSP_SILDET:
1131  if (cs->debug & L1_DEB_HSCX)
1132  debugl1(cs, "pump stev RSP_SILDET");
1133  if (bcs->hw.isar.state == STFAX_SILDET) {
1134  p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1135  bcs->hw.isar.newmod = 0;
1136  bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1137  bcs->hw.isar.newcmd = 0;
1138  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1139  bcs->hw.isar.cmd, 1, &p1);
1140  bcs->hw.isar.state = STFAX_LINE;
1141  bcs->hw.isar.try_mod = 3;
1142  }
1143  break;
1144  case PSEV_RSP_SILOFF:
1145  if (cs->debug & L1_DEB_HSCX)
1146  debugl1(cs, "pump stev RSP_SILOFF");
1147  break;
1148  case PSEV_RSP_FCERR:
1149  if (bcs->hw.isar.state == STFAX_LINE) {
1150  if (cs->debug & L1_DEB_HSCX)
1151  debugl1(cs, "pump stev RSP_FCERR try %d",
1152  bcs->hw.isar.try_mod);
1153  if (bcs->hw.isar.try_mod--) {
1154  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1155  bcs->hw.isar.cmd, 1,
1156  &bcs->hw.isar.mod);
1157  break;
1158  }
1159  }
1160  if (cs->debug & L1_DEB_HSCX)
1161  debugl1(cs, "pump stev RSP_FCERR");
1162  bcs->hw.isar.state = STFAX_ESCAPE;
1163  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
1164  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1165  break;
1166  default:
1167  break;
1168  }
1169 }
1170 
1171 static char debbuf[128];
1172 
1173 void
1174 isar_int_main(struct IsdnCardState *cs)
1175 {
1176  struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1177  struct BCState *bcs;
1178 
1179  get_irq_infos(cs, ireg);
1180  switch (ireg->iis & ISAR_IIS_MSCMSD) {
1181  case ISAR_IIS_RDATA:
1182  if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1183  isar_rcv_frame(cs, bcs);
1184  } else {
1185  debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
1186  ireg->iis, ireg->cmsb, ireg->clsb);
1187  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1188  }
1189  break;
1190  case ISAR_IIS_GSTEV:
1191  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1192  ireg->bstat |= ireg->cmsb;
1193  check_send(cs, ireg->cmsb);
1194  break;
1195  case ISAR_IIS_BSTEV:
1196 #ifdef ERROR_STATISTIC
1197  if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1198  if (ireg->cmsb == BSTEV_TBO)
1199  bcs->err_tx++;
1200  if (ireg->cmsb == BSTEV_RBO)
1201  bcs->err_rdo++;
1202  }
1203 #endif
1204  if (cs->debug & L1_DEB_WARN)
1205  debugl1(cs, "Buffer STEV dpath%d msb(%x)",
1206  ireg->iis >> 6, ireg->cmsb);
1207  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1208  break;
1209  case ISAR_IIS_PSTEV:
1210  if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1211  rcv_mbox(cs, ireg, (u_char *)ireg->par);
1212  if (bcs->mode == L1_MODE_V32) {
1213  isar_pump_statev_modem(bcs, ireg->cmsb);
1214  } else if (bcs->mode == L1_MODE_FAX) {
1215  isar_pump_statev_fax(bcs, ireg->cmsb);
1216  } else if (ireg->cmsb == PSEV_10MS_TIMER) {
1217  if (cs->debug & L1_DEB_HSCX)
1218  debugl1(cs, "pump stev TIMER");
1219  } else {
1220  if (cs->debug & L1_DEB_WARN)
1221  debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
1222  bcs->mode, ireg->cmsb);
1223  }
1224  } else {
1225  debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
1226  ireg->iis, ireg->cmsb, ireg->clsb);
1227  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1228  }
1229  break;
1230  case ISAR_IIS_PSTRSP:
1231  if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1232  rcv_mbox(cs, ireg, (u_char *)ireg->par);
1233  isar_pump_status_rsp(bcs, ireg);
1234  } else {
1235  debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
1236  ireg->iis, ireg->cmsb, ireg->clsb);
1237  cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1238  }
1239  break;
1240  case ISAR_IIS_DIAG:
1241  case ISAR_IIS_BSTRSP:
1242  case ISAR_IIS_IOM2RSP:
1243  rcv_mbox(cs, ireg, (u_char *)ireg->par);
1244  if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
1245  == L1_DEB_HSCX) {
1246  u_char *tp = debbuf;
1247 
1248  tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
1249  ireg->iis, ireg->cmsb);
1250  QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1251  debugl1(cs, debbuf);
1252  }
1253  break;
1254  case ISAR_IIS_INVMSG:
1255  rcv_mbox(cs, ireg, debbuf);
1256  if (cs->debug & L1_DEB_WARN)
1257  debugl1(cs, "invalid msg his:%x",
1258  ireg->cmsb);
1259  break;
1260  default:
1261  rcv_mbox(cs, ireg, debbuf);
1262  if (cs->debug & L1_DEB_WARN)
1263  debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
1264  ireg->iis, ireg->cmsb, ireg->clsb);
1265  break;
1266  }
1267 }
1268 
1269 static void
1270 ftimer_handler(struct BCState *bcs) {
1271  if (bcs->cs->debug)
1272  debugl1(bcs->cs, "ftimer flags %04lx",
1273  bcs->Flag);
1274  test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1275  if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
1276  schedule_event(bcs, B_LL_CONNECT);
1277  }
1278  if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
1279  schedule_event(bcs, B_LL_OK);
1280  }
1281 }
1282 
1283 static void
1284 setup_pump(struct BCState *bcs) {
1285  struct IsdnCardState *cs = bcs->cs;
1286  u_char dps = SET_DPS(bcs->hw.isar.dpath);
1287  u_char ctrl, param[6];
1288 
1289  switch (bcs->mode) {
1290  case L1_MODE_NULL:
1291  case L1_MODE_TRANS:
1292  case L1_MODE_HDLC:
1293  sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
1294  break;
1295  case L1_MODE_V32:
1296  ctrl = PMOD_DATAMODEM;
1297  if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1298  ctrl |= PCTRL_ORIG;
1299  param[5] = PV32P6_CTN;
1300  } else {
1301  param[5] = PV32P6_ATN;
1302  }
1303  param[0] = para_TOA; /* 6 db */
1304  param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
1305  PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
1306  param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
1307  param[3] = PV32P4_UT144;
1308  param[4] = PV32P5_UT144;
1309  sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
1310  break;
1311  case L1_MODE_FAX:
1312  ctrl = PMOD_FAX;
1313  if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1314  ctrl |= PCTRL_ORIG;
1315  param[1] = PFAXP2_CTN;
1316  } else {
1317  param[1] = PFAXP2_ATN;
1318  }
1319  param[0] = para_TOA; /* 6 db */
1320  sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
1321  bcs->hw.isar.state = STFAX_NULL;
1322  bcs->hw.isar.newcmd = 0;
1323  bcs->hw.isar.newmod = 0;
1324  test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1325  break;
1326  }
1327  udelay(1000);
1328  sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1329  udelay(1000);
1330 }
1331 
1332 static void
1333 setup_sart(struct BCState *bcs) {
1334  struct IsdnCardState *cs = bcs->cs;
1335  u_char dps = SET_DPS(bcs->hw.isar.dpath);
1336  u_char ctrl, param[2];
1337 
1338  switch (bcs->mode) {
1339  case L1_MODE_NULL:
1340  sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
1341  NULL);
1342  break;
1343  case L1_MODE_TRANS:
1344  sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
1345  "\0\0");
1346  break;
1347  case L1_MODE_HDLC:
1348  param[0] = 0;
1349  sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
1350  param);
1351  break;
1352  case L1_MODE_V32:
1353  ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
1354  param[0] = S_P1_CHS_8;
1355  param[1] = S_P2_BFT_DEF;
1356  sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
1357  param);
1358  break;
1359  case L1_MODE_FAX:
1360  /* SART must not configured with FAX */
1361  break;
1362  }
1363  udelay(1000);
1364  sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
1365  udelay(1000);
1366 }
1367 
1368 static void
1369 setup_iom2(struct BCState *bcs) {
1370  struct IsdnCardState *cs = bcs->cs;
1371  u_char dps = SET_DPS(bcs->hw.isar.dpath);
1372  u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD, 0, 0, 0, 0};
1373 
1374  if (bcs->channel)
1375  msg[1] = msg[3] = 1;
1376  switch (bcs->mode) {
1377  case L1_MODE_NULL:
1378  cmsb = 0;
1379  /* dummy slot */
1380  msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
1381  break;
1382  case L1_MODE_TRANS:
1383  case L1_MODE_HDLC:
1384  break;
1385  case L1_MODE_V32:
1386  case L1_MODE_FAX:
1387  cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
1388  break;
1389  }
1390  sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
1391  udelay(1000);
1392  sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
1393  udelay(1000);
1394 }
1395 
1396 static int
1397 modeisar(struct BCState *bcs, int mode, int bc)
1398 {
1399  struct IsdnCardState *cs = bcs->cs;
1400 
1401  /* Here we are selecting the best datapath for requested mode */
1402  if (bcs->mode == L1_MODE_NULL) { /* New Setup */
1403  bcs->channel = bc;
1404  switch (mode) {
1405  case L1_MODE_NULL: /* init */
1406  if (!bcs->hw.isar.dpath)
1407  /* no init for dpath 0 */
1408  return (0);
1409  break;
1410  case L1_MODE_TRANS:
1411  case L1_MODE_HDLC:
1412  /* best is datapath 2 */
1413  if (!test_and_set_bit(ISAR_DP2_USE,
1414  &bcs->hw.isar.reg->Flags))
1415  bcs->hw.isar.dpath = 2;
1416  else if (!test_and_set_bit(ISAR_DP1_USE,
1417  &bcs->hw.isar.reg->Flags))
1418  bcs->hw.isar.dpath = 1;
1419  else {
1420  printk(KERN_WARNING"isar modeisar both pathes in use\n");
1421  return (1);
1422  }
1423  break;
1424  case L1_MODE_V32:
1425  case L1_MODE_FAX:
1426  /* only datapath 1 */
1427  if (!test_and_set_bit(ISAR_DP1_USE,
1428  &bcs->hw.isar.reg->Flags))
1429  bcs->hw.isar.dpath = 1;
1430  else {
1431  printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");
1432  debugl1(cs, "isar modeisar analog functions only with DP1");
1433  return (1);
1434  }
1435  break;
1436  }
1437  }
1438  if (cs->debug & L1_DEB_HSCX)
1439  debugl1(cs, "isar dp%d mode %d->%d ichan %d",
1440  bcs->hw.isar.dpath, bcs->mode, mode, bc);
1441  bcs->mode = mode;
1442  setup_pump(bcs);
1443  setup_iom2(bcs);
1444  setup_sart(bcs);
1445  if (bcs->mode == L1_MODE_NULL) {
1446  /* Clear resources */
1447  if (bcs->hw.isar.dpath == 1)
1448  test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
1449  else if (bcs->hw.isar.dpath == 2)
1450  test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
1451  bcs->hw.isar.dpath = 0;
1452  }
1453  return (0);
1454 }
1455 
1456 static void
1457 isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
1458 {
1459  struct IsdnCardState *cs = bcs->cs;
1460  u_char dps = SET_DPS(bcs->hw.isar.dpath);
1461  u_char ctrl = 0, nom = 0, p1 = 0;
1462 
1463  switch (cmd) {
1464  case ISDN_FAX_CLASS1_FTM:
1465  test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1466  if (bcs->hw.isar.state == STFAX_READY) {
1467  p1 = para;
1468  ctrl = PCTRL_CMD_FTM;
1469  nom = 1;
1470  bcs->hw.isar.state = STFAX_LINE;
1471  bcs->hw.isar.cmd = ctrl;
1472  bcs->hw.isar.mod = para;
1473  bcs->hw.isar.newmod = 0;
1474  bcs->hw.isar.newcmd = 0;
1475  bcs->hw.isar.try_mod = 3;
1476  } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1477  (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
1478  (bcs->hw.isar.mod == para)) {
1479  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1480  } else {
1481  bcs->hw.isar.newmod = para;
1482  bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
1483  nom = 0;
1484  ctrl = PCTRL_CMD_ESC;
1485  bcs->hw.isar.state = STFAX_ESCAPE;
1486  }
1487  break;
1488  case ISDN_FAX_CLASS1_FTH:
1489  test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1490  if (bcs->hw.isar.state == STFAX_READY) {
1491  p1 = para;
1492  ctrl = PCTRL_CMD_FTH;
1493  nom = 1;
1494  bcs->hw.isar.state = STFAX_LINE;
1495  bcs->hw.isar.cmd = ctrl;
1496  bcs->hw.isar.mod = para;
1497  bcs->hw.isar.newmod = 0;
1498  bcs->hw.isar.newcmd = 0;
1499  bcs->hw.isar.try_mod = 3;
1500  } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1501  (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
1502  (bcs->hw.isar.mod == para)) {
1503  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1504  } else {
1505  bcs->hw.isar.newmod = para;
1506  bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
1507  nom = 0;
1508  ctrl = PCTRL_CMD_ESC;
1509  bcs->hw.isar.state = STFAX_ESCAPE;
1510  }
1511  break;
1512  case ISDN_FAX_CLASS1_FRM:
1513  test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1514  if (bcs->hw.isar.state == STFAX_READY) {
1515  p1 = para;
1516  ctrl = PCTRL_CMD_FRM;
1517  nom = 1;
1518  bcs->hw.isar.state = STFAX_LINE;
1519  bcs->hw.isar.cmd = ctrl;
1520  bcs->hw.isar.mod = para;
1521  bcs->hw.isar.newmod = 0;
1522  bcs->hw.isar.newcmd = 0;
1523  bcs->hw.isar.try_mod = 3;
1524  } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1525  (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
1526  (bcs->hw.isar.mod == para)) {
1527  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1528  } else {
1529  bcs->hw.isar.newmod = para;
1530  bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
1531  nom = 0;
1532  ctrl = PCTRL_CMD_ESC;
1533  bcs->hw.isar.state = STFAX_ESCAPE;
1534  }
1535  break;
1536  case ISDN_FAX_CLASS1_FRH:
1537  test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1538  if (bcs->hw.isar.state == STFAX_READY) {
1539  p1 = para;
1540  ctrl = PCTRL_CMD_FRH;
1541  nom = 1;
1542  bcs->hw.isar.state = STFAX_LINE;
1543  bcs->hw.isar.cmd = ctrl;
1544  bcs->hw.isar.mod = para;
1545  bcs->hw.isar.newmod = 0;
1546  bcs->hw.isar.newcmd = 0;
1547  bcs->hw.isar.try_mod = 3;
1548  } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1549  (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
1550  (bcs->hw.isar.mod == para)) {
1551  ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1552  } else {
1553  bcs->hw.isar.newmod = para;
1554  bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
1555  nom = 0;
1556  ctrl = PCTRL_CMD_ESC;
1557  bcs->hw.isar.state = STFAX_ESCAPE;
1558  }
1559  break;
1560  case ISDN_FAXPUMP_HALT:
1561  bcs->hw.isar.state = STFAX_NULL;
1562  nom = 0;
1563  ctrl = PCTRL_CMD_HALT;
1564  break;
1565  }
1566  if (ctrl)
1567  sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
1568 }
1569 
1570 static void
1571 isar_setup(struct IsdnCardState *cs)
1572 {
1573  u_char msg;
1574  int i;
1575 
1576  /* Dpath 1, 2 */
1577  msg = 61;
1578  for (i = 0; i < 2; i++) {
1579  /* Buffer Config */
1580  sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1581  ISAR_HIS_P12CFG, 4, 1, &msg);
1582  cs->bcs[i].hw.isar.mml = msg;
1583  cs->bcs[i].mode = 0;
1584  cs->bcs[i].hw.isar.dpath = i + 1;
1585  modeisar(&cs->bcs[i], 0, 0);
1586  INIT_WORK(&cs->bcs[i].tqueue, isar_bh);
1587  }
1588 }
1589 
1590 static void
1591 isar_l2l1(struct PStack *st, int pr, void *arg)
1592 {
1593  struct BCState *bcs = st->l1.bcs;
1594  struct sk_buff *skb = arg;
1595  int ret;
1596  u_long flags;
1597 
1598  switch (pr) {
1599  case (PH_DATA | REQUEST):
1600  spin_lock_irqsave(&bcs->cs->lock, flags);
1601  if (bcs->tx_skb) {
1602  skb_queue_tail(&bcs->squeue, skb);
1603  } else {
1604  bcs->tx_skb = skb;
1605  test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1606  if (bcs->cs->debug & L1_DEB_HSCX)
1607  debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
1608  bcs->hw.isar.txcnt = 0;
1609  bcs->cs->BC_Send_Data(bcs);
1610  }
1611  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1612  break;
1613  case (PH_PULL | INDICATION):
1614  spin_lock_irqsave(&bcs->cs->lock, flags);
1615  if (bcs->tx_skb) {
1616  printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
1617  } else {
1618  test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1619  if (bcs->cs->debug & L1_DEB_HSCX)
1620  debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
1621  bcs->tx_skb = skb;
1622  bcs->hw.isar.txcnt = 0;
1623  bcs->cs->BC_Send_Data(bcs);
1624  }
1625  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1626  break;
1627  case (PH_PULL | REQUEST):
1628  if (!bcs->tx_skb) {
1629  test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1630  st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1631  } else
1632  test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1633  break;
1634  case (PH_ACTIVATE | REQUEST):
1635  spin_lock_irqsave(&bcs->cs->lock, flags);
1636  test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1637  bcs->hw.isar.conmsg[0] = 0;
1638  if (test_bit(FLG_ORIG, &st->l2.flag))
1639  test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
1640  else
1641  test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
1642  switch (st->l1.mode) {
1643  case L1_MODE_TRANS:
1644  case L1_MODE_HDLC:
1645  ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1646  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1647  if (ret)
1648  l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1649  else
1650  l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
1651  break;
1652  case L1_MODE_V32:
1653  case L1_MODE_FAX:
1654  ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1655  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1656  if (ret)
1657  l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1658  break;
1659  default:
1660  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1661  break;
1662  }
1663  break;
1664  case (PH_DEACTIVATE | REQUEST):
1665  l1_msg_b(st, pr, arg);
1666  break;
1667  case (PH_DEACTIVATE | CONFIRM):
1668  spin_lock_irqsave(&bcs->cs->lock, flags);
1669  switch (st->l1.mode) {
1670  case L1_MODE_TRANS:
1671  case L1_MODE_HDLC:
1672  case L1_MODE_V32:
1673  break;
1674  case L1_MODE_FAX:
1675  isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
1676  break;
1677  }
1678  test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1679  test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1680  if (bcs->cs->debug & L1_DEB_HSCX)
1681  debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
1682  modeisar(bcs, 0, st->l1.bc);
1683  spin_unlock_irqrestore(&bcs->cs->lock, flags);
1684  st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1685  break;
1686  }
1687 }
1688 
1689 static void
1690 close_isarstate(struct BCState *bcs)
1691 {
1692  modeisar(bcs, 0, bcs->channel);
1693  if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1694  kfree(bcs->hw.isar.rcvbuf);
1695  bcs->hw.isar.rcvbuf = NULL;
1696  skb_queue_purge(&bcs->rqueue);
1697  skb_queue_purge(&bcs->squeue);
1698  if (bcs->tx_skb) {
1699  dev_kfree_skb_any(bcs->tx_skb);
1700  bcs->tx_skb = NULL;
1701  test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1702  if (bcs->cs->debug & L1_DEB_HSCX)
1703  debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
1704  }
1705  }
1706  del_timer(&bcs->hw.isar.ftimer);
1707 }
1708 
1709 static int
1710 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
1711 {
1712  if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1713  if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
1714  printk(KERN_WARNING
1715  "HiSax: No memory for isar.rcvbuf\n");
1716  return (1);
1717  }
1718  skb_queue_head_init(&bcs->rqueue);
1719  skb_queue_head_init(&bcs->squeue);
1720  }
1721  bcs->tx_skb = NULL;
1722  test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1723  if (cs->debug & L1_DEB_HSCX)
1724  debugl1(cs, "openisar clear BC_FLG_BUSY");
1725  bcs->event = 0;
1726  bcs->hw.isar.rcvidx = 0;
1727  bcs->tx_cnt = 0;
1728  return (0);
1729 }
1730 
1731 static int
1732 setstack_isar(struct PStack *st, struct BCState *bcs)
1733 {
1734  bcs->channel = st->l1.bc;
1735  if (open_isarstate(st->l1.hardware, bcs))
1736  return (-1);
1737  st->l1.bcs = bcs;
1738  st->l2.l2l1 = isar_l2l1;
1739  setstack_manager(st);
1740  bcs->st = st;
1741  setstack_l1_B(st);
1742  return (0);
1743 }
1744 
1745 int
1746 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
1747  u_long adr;
1748  int features, i;
1749  struct BCState *bcs;
1750 
1751  if (cs->debug & L1_DEB_HSCX)
1752  debugl1(cs, "isar_auxcmd cmd/ch %x/%ld", ic->command, ic->arg);
1753  switch (ic->command) {
1754  case (ISDN_CMD_FAXCMD):
1755  bcs = cs->channel[ic->arg].bcs;
1756  if (cs->debug & L1_DEB_HSCX)
1757  debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
1758  ic->parm.aux.cmd, ic->parm.aux.subcmd);
1759  switch (ic->parm.aux.cmd) {
1760  case ISDN_FAX_CLASS1_CTRL:
1761  if (ic->parm.aux.subcmd == ETX)
1762  test_and_set_bit(BC_FLG_DLEETX,
1763  &bcs->Flag);
1764  break;
1765  case ISDN_FAX_CLASS1_FTS:
1766  if (ic->parm.aux.subcmd == AT_QUERY) {
1767  ic->command = ISDN_STAT_FAXIND;
1768  ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1769  cs->iif.statcallb(ic);
1770  return (0);
1771  } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1772  strcpy(ic->parm.aux.para, "0-255");
1773  ic->command = ISDN_STAT_FAXIND;
1774  ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1775  cs->iif.statcallb(ic);
1776  return (0);
1777  } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1778  if (cs->debug & L1_DEB_HSCX)
1779  debugl1(cs, "isar_auxcmd %s=%d",
1780  FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1781  if (bcs->hw.isar.state == STFAX_READY) {
1782  if (!ic->parm.aux.para[0]) {
1783  ic->command = ISDN_STAT_FAXIND;
1784  ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1785  cs->iif.statcallb(ic);
1786  return (0);
1787  }
1788  if (!test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
1789  /* n*10 ms */
1790  bcs->hw.isar.ftimer.expires =
1791  jiffies + ((ic->parm.aux.para[0] * 10 * HZ) / 1000);
1792  test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
1793  add_timer(&bcs->hw.isar.ftimer);
1794  return (0);
1795  } else {
1796  if (cs->debug)
1797  debugl1(cs, "isar FTS=%d and FTI busy",
1798  ic->parm.aux.para[0]);
1799  }
1800  } else {
1801  if (cs->debug)
1802  debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
1803  ic->parm.aux.para[0], bcs->hw.isar.state);
1804  }
1805  ic->command = ISDN_STAT_FAXIND;
1806  ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1807  cs->iif.statcallb(ic);
1808  }
1809  break;
1810  case ISDN_FAX_CLASS1_FRM:
1811  case ISDN_FAX_CLASS1_FRH:
1812  case ISDN_FAX_CLASS1_FTM:
1813  case ISDN_FAX_CLASS1_FTH:
1814  if (ic->parm.aux.subcmd == AT_QUERY) {
1815  sprintf(ic->parm.aux.para,
1816  "%d", bcs->hw.isar.mod);
1817  ic->command = ISDN_STAT_FAXIND;
1818  ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1819  cs->iif.statcallb(ic);
1820  return (0);
1821  } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1822  char *p = ic->parm.aux.para;
1823  for (i = 0; i < FAXMODCNT; i++)
1824  if ((1 << i) & modmask)
1825  p += sprintf(p, "%d,", faxmodulation[i]);
1826  p--;
1827  *p = 0;
1828  ic->command = ISDN_STAT_FAXIND;
1829  ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1830  cs->iif.statcallb(ic);
1831  return (0);
1832  } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1833  if (cs->debug & L1_DEB_HSCX)
1834  debugl1(cs, "isar_auxcmd %s=%d",
1835  FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1836  for (i = 0; i < FAXMODCNT; i++)
1837  if (faxmodulation[i] == ic->parm.aux.para[0])
1838  break;
1839  if ((i < FAXMODCNT) && ((1 << i) & modmask) &&
1840  test_bit(BC_FLG_INIT, &bcs->Flag)) {
1841  isar_pump_cmd(bcs,
1842  ic->parm.aux.cmd,
1843  ic->parm.aux.para[0]);
1844  return (0);
1845  }
1846  }
1847  /* wrong modulation or not activ */
1848  /* fall through */
1849  default:
1850  ic->command = ISDN_STAT_FAXIND;
1851  ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1852  cs->iif.statcallb(ic);
1853  }
1854  break;
1855  case (ISDN_CMD_IOCTL):
1856  switch (ic->arg) {
1857  case 9: /* load firmware */
1858  features = ISDN_FEATURE_L2_MODEM |
1859  ISDN_FEATURE_L2_FAX |
1860  ISDN_FEATURE_L3_FCLASS1;
1861  memcpy(&adr, ic->parm.num, sizeof(ulong));
1862  if (isar_load_firmware(cs, (u_char __user *)adr))
1863  return (1);
1864  else
1865  ll_run(cs, features);
1866  break;
1867  case 20:
1868  features = *(unsigned int *) ic->parm.num;
1869  printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
1870  modmask, features);
1871  modmask = features;
1872  break;
1873  case 21:
1874  features = *(unsigned int *) ic->parm.num;
1875  printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
1876  frm_extra_delay, features);
1877  if (features >= 0)
1878  frm_extra_delay = features;
1879  break;
1880  case 22:
1881  features = *(unsigned int *) ic->parm.num;
1882  printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
1883  para_TOA, features);
1884  if (features >= 0 && features < 32)
1885  para_TOA = features;
1886  break;
1887  default:
1888  printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
1889  (int) ic->arg);
1890  return (-EINVAL);
1891  }
1892  break;
1893  default:
1894  return (-EINVAL);
1895  }
1896  return (0);
1897 }
1898 
1899 void initisar(struct IsdnCardState *cs)
1900 {
1901  cs->bcs[0].BC_SetStack = setstack_isar;
1902  cs->bcs[1].BC_SetStack = setstack_isar;
1903  cs->bcs[0].BC_Close = close_isarstate;
1904  cs->bcs[1].BC_Close = close_isarstate;
1905  cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler;
1906  cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0];
1907  init_timer(&cs->bcs[0].hw.isar.ftimer);
1908  cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler;
1909  cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1];
1910  init_timer(&cs->bcs[1].hw.isar.ftimer);
1911 }
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