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64 #ifndef __il_commands_h__
65 #define __il_commands_h__
72 #define IL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
73 #define IL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
74 #define IL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
75 #define IL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
78 #define IL_CCK_RATES 4
79 #define IL_OFDM_RATES 8
80 #define IL_MAX_RATES (IL_CCK_RATES + IL_OFDM_RATES)
163 #define IL_CMD_FAILED_MSK 0x40
165 #define SEQ_TO_QUEUE(s) (((s) >> 8) & 0x1f)
166 #define QUEUE_TO_SEQ(q) (((q) & 0x1f) << 8)
167 #define SEQ_TO_IDX(s) ((s) & 0xff)
168 #define IDX_TO_SEQ(i) ((i) & 0xff)
169 #define SEQ_HUGE_FRAME cpu_to_le16(0x4000)
170 #define SEQ_RX_FRAME cpu_to_le16(0x8000)
280 #define RATE_MCS_CODE_MSK 0x7
281 #define RATE_MCS_SPATIAL_POS 3
282 #define RATE_MCS_SPATIAL_MSK 0x18
283 #define RATE_MCS_HT_DUP_POS 5
284 #define RATE_MCS_HT_DUP_MSK 0x20
287 #define RATE_MCS_FLAGS_POS 8
288 #define RATE_MCS_HT_POS 8
289 #define RATE_MCS_HT_MSK 0x100
292 #define RATE_MCS_CCK_POS 9
293 #define RATE_MCS_CCK_MSK 0x200
296 #define RATE_MCS_GF_POS 10
297 #define RATE_MCS_GF_MSK 0x400
300 #define RATE_MCS_HT40_POS 11
301 #define RATE_MCS_HT40_MSK 0x800
304 #define RATE_MCS_DUP_POS 12
305 #define RATE_MCS_DUP_MSK 0x1000
308 #define RATE_MCS_SGI_POS 13
309 #define RATE_MCS_SGI_MSK 0x2000
316 #define RATE_MCS_ANT_POS 14
317 #define RATE_MCS_ANT_A_MSK 0x04000
318 #define RATE_MCS_ANT_B_MSK 0x08000
319 #define RATE_MCS_ANT_C_MSK 0x10000
320 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
321 #define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
322 #define RATE_ANT_NUM 3
324 #define POWER_TBL_NUM_ENTRIES 33
325 #define POWER_TBL_NUM_HT_OFDM_ENTRIES 32
326 #define POWER_TBL_CCK_ENTRY 32
328 #define IL_PWR_NUM_HT_OFDM_ENTRIES 24
329 #define IL_PWR_CCK_ENTRIES 2
381 #define UCODE_VALID_OK cpu_to_le32(0x1)
382 #define INITIALIZE_SUBTYPE (9)
551 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
552 #define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
553 #define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
554 #define RXON_RX_CHAIN_VALID_POS (1)
555 #define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
556 #define RXON_RX_CHAIN_FORCE_SEL_POS (4)
557 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
558 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
559 #define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
560 #define RXON_RX_CHAIN_CNT_POS (10)
561 #define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
562 #define RXON_RX_CHAIN_MIMO_CNT_POS (12)
563 #define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
564 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
568 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
569 #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
571 #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
573 #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
575 #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
576 #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
578 #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
579 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
580 #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
581 #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
583 #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
584 #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
587 #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
590 #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
591 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
593 #define RXON_FLG_HT_OPERATING_MODE_POS (23)
595 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
596 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
598 #define RXON_FLG_CHANNEL_MODE_POS (25)
599 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
608 #define RXON_FLG_CHANNEL_MODE_LEGACY \
609 cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
610 #define RXON_FLG_CHANNEL_MODE_PURE_40 \
611 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
612 #define RXON_FLG_CHANNEL_MODE_MIXED \
613 cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
616 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
620 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
622 #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
624 #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
626 #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
628 #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
630 #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
632 #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
738 #define IL_CONN_MAX_LISTEN_INTERVAL 10
739 #define IL_MAX_UCODE_BEACON_INTERVAL 4
740 #define IL39_MAX_UCODE_BEACON_INTERVAL 1
818 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
819 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
820 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
848 #define IL3945_BROADCAST_ID 24
849 #define IL3945_STATION_COUNT 25
850 #define IL4965_BROADCAST_ID 31
851 #define IL4965_STATION_COUNT 32
853 #define IL_STATION_COUNT 32
854 #define IL_INVALID_STATION 255
856 #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
857 #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
858 #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
859 #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
860 #define STA_FLG_MAX_AGG_SIZE_POS (19)
861 #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
862 #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
863 #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
864 #define STA_FLG_AGG_MPDU_DENSITY_POS (23)
865 #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
868 #define STA_CONTROL_MODIFY_MSK 0x01
871 #define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
872 #define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
873 #define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
874 #define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
875 #define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
877 #define STA_KEY_FLG_KEYID_POS 8
878 #define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
880 #define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
883 #define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
884 #define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
885 #define STA_KEY_MAX_NUM 8
888 #define STA_MODIFY_KEY_MASK 0x01
889 #define STA_MODIFY_TID_DISABLE_TX 0x02
890 #define STA_MODIFY_TX_RATE_MSK 0x04
891 #define STA_MODIFY_ADDBA_TID_MSK 0x08
892 #define STA_MODIFY_DELBA_TID_MSK 0x10
893 #define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
897 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1059 #define ADD_STA_SUCCESS_MSK 0x1
1060 #define ADD_STA_NO_ROOM_IN_TBL 0x2
1061 #define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
1062 #define ADD_STA_MODIFY_NON_EXIST_STA 0x8
1070 #define REM_STA_SUCCESS_MSK 0x1
1088 #define IL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
1089 #define IL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1))
1090 #define IL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2))
1091 #define IL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3))
1092 #define IL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
1094 #define IL_DROP_SINGLE 0
1095 #define IL_DROP_SELECTED 1
1096 #define IL_DROP_ALL 2
1118 #define WEP_KEY_WEP_TYPE 1
1119 #define WEP_KEYS_MAX 4
1120 #define WEP_INVALID_OFFSET 0xff
1121 #define WEP_KEY_LEN_64 5
1122 #define WEP_KEY_LEN_128 13
1130 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1131 #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1133 #define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1134 #define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1135 #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1136 #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1137 #define RX_RES_PHY_FLAGS_ANTENNA_MSK 0xf0
1138 #define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1140 #define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1141 #define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1142 #define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1143 #define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1144 #define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1145 #define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1147 #define RX_RES_STATUS_STATION_FOUND (1<<6)
1148 #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1150 #define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1151 #define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1152 #define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1153 #define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1154 #define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1156 #define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1157 #define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1158 #define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1159 #define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1200 #define IL39_RX_FRAME_SIZE (4 + sizeof(struct il3945_rx_frame))
1204 #define IL49_RX_RES_PHY_CNT 14
1205 #define IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET (4)
1206 #define IL49_RX_PHY_FLAGS_ANTENNAE_MASK (0x70)
1207 #define IL49_AGC_DB_MASK (0x3f80)
1208 #define IL49_AGC_DB_POS (7)
1271 #define TX_CMD_FLG_RTS_MSK cpu_to_le32(1 << 1)
1278 #define TX_CMD_FLG_CTS_MSK cpu_to_le32(1 << 2)
1283 #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1291 #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1295 #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1301 #define TX_CMD_FLG_FULL_TXOP_PROT_MSK cpu_to_le32(1 << 7)
1305 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1306 #define TX_CMD_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
1307 #define TX_CMD_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
1313 #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1317 #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1322 #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1330 #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1334 #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1337 #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1342 #define TX_CMD_SEC_WEP 0x01
1343 #define TX_CMD_SEC_CCM 0x02
1344 #define TX_CMD_SEC_TKIP 0x03
1345 #define TX_CMD_SEC_MSK 0x03
1346 #define TX_CMD_SEC_SHIFT 6
1347 #define TX_CMD_SEC_KEY128 0x08
1352 #define WEP_IV_LEN 4
1353 #define WEP_ICV_LEN 4
1354 #define CCMP_MIC_LEN 8
1355 #define TKIP_ICV_LEN 4
1607 #define TX_PACKET_MODE_REGULAR 0x0000
1608 #define TX_PACKET_MODE_BURST_SEQ 0x0100
1609 #define TX_PACKET_MODE_BURST_FIRST 0x0200
1644 #define AGG_TX_STATUS_MSK 0x00000fff
1645 #define AGG_TX_TRY_MSK 0x0000f000
1647 #define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1648 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK)
1651 #define AGG_TX_STATE_TRY_CNT_POS 12
1652 #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1655 #define AGG_TX_STATE_SEQ_NUM_POS 16
1656 #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1789 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1792 #define LINK_QUAL_AC_NUM AC_NUM
1795 #define LINK_QUAL_MAX_RETRY_NUM 16
1798 #define LINK_QUAL_ANT_A_MSK (1 << 0)
1799 #define LINK_QUAL_ANT_B_MSK (1 << 1)
1800 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1833 #define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1834 #define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1835 #define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1837 #define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1838 #define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1839 #define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1841 #define LINK_QUAL_AGG_FRAME_LIMIT_DEF (31)
1842 #define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1843 #define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
2091 #define BT_COEX_DISABLE (0x0)
2092 #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
2093 #define BT_ENABLE_PRIORITY BIT(1)
2095 #define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
2097 #define BT_LEAD_TIME_DEF (0x1E)
2099 #define BT_MAX_KILL_DEF (0x5)
2126 #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
2127 RXON_FILTER_CTL2HOST_MSK | \
2128 RXON_FILTER_ACCEPT_GRP_MSK | \
2129 RXON_FILTER_DIS_DECRYPT_MSK | \
2130 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
2131 RXON_FILTER_ASSOC_MSK | \
2132 RXON_FILTER_BCON_AWARE_MSK)
2188 #define NUM_ELEMENTS_IN_HISTOGRAM 8
2278 #define IL_POWER_VEC_SIZE 5
2280 #define IL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2281 #define IL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2336 #define HW_CARD_DISABLED 0x01
2337 #define SW_CARD_DISABLED 0x02
2338 #define CT_CARD_DISABLED 0x04
2339 #define RXON_CARD_DISABLED 0x10
2353 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2354 #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2391 #define IL39_SCAN_PROBE_MASK(n) ((BIT(n) | (BIT(n) - BIT(1))))
2410 #define IL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2426 #define PROBE_OPTION_MAX_3945 4
2427 #define PROBE_OPTION_MAX 20
2428 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2429 #define IL_GOOD_CRC_TH_DISABLED 0
2430 #define IL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2431 #define IL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2432 #define IL_MAX_SCAN_SIZE 1024
2433 #define IL_MAX_CMD_SIZE 4096
2577 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2579 #define ABORT_STATUS 0x2
2601 #define SCAN_OWNER_STATUS 0x1
2602 #define MEASURE_OWNER_STATUS 0x2
2604 #define IL_PROBE_STATUS_OK 0
2605 #define IL_PROBE_STATUS_TX_FAILED BIT(0)
2607 #define IL_PROBE_STATUS_FAIL_TTL BIT(1)
2608 #define IL_PROBE_STATUS_FAIL_BT BIT(2)
2610 #define NUMBER_OF_STATS 1
2690 #define IL_TEMP_CONVERT 260
2692 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2693 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2694 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2819 #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2940 #define UCODE_STATS_CLEAR_MSK (0x1 << 0)
2941 #define UCODE_STATS_FREQUENCY_MSK (0x1 << 1)
2942 #define UCODE_STATS_NARROW_BAND_MSK (0x1 << 2)
2959 #define IL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2960 #define IL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2980 #define STATS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2981 #define STATS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
3017 #define IL_MISSED_BEACON_THRESHOLD_MIN (1)
3018 #define IL_MISSED_BEACON_THRESHOLD_DEF (5)
3019 #define IL_MISSED_BEACON_THRESHOLD_MAX IL_MISSED_BEACON_THRESHOLD_DEF
3200 #define HD_TBL_SIZE (11)
3201 #define HD_MIN_ENERGY_CCK_DET_IDX (0)
3202 #define HD_MIN_ENERGY_OFDM_DET_IDX (1)
3203 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_IDX (2)
3204 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX (3)
3205 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX (4)
3206 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_IDX (5)
3207 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX (6)
3208 #define HD_BARKER_CORR_TH_ADD_MIN_IDX (7)
3209 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_IDX (8)
3210 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX (9)
3211 #define HD_OFDM_ENERGY_TH_IN_IDX (10)
3214 #define C_SENSITIVITY_CONTROL_DEFAULT_TBL cpu_to_le16(0)
3215 #define C_SENSITIVITY_CONTROL_WORK_TBL cpu_to_le16(1)
3286 #define IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
3292 #define IL_MAX_PHY_CALIBRATE_TBL_SIZE (253)
3339 #define IL_RX_FRAME_SIZE_MSK 0x00003fff