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Linux Kernel
3.7.1
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#include <linux/init.h>#include <linux/interrupt.h>#include <linux/kernel.h>#include <linux/ptrace.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/ctype.h>#include <linux/timer.h>#include <asm/byteorder.h>#include <asm/io.h>#include <asm/uaccess.h>#include <linux/module.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/if_arp.h>#include <linux/ioport.h>#include <linux/fcntl.h>#include <linux/delay.h>#include <linux/wireless.h>#include <net/iw_handler.h>#include <linux/crc32.h>#include <linux/proc_fs.h>#include <linux/device.h>#include <linux/moduleparam.h>#include <linux/firmware.h>#include <linux/jiffies.h>#include <linux/ieee80211.h>#include "atmel.h"Go to the source code of this file.
Data Structures | |
| struct | get_set_mib |
| struct | rx_desc |
| struct | tx_desc |
| struct | atmel_private |
| struct | atmel_private::host_info_struct |
| struct | atmel_private::bss_info |
| struct | atmel_priv_ioctl |
| struct | auth_body |
Macros | |
| #define | DRIVER_MAJOR 0 |
| #define | DRIVER_MINOR 98 |
| #define | MAX_SSID_LENGTH 32 |
| #define | MGMT_JIFFIES (256 * HZ / 100) |
| #define | MAX_BSS_ENTRIES 64 |
| #define | GCR 0x00 /* (SIR0) General Configuration Register */ |
| #define | BSR 0x02 /* (SIR1) Bank Switching Select Register */ |
| #define | AR 0x04 |
| #define | DR 0x08 |
| #define | MR1 0x12 /* Mirror Register 1 */ |
| #define | MR2 0x14 /* Mirror Register 2 */ |
| #define | MR3 0x16 /* Mirror Register 3 */ |
| #define | MR4 0x18 /* Mirror Register 4 */ |
| #define | GPR1 0x0c |
| #define | GPR2 0x0e |
| #define | GPR3 0x10 |
| #define | GCR_REMAP 0x0400 /* Remap internal SRAM to 0 */ |
| #define | GCR_SWRES 0x0080 /* BIU reset (ARM and PAI are NOT reset) */ |
| #define | GCR_CORES 0x0060 /* Core Reset (ARM and PAI are reset) */ |
| #define | GCR_ENINT 0x0002 /* Enable Interrupts */ |
| #define | GCR_ACKINT 0x0008 /* Acknowledge Interrupts */ |
| #define | BSS_SRAM 0x0200 /* AMBA module selection --> SRAM */ |
| #define | BSS_IRAM 0x0100 /* AMBA module selection --> IRAM */ |
| #define | MAC_INIT_COMPLETE 0x0001 /* MAC init has been completed */ |
| #define | MAC_BOOT_COMPLETE 0x0010 /* MAC boot has been completed */ |
| #define | MAC_INIT_OK 0x0002 /* MAC boot has been completed */ |
| #define | MIB_MAX_DATA_BYTES 212 |
| #define | MIB_HEADER_SIZE 4 /* first four fields */ |
| #define | RX_DESC_FLAG_VALID 0x80 |
| #define | RX_DESC_FLAG_CONSUMED 0x40 |
| #define | RX_DESC_FLAG_IDLE 0x00 |
| #define | RX_STATUS_SUCCESS 0x00 |
| #define | RX_DESC_MSDU_POS_OFFSET 4 |
| #define | RX_DESC_MSDU_SIZE_OFFSET 6 |
| #define | RX_DESC_FLAGS_OFFSET 8 |
| #define | RX_DESC_STATUS_OFFSET 9 |
| #define | RX_DESC_RSSI_OFFSET 11 |
| #define | RX_DESC_LINK_QUALITY_OFFSET 12 |
| #define | RX_DESC_PREAMBLE_TYPE_OFFSET 13 |
| #define | RX_DESC_DURATION_OFFSET 14 |
| #define | RX_DESC_RX_TIME_OFFSET 16 |
| #define | TX_DESC_NEXT_OFFSET 0 |
| #define | TX_DESC_POS_OFFSET 4 |
| #define | TX_DESC_SIZE_OFFSET 6 |
| #define | TX_DESC_FLAGS_OFFSET 8 |
| #define | TX_DESC_STATUS_OFFSET 9 |
| #define | TX_DESC_RETRY_OFFSET 10 |
| #define | TX_DESC_RATE_OFFSET 11 |
| #define | TX_DESC_KEY_INDEX_OFFSET 12 |
| #define | TX_DESC_CIPHER_TYPE_OFFSET 13 |
| #define | TX_DESC_CIPHER_LENGTH_OFFSET 14 |
| #define | TX_DESC_PACKET_TYPE_OFFSET 17 |
| #define | TX_DESC_HOST_LENGTH_OFFSET 18 |
| #define | TX_STATUS_SUCCESS 0x00 |
| #define | TX_FIRM_OWN 0x80 |
| #define | TX_DONE 0x40 |
| #define | TX_ERROR 0x01 |
| #define | TX_PACKET_TYPE_DATA 0x01 |
| #define | TX_PACKET_TYPE_MGMT 0x02 |
| #define | ISR_EMPTY 0x00 /* no bits set in ISR */ |
| #define | ISR_TxCOMPLETE 0x01 /* packet transmitted */ |
| #define | ISR_RxCOMPLETE 0x02 /* packet received */ |
| #define | ISR_RxFRAMELOST 0x04 /* Rx Frame lost */ |
| #define | ISR_FATAL_ERROR 0x08 /* Fatal error */ |
| #define | ISR_COMMAND_COMPLETE 0x10 /* command completed */ |
| #define | ISR_OUT_OF_RANGE 0x20 /* command completed */ |
| #define | ISR_IBSS_MERGE 0x40 /* (4.1.2.30): IBSS merge */ |
| #define | ISR_GENERIC_IRQ 0x80 |
| #define | Local_Mib_Type 0x01 |
| #define | Mac_Address_Mib_Type 0x02 |
| #define | Mac_Mib_Type 0x03 |
| #define | Statistics_Mib_Type 0x04 |
| #define | Mac_Mgmt_Mib_Type 0x05 |
| #define | Mac_Wep_Mib_Type 0x06 |
| #define | Phy_Mib_Type 0x07 |
| #define | Multi_Domain_MIB 0x08 |
| #define | MAC_MGMT_MIB_CUR_BSSID_POS 14 |
| #define | MAC_MIB_FRAG_THRESHOLD_POS 8 |
| #define | MAC_MIB_RTS_THRESHOLD_POS 10 |
| #define | MAC_MIB_SHORT_RETRY_POS 16 |
| #define | MAC_MIB_LONG_RETRY_POS 17 |
| #define | MAC_MIB_SHORT_RETRY_LIMIT_POS 16 |
| #define | MAC_MGMT_MIB_BEACON_PER_POS 0 |
| #define | MAC_MGMT_MIB_STATION_ID_POS 6 |
| #define | MAC_MGMT_MIB_CUR_PRIVACY_POS 11 |
| #define | MAC_MGMT_MIB_CUR_BSSID_POS 14 |
| #define | MAC_MGMT_MIB_PS_MODE_POS 53 |
| #define | MAC_MGMT_MIB_LISTEN_INTERVAL_POS 54 |
| #define | MAC_MGMT_MIB_MULTI_DOMAIN_IMPLEMENTED 56 |
| #define | MAC_MGMT_MIB_MULTI_DOMAIN_ENABLED 57 |
| #define | PHY_MIB_CHANNEL_POS 14 |
| #define | PHY_MIB_RATE_SET_POS 20 |
| #define | PHY_MIB_REG_DOMAIN_POS 26 |
| #define | LOCAL_MIB_AUTO_TX_RATE_POS 3 |
| #define | LOCAL_MIB_SSID_SIZE 5 |
| #define | LOCAL_MIB_TX_PROMISCUOUS_POS 6 |
| #define | LOCAL_MIB_TX_MGMT_RATE_POS 7 |
| #define | LOCAL_MIB_TX_CONTROL_RATE_POS 8 |
| #define | LOCAL_MIB_PREAMBLE_TYPE 9 |
| #define | MAC_ADDR_MIB_MAC_ADDR_POS 0 |
| #define | CMD_Set_MIB_Vars 0x01 |
| #define | CMD_Get_MIB_Vars 0x02 |
| #define | CMD_Scan 0x03 |
| #define | CMD_Join 0x04 |
| #define | CMD_Start 0x05 |
| #define | CMD_EnableRadio 0x06 |
| #define | CMD_DisableRadio 0x07 |
| #define | CMD_SiteSurvey 0x0B |
| #define | CMD_STATUS_IDLE 0x00 |
| #define | CMD_STATUS_COMPLETE 0x01 |
| #define | CMD_STATUS_UNKNOWN 0x02 |
| #define | CMD_STATUS_INVALID_PARAMETER 0x03 |
| #define | CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04 |
| #define | CMD_STATUS_TIME_OUT 0x07 |
| #define | CMD_STATUS_IN_PROGRESS 0x08 |
| #define | CMD_STATUS_REJECTED_RADIO_OFF 0x09 |
| #define | CMD_STATUS_HOST_ERROR 0xFF |
| #define | CMD_STATUS_BUSY 0xFE |
| #define | CMD_BLOCK_COMMAND_OFFSET 0 |
| #define | CMD_BLOCK_STATUS_OFFSET 1 |
| #define | CMD_BLOCK_PARAMETERS_OFFSET 4 |
| #define | SCAN_OPTIONS_SITE_SURVEY 0x80 |
| #define | MGMT_FRAME_BODY_OFFSET 24 |
| #define | MAX_AUTHENTICATION_RETRIES 3 |
| #define | MAX_ASSOCIATION_RETRIES 3 |
| #define | AUTHENTICATION_RESPONSE_TIME_OUT 1000 |
| #define | MAX_WIRELESS_BODY 2316 /* mtu is 2312, CRC is 4 */ |
| #define | LOOP_RETRY_LIMIT 500000 |
| #define | ACTIVE_MODE 1 |
| #define | PS_MODE 2 |
| #define | MAX_ENCRYPTION_KEYS 4 |
| #define | MAX_ENCRYPTION_KEY_SIZE 40 |
| #define | REG_DOMAIN_FCC 0x10 /* Channels 1-11 USA */ |
| #define | REG_DOMAIN_DOC 0x20 /* Channel 1-11 Canada */ |
| #define | REG_DOMAIN_ETSI 0x30 /* Channel 1-13 Europe (ex Spain/France) */ |
| #define | REG_DOMAIN_SPAIN 0x31 /* Channel 10-11 Spain */ |
| #define | REG_DOMAIN_FRANCE 0x32 /* Channel 10-13 France */ |
| #define | REG_DOMAIN_MKK 0x40 /* Channel 14 Japan */ |
| #define | REG_DOMAIN_MKK1 0x41 /* Channel 1-14 Japan(MKK1) */ |
| #define | REG_DOMAIN_ISRAEL 0x50 /* Channel 3-9 ISRAEL */ |
| #define | BSS_TYPE_AD_HOC 1 |
| #define | BSS_TYPE_INFRASTRUCTURE 2 |
| #define | SCAN_TYPE_ACTIVE 0 |
| #define | SCAN_TYPE_PASSIVE 1 |
| #define | LONG_PREAMBLE 0 |
| #define | SHORT_PREAMBLE 1 |
| #define | AUTO_PREAMBLE 2 |
| #define | DATA_FRAME_WS_HEADER_SIZE 30 |
| #define | PROM_MODE_OFF 0x0 |
| #define | PROM_MODE_UNKNOWN 0x1 |
| #define | PROM_MODE_CRC_FAILED 0x2 |
| #define | PROM_MODE_DUPLICATED 0x4 |
| #define | PROM_MODE_MGMT 0x8 |
| #define | PROM_MODE_CTRL 0x10 |
| #define | PROM_MODE_BAD_PROTOCOL 0x20 |
| #define | IFACE_INT_STATUS_OFFSET 0 |
| #define | IFACE_INT_MASK_OFFSET 1 |
| #define | IFACE_LOCKOUT_HOST_OFFSET 2 |
| #define | IFACE_LOCKOUT_MAC_OFFSET 3 |
| #define | IFACE_FUNC_CTRL_OFFSET 28 |
| #define | IFACE_MAC_STAT_OFFSET 30 |
| #define | IFACE_GENERIC_INT_TYPE_OFFSET 32 |
| #define | CIPHER_SUITE_NONE 0 |
| #define | CIPHER_SUITE_WEP_64 1 |
| #define | CIPHER_SUITE_TKIP 2 |
| #define | CIPHER_SUITE_AES 3 |
| #define | CIPHER_SUITE_CCX 4 |
| #define | CIPHER_SUITE_WEP_128 5 |
| #define | FUNC_CTRL_TxENABLE 0x10 |
| #define | FUNC_CTRL_RxENABLE 0x20 |
| #define | FUNC_CTRL_INIT_COMPLETE 0x01 |
| #define | ATMELFWL SIOCIWFIRSTPRIV |
| #define | ATMELIDIFC ATMELFWL + 1 |
| #define | ATMELRD ATMELFWL + 2 |
| #define | ATMELMAGIC 0x51807 |
| #define | REGDOMAINSZ 20 |
Typedefs | |
| typedef struct atmel_priv_ioctl | atmel_priv_ioctl |
Functions | |
| MODULE_AUTHOR ("Simon Kelley") | |
| MODULE_DESCRIPTION ("Support for Atmel at76c50x 802.11 wireless ethernet cards.") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_SUPPORTED_DEVICE ("Atmel at76c50x wireless cards") | |
| module_param (firmware, charp, 0) | |
| MODULE_FIRMWARE ("atmel_at76c502-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502d-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502d.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502e-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502e.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502_3com-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c502_3com.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504_2958-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504_2958.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504a_2958-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c504a_2958.bin") | |
| MODULE_FIRMWARE ("atmel_at76c506-wpa.bin") | |
| MODULE_FIRMWARE ("atmel_at76c506.bin") | |
| int | atmel_open (struct net_device *dev) |
| EXPORT_SYMBOL (atmel_open) | |
| struct net_device * | init_atmel_card (unsigned short irq, unsigned long port, const AtmelFWType fw_type, struct device *sys_dev, int(*card_present)(void *), void *card) |
| EXPORT_SYMBOL (init_atmel_card) | |
| void | stop_atmel_card (struct net_device *dev) |
| EXPORT_SYMBOL (stop_atmel_card) | |
| #define ATMELFWL SIOCIWFIRSTPRIV |
| #define BSR 0x02 /* (SIR1) Bank Switching Select Register */ |
| #define BSS_IRAM 0x0100 /* AMBA module selection --> IRAM */ |
| #define BSS_SRAM 0x0200 /* AMBA module selection --> SRAM */ |
| #define GCR 0x00 /* (SIR0) General Configuration Register */ |
| #define GCR_CORES 0x0060 /* Core Reset (ARM and PAI are reset) */ |
| #define GCR_SWRES 0x0080 /* BIU reset (ARM and PAI are NOT reset) */ |
| #define MAC_BOOT_COMPLETE 0x0010 /* MAC boot has been completed */ |
| #define MAC_INIT_COMPLETE 0x0001 /* MAC init has been completed */ |
| #define MAC_INIT_OK 0x0002 /* MAC boot has been completed */ |
| #define REG_DOMAIN_ETSI 0x30 /* Channel 1-13 Europe (ex Spain/France) */ |
| typedef struct atmel_priv_ioctl atmel_priv_ioctl |
| int atmel_open | ( | struct net_device * | dev | ) |
| EXPORT_SYMBOL | ( | atmel_open | ) |
| EXPORT_SYMBOL | ( | init_atmel_card | ) |
| EXPORT_SYMBOL | ( | stop_atmel_card | ) |
| MODULE_AUTHOR | ( | "Simon Kelley" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502d-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502d.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502e-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502e.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502_3com-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c502_3com.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504_2958-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504_2958.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504a_2958-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c504a_2958.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c506-wpa.bin" | ) |
| MODULE_FIRMWARE | ( | "atmel_at76c506.bin" | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_param | ( | firmware | , |
| charp | , | ||
| 0 | |||
| ) |
| MODULE_SUPPORTED_DEVICE | ( | "Atmel at76c50x wireless cards" | ) |
| void stop_atmel_card | ( | struct net_device * | dev | ) |
| AtmelFWType fw_type |
1.8.2