#include <linux/mdio.h>
#include "ixgb_osdep.h"

Data Structures
struct	ixgb_rx_desc

struct	ixgb_tx_desc

struct	ixgb_context_desc

struct	ixgb_flash_buffer

struct	ixgb_fc

struct	ixgb_bus

struct	ixgb_hw

struct	ixgb_hw_stats

Macros
#define	IXGB_EEPROM_SIZE 64 /* Size in words */

#define	SPEED_10000 10000

#define	FULL_DUPLEX 2

#define	MIN_NUMBER_OF_DESCRIPTORS 8

#define	MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */

#define	IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */

#define	IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */

#define	IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */

#define	IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */

#define	MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */

#define	IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */

#define	IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */

#define	IXGB_STATUS 0x00010 /* Device Status Register - RO */

#define	IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */

#define	IXGB_MFS 0x00020 /* Maximum Frame Size - RW */

#define	IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */

#define	IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */

#define	IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */

#define	IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */

#define	IXGB_RCTL 0x00100 /* RX Control - RW */

#define	IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */

#define	IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */

#define	IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */

#define	IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */

#define	IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */

#define	IXGB_RDH 0x00128 /* RX Descriptor Head - RW */

#define	IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */

#define	IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */

#define	IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */

#define	IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */

#define	IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */

#define	IXGB_RA 0x00180 /* Receive Address Array Base - RW */

#define	IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */

#define	IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */

#define	IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */

#define	IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */

#define	IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8

#define	IXGB_TCTL 0x00600 /* TX Control - RW */

#define	IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */

#define	IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */

#define	IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */

#define	IXGB_TDH 0x00618 /* TX Descriptor Head - RW */

#define	IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */

#define	IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */

#define	IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */

#define	IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */

#define	IXGB_PAP 0x00640 /* Pause and Pace - RW */

#define	IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8

#define	IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */

#define	IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */

#define	IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */

#define	IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */

#define	IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */

#define	IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */

#define	IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */

#define	IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */

#define	IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */

#define	IXGB_ARD 0x00748 /* Autoscan Read Data - RO */

#define	IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */

#define	IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */

#define	IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */

#define	IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */

#define	IXGB_WUS 0x00810 /* Wake Up Status - RO */

#define	IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */

#define	IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */

#define	IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */

#define	IXGB_TPRL 0x02000 /* Total Packets Received (Low) */

#define	IXGB_TPRH 0x02004 /* Total Packets Received (High) */

#define	IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */

#define	IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */

#define	IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */

#define	IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */

#define	IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */

#define	IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */

#define	IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */

#define	IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */

#define	IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */

#define	IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */

#define	IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */

#define	IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */

#define	IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */

#define	IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */

#define	IXGB_TORL 0x02040 /* Total Octets Received (Low) */

#define	IXGB_TORH 0x02044 /* Total Octets Received (High) */

#define	IXGB_RNBC 0x02048 /* Receive No Buffers Count */

#define	IXGB_RUC 0x02050 /* Receive Undersize Count */

#define	IXGB_ROC 0x02058 /* Receive Oversize Count */

#define	IXGB_RLEC 0x02060 /* Receive Length Error Count */

#define	IXGB_CRCERRS 0x02068 /* CRC Error Count */

#define	IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */

#define	IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */

#define	IXGB_MPC 0x02080 /* Missed Packets Count */

#define	IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */

#define	IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */

#define	IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */

#define	IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */

#define	IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */

#define	IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */

#define	IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */

#define	IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */

#define	IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */

#define	IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */

#define	IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */

#define	IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */

#define	IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */

#define	IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */

#define	IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */

#define	IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */

#define	IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */

#define	IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */

#define	IXGB_DC 0x02148 /* Defer Count */

#define	IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */

#define	IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */

#define	IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */

#define	IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */

#define	IXGB_RFC 0x02188 /* Remote Fault Count */

#define	IXGB_LFC 0x02190 /* Local Fault Count */

#define	IXGB_PFRC 0x02198 /* Pause Frame Receive Count */

#define	IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */

#define	IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */

#define	IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */

#define	IXGB_XONRXC 0x021B8 /* XON Received Count */

#define	IXGB_XONTXC 0x021C0 /* XON Transmitted Count */

#define	IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */

#define	IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */

#define	IXGB_RJC 0x021D8 /* Receive Jabber Count */

#define	IXGB_CTRL0_LRST 0x00000008

#define	IXGB_CTRL0_JFE 0x00000010

#define	IXGB_CTRL0_XLE 0x00000020

#define	IXGB_CTRL0_MDCS 0x00000040

#define	IXGB_CTRL0_CMDC 0x00000080

#define	IXGB_CTRL0_SDP0 0x00040000

#define	IXGB_CTRL0_SDP1 0x00080000

#define	IXGB_CTRL0_SDP2 0x00100000

#define	IXGB_CTRL0_SDP3 0x00200000

#define	IXGB_CTRL0_SDP0_DIR 0x00400000

#define	IXGB_CTRL0_SDP1_DIR 0x00800000

#define	IXGB_CTRL0_SDP2_DIR 0x01000000

#define	IXGB_CTRL0_SDP3_DIR 0x02000000

#define	IXGB_CTRL0_RST 0x04000000

#define	IXGB_CTRL0_RPE 0x08000000

#define	IXGB_CTRL0_TPE 0x10000000

#define	IXGB_CTRL0_VME 0x40000000

#define	IXGB_CTRL1_GPI0_EN 0x00000001

#define	IXGB_CTRL1_GPI1_EN 0x00000002

#define	IXGB_CTRL1_GPI2_EN 0x00000004

#define	IXGB_CTRL1_GPI3_EN 0x00000008

#define	IXGB_CTRL1_SDP4 0x00000010

#define	IXGB_CTRL1_SDP5 0x00000020

#define	IXGB_CTRL1_SDP6 0x00000040

#define	IXGB_CTRL1_SDP7 0x00000080

#define	IXGB_CTRL1_SDP4_DIR 0x00000100

#define	IXGB_CTRL1_SDP5_DIR 0x00000200

#define	IXGB_CTRL1_SDP6_DIR 0x00000400

#define	IXGB_CTRL1_SDP7_DIR 0x00000800

#define	IXGB_CTRL1_EE_RST 0x00002000

#define	IXGB_CTRL1_RO_DIS 0x00020000

#define	IXGB_CTRL1_PCIXHM_MASK 0x00C00000

#define	IXGB_CTRL1_PCIXHM_1_2 0x00000000

#define	IXGB_CTRL1_PCIXHM_5_8 0x00400000

#define	IXGB_CTRL1_PCIXHM_3_4 0x00800000

#define	IXGB_CTRL1_PCIXHM_7_8 0x00C00000

#define	IXGB_STATUS_LU 0x00000002

#define	IXGB_STATUS_AIP 0x00000004

#define	IXGB_STATUS_TXOFF 0x00000010

#define	IXGB_STATUS_XAUIME 0x00000020

#define	IXGB_STATUS_RES 0x00000040

#define	IXGB_STATUS_RIS 0x00000080

#define	IXGB_STATUS_RIE 0x00000100

#define	IXGB_STATUS_RLF 0x00000200

#define	IXGB_STATUS_RRF 0x00000400

#define	IXGB_STATUS_PCI_SPD 0x00000800

#define	IXGB_STATUS_BUS64 0x00001000

#define	IXGB_STATUS_PCIX_MODE 0x00002000

#define	IXGB_STATUS_PCIX_SPD_MASK 0x0000C000

#define	IXGB_STATUS_PCIX_SPD_66 0x00000000

#define	IXGB_STATUS_PCIX_SPD_100 0x00004000

#define	IXGB_STATUS_PCIX_SPD_133 0x00008000

#define	IXGB_STATUS_REV_ID_MASK 0x000F0000

#define	IXGB_STATUS_REV_ID_SHIFT 16

#define	IXGB_EECD_SK 0x00000001

#define	IXGB_EECD_CS 0x00000002

#define	IXGB_EECD_DI 0x00000004

#define	IXGB_EECD_DO 0x00000008

#define	IXGB_EECD_FWE_MASK 0x00000030

#define	IXGB_EECD_FWE_DIS 0x00000010

#define	IXGB_EECD_FWE_EN 0x00000020

#define	IXGB_MFS_SHIFT 16

#define	IXGB_INT_TXDW 0x00000001

#define	IXGB_INT_TXQE 0x00000002

#define	IXGB_INT_LSC 0x00000004

#define	IXGB_INT_RXSEQ 0x00000008

#define	IXGB_INT_RXDMT0 0x00000010

#define	IXGB_INT_RXO 0x00000040

#define	IXGB_INT_RXT0 0x00000080

#define	IXGB_INT_AUTOSCAN 0x00000200

#define	IXGB_INT_GPI0 0x00000800

#define	IXGB_INT_GPI1 0x00001000

#define	IXGB_INT_GPI2 0x00002000

#define	IXGB_INT_GPI3 0x00004000

#define	IXGB_RCTL_RXEN 0x00000002

#define	IXGB_RCTL_SBP 0x00000004

#define	IXGB_RCTL_UPE 0x00000008

#define	IXGB_RCTL_MPE 0x00000010

#define	IXGB_RCTL_RDMTS_MASK 0x00000300

#define	IXGB_RCTL_RDMTS_1_2 0x00000000

#define	IXGB_RCTL_RDMTS_1_4 0x00000100

#define	IXGB_RCTL_RDMTS_1_8 0x00000200

#define	IXGB_RCTL_MO_MASK 0x00003000

#define	IXGB_RCTL_MO_47_36 0x00000000

#define	IXGB_RCTL_MO_46_35 0x00001000

#define	IXGB_RCTL_MO_45_34 0x00002000

#define	IXGB_RCTL_MO_43_32 0x00003000

#define	IXGB_RCTL_MO_SHIFT 12

#define	IXGB_RCTL_BAM 0x00008000

#define	IXGB_RCTL_BSIZE_MASK 0x00030000

#define	IXGB_RCTL_BSIZE_2048 0x00000000

#define	IXGB_RCTL_BSIZE_4096 0x00010000

#define	IXGB_RCTL_BSIZE_8192 0x00020000

#define	IXGB_RCTL_BSIZE_16384 0x00030000

#define	IXGB_RCTL_VFE 0x00040000

#define	IXGB_RCTL_CFIEN 0x00080000

#define	IXGB_RCTL_CFI 0x00100000

#define	IXGB_RCTL_RPDA_MASK 0x00600000

#define	IXGB_RCTL_RPDA_MC_MAC 0x00000000

#define	IXGB_RCTL_MC_ONLY 0x00400000

#define	IXGB_RCTL_CFF 0x00800000

#define	IXGB_RCTL_SECRC 0x04000000

#define	IXGB_RDT_FPDB 0x80000000

#define	IXGB_RCTL_IDLE_RX_UNIT 0

#define	IXGB_FCRTL_XONE 0x80000000

#define	IXGB_RXDCTL_PTHRESH_MASK 0x000001FF

#define	IXGB_RXDCTL_PTHRESH_SHIFT 0

#define	IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00

#define	IXGB_RXDCTL_HTHRESH_SHIFT 9

#define	IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000

#define	IXGB_RXDCTL_WTHRESH_SHIFT 18

#define	IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F

#define	IXGB_RAIDC_DELAY_MASK 0x000FF800

#define	IXGB_RAIDC_DELAY_SHIFT 11

#define	IXGB_RAIDC_POLL_MASK 0x1FF00000

#define	IXGB_RAIDC_POLL_SHIFT 20

#define	IXGB_RAIDC_RXT_GATE 0x40000000

#define	IXGB_RAIDC_EN 0x80000000

#define	IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220

#define	IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244

#define	IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122

#define	IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61

#define	IXGB_RXCSUM_IPOFL 0x00000100

#define	IXGB_RXCSUM_TUOFL 0x00000200

#define	IXGB_RAH_ASEL_MASK 0x00030000

#define	IXGB_RAH_ASEL_DEST 0x00000000

#define	IXGB_RAH_ASEL_SRC 0x00010000

#define	IXGB_RAH_AV 0x80000000

#define	IXGB_TCTL_TCE 0x00000001

#define	IXGB_TCTL_TXEN 0x00000002

#define	IXGB_TCTL_TPDE 0x00000004

#define	IXGB_TCTL_IDLE_TX_UNIT 0

#define	IXGB_TXDCTL_PTHRESH_MASK 0x0000007F

#define	IXGB_TXDCTL_HTHRESH_MASK 0x00007F00

#define	IXGB_TXDCTL_HTHRESH_SHIFT 8

#define	IXGB_TXDCTL_WTHRESH_MASK 0x007F0000

#define	IXGB_TXDCTL_WTHRESH_SHIFT 16

#define	IXGB_TSPMT_TSMT_MASK 0x0000FFFF

#define	IXGB_TSPMT_TSPBP_MASK 0xFFFF0000

#define	IXGB_TSPMT_TSPBP_SHIFT 16

#define	IXGB_PAP_TXPC_MASK 0x0000FFFF

#define	IXGB_PAP_TXPV_MASK 0x000F0000

#define	IXGB_PAP_TXPV_10G 0x00000000

#define	IXGB_PAP_TXPV_1G 0x00010000

#define	IXGB_PAP_TXPV_2G 0x00020000

#define	IXGB_PAP_TXPV_3G 0x00030000

#define	IXGB_PAP_TXPV_4G 0x00040000

#define	IXGB_PAP_TXPV_5G 0x00050000

#define	IXGB_PAP_TXPV_6G 0x00060000

#define	IXGB_PAP_TXPV_7G 0x00070000

#define	IXGB_PAP_TXPV_8G 0x00080000

#define	IXGB_PAP_TXPV_9G 0x00090000

#define	IXGB_PAP_TXPV_WAN 0x000F0000

#define	IXGB_PCSC1_LOOPBACK 0x00004000

#define	IXGB_PCSC2_PCS_TYPE_MASK 0x00000003

#define	IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001

#define	IXGB_PCSS1_LOCAL_FAULT 0x00000080

#define	IXGB_PCSS1_RX_LINK_STATUS 0x00000004

#define	IXGB_PCSS2_DEV_PRES_MASK 0x0000C000

#define	IXGB_PCSS2_DEV_PRES 0x00004000

#define	IXGB_PCSS2_TX_LF 0x00000800

#define	IXGB_PCSS2_RX_LF 0x00000400

#define	IXGB_PCSS2_10GBW 0x00000004

#define	IXGB_PCSS2_10GBX 0x00000002

#define	IXGB_PCSS2_10GBR 0x00000001

#define	IXGB_XPCSS_ALIGN_STATUS 0x00001000

#define	IXGB_XPCSS_PATTERN_TEST 0x00000800

#define	IXGB_XPCSS_LANE_3_SYNC 0x00000008

#define	IXGB_XPCSS_LANE_2_SYNC 0x00000004

#define	IXGB_XPCSS_LANE_1_SYNC 0x00000002

#define	IXGB_XPCSS_LANE_0_SYNC 0x00000001

#define	IXGB_XPCSTC_BERT_TRIG 0x00200000

#define	IXGB_XPCSTC_BERT_SST 0x00100000

#define	IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000

#define	IXGB_XPCSTC_BERT_PSZ_SHIFT 17

#define	IXGB_XPCSTC_BERT_PSZ_INF 0x00000003

#define	IXGB_XPCSTC_BERT_PSZ_68 0x00000001

#define	IXGB_XPCSTC_BERT_PSZ_1028 0x00000000

#define	IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF

#define	IXGB_MSCA_NP_ADDR_SHIFT 0

#define	IXGB_MSCA_DEV_TYPE_MASK 0x001F0000

#define	IXGB_MSCA_DEV_TYPE_SHIFT 16

#define	IXGB_MSCA_PHY_ADDR_MASK 0x03E00000

#define	IXGB_MSCA_PHY_ADDR_SHIFT 21

#define	IXGB_MSCA_OP_CODE_MASK 0x0C000000

#define	IXGB_MSCA_ADDR_CYCLE 0x00000000

#define	IXGB_MSCA_WRITE 0x04000000

#define	IXGB_MSCA_READ 0x08000000

#define	IXGB_MSCA_READ_AUTOINC 0x0C000000

#define	IXGB_MSCA_OP_CODE_SHIFT 26

#define	IXGB_MSCA_ST_CODE_MASK 0x30000000

#define	IXGB_MSCA_NEW_PROTOCOL 0x00000000

#define	IXGB_MSCA_OLD_PROTOCOL 0x10000000

#define	IXGB_MSCA_ST_CODE_SHIFT 28

#define	IXGB_MSCA_MDI_COMMAND 0x40000000

#define	IXGB_MSCA_MDI_IN_PROG_EN 0x80000000

#define	IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF

#define	IXGB_MSRWD_WRITE_DATA_SHIFT 0

#define	IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000

#define	IXGB_MSRWD_READ_DATA_SHIFT 16

#define	IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */

#define	MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */

#define	G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */

#define	G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */

#define	G6XXX_PMA_PMD_VS1_PLL_RESET 0x80

#define	G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00

#define	G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */

#define	IXGB_RX_DESC_STATUS_DD 0x01

#define	IXGB_RX_DESC_STATUS_EOP 0x02

#define	IXGB_RX_DESC_STATUS_IXSM 0x04

#define	IXGB_RX_DESC_STATUS_VP 0x08

#define	IXGB_RX_DESC_STATUS_TCPCS 0x20

#define	IXGB_RX_DESC_STATUS_IPCS 0x40

#define	IXGB_RX_DESC_STATUS_PIF 0x80

#define	IXGB_RX_DESC_ERRORS_CE 0x01

#define	IXGB_RX_DESC_ERRORS_SE 0x02

#define	IXGB_RX_DESC_ERRORS_P 0x08

#define	IXGB_RX_DESC_ERRORS_TCPE 0x20

#define	IXGB_RX_DESC_ERRORS_IPE 0x40

#define	IXGB_RX_DESC_ERRORS_RXE 0x80

#define	IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */

#define	IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */

#define	IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */

#define	IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF

#define	IXGB_TX_DESC_TYPE_MASK 0x00F00000

#define	IXGB_TX_DESC_TYPE_SHIFT 20

#define	IXGB_TX_DESC_CMD_MASK 0xFF000000

#define	IXGB_TX_DESC_CMD_SHIFT 24

#define	IXGB_TX_DESC_CMD_EOP 0x01000000

#define	IXGB_TX_DESC_CMD_TSE 0x04000000

#define	IXGB_TX_DESC_CMD_RS 0x08000000

#define	IXGB_TX_DESC_CMD_VLE 0x40000000

#define	IXGB_TX_DESC_CMD_IDE 0x80000000

#define	IXGB_TX_DESC_TYPE 0x00100000

#define	IXGB_TX_DESC_STATUS_DD 0x01

#define	IXGB_TX_DESC_POPTS_IXSM 0x01

#define	IXGB_TX_DESC_POPTS_TXSM 0x02

#define	IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */

#define	IXGB_CONTEXT_DESC_CMD_TCP 0x01000000

#define	IXGB_CONTEXT_DESC_CMD_IP 0x02000000

#define	IXGB_CONTEXT_DESC_CMD_TSE 0x04000000

#define	IXGB_CONTEXT_DESC_CMD_RS 0x08000000

#define	IXGB_CONTEXT_DESC_CMD_IDE 0x80000000

#define	IXGB_CONTEXT_DESC_TYPE 0x00000000

#define	IXGB_CONTEXT_DESC_STATUS_DD 0x01

#define	IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */

#define	IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */

#define	IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */

#define	IXGB_MEMORY_REGISTER_BASE_ADDRESS 0

#define	ENET_HEADER_SIZE 14

#define	ENET_FCS_LENGTH 4

#define	IXGB_MAX_NUM_MULTICAST_ADDRESSES 128

#define	IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60

#define	IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514

#define	IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00

#define	IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */

#define	IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */

#define	IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */

#define	FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */

#define	FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */

#define	FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */

#define	IXGB_MAX_PHY_REG_ADDRESS 0xFFFF

#define	IXGB_MAX_PHY_ADDRESS 31

#define	IXGB_MAX_PHY_DEV_TYPE 31

Enumerations
enum	ixgb_mac_type { ixgb_mac_unknown = 0, ixgb_82597, ixgb_num_macs }

enum	ixgb_phy_type { ixgb_phy_type_unknown = 0, ixgb_phy_type_g6005, ixgb_phy_type_g6104, ixgb_phy_type_txn17201, ixgb_phy_type_txn17401, ixgb_phy_type_bcm }

enum	ixgb_xpak_vendor { ixgb_xpak_vendor_intel, ixgb_xpak_vendor_infineon }

enum	ixgb_media_type { ixgb_media_type_unknown = 0, ixgb_media_type_fiber = 1, ixgb_media_type_copper = 2, ixgb_num_media_types }

enum	ixgb_fc_type { ixgb_fc_none = 0, ixgb_fc_rx_pause = 1, ixgb_fc_tx_pause = 2, ixgb_fc_full = 3, ixgb_fc_default = 0xFF }

enum	ixgb_bus_type { ixgb_bus_type_unknown = 0, ixgb_bus_type_pci, ixgb_bus_type_pcix }

enum	ixgb_bus_speed { ixgb_bus_speed_unknown = 0, ixgb_bus_speed_33, ixgb_bus_speed_66, ixgb_bus_speed_100, ixgb_bus_speed_133, ixgb_bus_speed_reserved }

enum	ixgb_bus_width { ixgb_bus_width_unknown = 0, ixgb_bus_width_32, ixgb_bus_width_64 }

Functions
bool	ixgb_adapter_stop (struct ixgb_hw *hw)

bool	ixgb_init_hw (struct ixgb_hw *hw)

bool	ixgb_adapter_start (struct ixgb_hw *hw)

void	ixgb_check_for_link (struct ixgb_hw *hw)

bool	ixgb_check_for_bad_link (struct ixgb_hw *hw)

void	ixgb_rar_set (struct ixgb_hw hw, u8 addr, u32 index)

void	ixgb_mc_addr_list_update (struct ixgb_hw hw, u8 mc_addr_list, u32 mc_addr_count, u32 pad)

void	ixgb_write_vfta (struct ixgb_hw *hw, u32 offset, u32 value)

void	ixgb_get_ee_mac_addr (struct ixgb_hw hw, u8 mac_addr)

u32	ixgb_get_ee_pba_number (struct ixgb_hw *hw)

u16	ixgb_get_ee_device_id (struct ixgb_hw *hw)

bool	ixgb_get_eeprom_data (struct ixgb_hw *hw)

__le16	ixgb_get_eeprom_word (struct ixgb_hw *hw, u16 index)

void	ixgb_led_on (struct ixgb_hw *hw)

void	ixgb_led_off (struct ixgb_hw *hw)

void	ixgb_write_pci_cfg (struct ixgb_hw hw, u32 reg, u16 value)

Macro Definition Documentation

#define ENET_FCS_LENGTH 4

Definition at line 615 of file ixgb_hw.h.

#define ENET_HEADER_SIZE 14

Definition at line 614 of file ixgb_hw.h.

#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */

Definition at line 647 of file ixgb_hw.h.

#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */

Definition at line 648 of file ixgb_hw.h.

#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */

Definition at line 649 of file ixgb_hw.h.

#define FULL_DUPLEX 2

Definition at line 103 of file ixgb_hw.h.

#define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */

Definition at line 513 of file ixgb_hw.h.

#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80

Definition at line 516 of file ixgb_hw.h.

#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00

Definition at line 517 of file ixgb_hw.h.

#define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */

Definition at line 514 of file ixgb_hw.h.

#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */

Definition at line 518 of file ixgb_hw.h.

#define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */

Definition at line 173 of file ixgb_hw.h.

#define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */

Definition at line 171 of file ixgb_hw.h.

#define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */

Definition at line 172 of file ixgb_hw.h.

#define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */

Definition at line 190 of file ixgb_hw.h.

#define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */

Definition at line 189 of file ixgb_hw.h.

#define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */

Definition at line 216 of file ixgb_hw.h.

#define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */

Definition at line 215 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000

Definition at line 602 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_CMD_IP 0x02000000

Definition at line 599 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_CMD_RS 0x08000000

Definition at line 601 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000

Definition at line 598 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000

Definition at line 600 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_STATUS_DD 0x01

Definition at line 606 of file ixgb_hw.h.

#define IXGB_CONTEXT_DESC_TYPE 0x00000000

Definition at line 604 of file ixgb_hw.h.

#define IXGB_CRCERRS 0x02068 /* CRC Error Count */

Definition at line 207 of file ixgb_hw.h.

#define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */

Definition at line 117 of file ixgb_hw.h.

#define IXGB_CTRL0_CMDC 0x00000080

Definition at line 251 of file ixgb_hw.h.

#define IXGB_CTRL0_JFE 0x00000010

Definition at line 248 of file ixgb_hw.h.

#define IXGB_CTRL0_LRST 0x00000008

Definition at line 247 of file ixgb_hw.h.

#define IXGB_CTRL0_MDCS 0x00000040

Definition at line 250 of file ixgb_hw.h.

#define IXGB_CTRL0_RPE 0x08000000

Definition at line 261 of file ixgb_hw.h.

#define IXGB_CTRL0_RST 0x04000000

Definition at line 260 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP0 0x00040000

Definition at line 252 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP0_DIR 0x00400000

Definition at line 256 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP1 0x00080000

Definition at line 253 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP1_DIR 0x00800000

Definition at line 257 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP2 0x00100000

Definition at line 254 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP2_DIR 0x01000000

Definition at line 258 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP3 0x00200000

Definition at line 255 of file ixgb_hw.h.

#define IXGB_CTRL0_SDP3_DIR 0x02000000

Definition at line 259 of file ixgb_hw.h.

#define IXGB_CTRL0_TPE 0x10000000

Definition at line 262 of file ixgb_hw.h.

#define IXGB_CTRL0_VME 0x40000000

Definition at line 263 of file ixgb_hw.h.

#define IXGB_CTRL0_XLE 0x00000020

Definition at line 249 of file ixgb_hw.h.

#define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */

Definition at line 118 of file ixgb_hw.h.

#define IXGB_CTRL1_EE_RST 0x00002000

Definition at line 278 of file ixgb_hw.h.

#define IXGB_CTRL1_GPI0_EN 0x00000001

Definition at line 266 of file ixgb_hw.h.

#define IXGB_CTRL1_GPI1_EN 0x00000002

Definition at line 267 of file ixgb_hw.h.

#define IXGB_CTRL1_GPI2_EN 0x00000004

Definition at line 268 of file ixgb_hw.h.

#define IXGB_CTRL1_GPI3_EN 0x00000008

Definition at line 269 of file ixgb_hw.h.

#define IXGB_CTRL1_PCIXHM_1_2 0x00000000

Definition at line 281 of file ixgb_hw.h.

#define IXGB_CTRL1_PCIXHM_3_4 0x00800000

Definition at line 283 of file ixgb_hw.h.

#define IXGB_CTRL1_PCIXHM_5_8 0x00400000

Definition at line 282 of file ixgb_hw.h.

#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000

Definition at line 284 of file ixgb_hw.h.

#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000

Definition at line 280 of file ixgb_hw.h.

#define IXGB_CTRL1_RO_DIS 0x00020000

Definition at line 279 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP4 0x00000010

Definition at line 270 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP4_DIR 0x00000100

Definition at line 274 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP5 0x00000020

Definition at line 271 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP5_DIR 0x00000200

Definition at line 275 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP6 0x00000040

Definition at line 272 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP6_DIR 0x00000400

Definition at line 276 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP7 0x00000080

Definition at line 273 of file ixgb_hw.h.

#define IXGB_CTRL1_SDP7_DIR 0x00000800

Definition at line 277 of file ixgb_hw.h.

#define IXGB_DC 0x02148 /* Defer Count */

Definition at line 229 of file ixgb_hw.h.

#define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */

Definition at line 110 of file ixgb_hw.h.

#define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */

Definition at line 109 of file ixgb_hw.h.

#define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */

Definition at line 108 of file ixgb_hw.h.

#define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */

Definition at line 112 of file ixgb_hw.h.

#define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */

Definition at line 624 of file ixgb_hw.h.

#define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */

Definition at line 209 of file ixgb_hw.h.

#define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */

Definition at line 120 of file ixgb_hw.h.

#define IXGB_EECD_CS 0x00000002

Definition at line 308 of file ixgb_hw.h.

#define IXGB_EECD_DI 0x00000004

Definition at line 309 of file ixgb_hw.h.

#define IXGB_EECD_DO 0x00000008

Definition at line 310 of file ixgb_hw.h.

#define IXGB_EECD_FWE_DIS 0x00000010

Definition at line 312 of file ixgb_hw.h.

#define IXGB_EECD_FWE_EN 0x00000020

Definition at line 313 of file ixgb_hw.h.

#define IXGB_EECD_FWE_MASK 0x00000030

Definition at line 311 of file ixgb_hw.h.

#define IXGB_EECD_SK 0x00000001

Definition at line 307 of file ixgb_hw.h.

#define IXGB_EEPROM_SIZE 64 /* Size in words */

Definition at line 100 of file ixgb_hw.h.

#define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */

Definition at line 132 of file ixgb_hw.h.

#define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */

Definition at line 131 of file ixgb_hw.h.

#define IXGB_FCRTL_XONE 0x80000000

Definition at line 366 of file ixgb_hw.h.

#define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */

Definition at line 180 of file ixgb_hw.h.

#define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */

Definition at line 181 of file ixgb_hw.h.

#define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */

Definition at line 182 of file ixgb_hw.h.

#define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */

Definition at line 200 of file ixgb_hw.h.

#define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */

Definition at line 199 of file ixgb_hw.h.

#define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */

Definition at line 226 of file ixgb_hw.h.

#define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */

Definition at line 225 of file ixgb_hw.h.

#define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */

Definition at line 188 of file ixgb_hw.h.

#define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */

Definition at line 187 of file ixgb_hw.h.

#define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */

Definition at line 214 of file ixgb_hw.h.

#define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */

Definition at line 213 of file ixgb_hw.h.

#define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */

Definition at line 233 of file ixgb_hw.h.

#define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */

Definition at line 208 of file ixgb_hw.h.

#define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */

Definition at line 124 of file ixgb_hw.h.

#define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */

Definition at line 125 of file ixgb_hw.h.

#define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */

Definition at line 127 of file ixgb_hw.h.

#define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */

Definition at line 126 of file ixgb_hw.h.

#define IXGB_INT_AUTOSCAN 0x00000200

Definition at line 326 of file ixgb_hw.h.

#define IXGB_INT_GPI0 0x00000800

Definition at line 327 of file ixgb_hw.h.

#define IXGB_INT_GPI1 0x00001000

Definition at line 328 of file ixgb_hw.h.

#define IXGB_INT_GPI2 0x00002000

Definition at line 329 of file ixgb_hw.h.

#define IXGB_INT_GPI3 0x00004000

Definition at line 330 of file ixgb_hw.h.

#define IXGB_INT_LSC 0x00000004

Definition at line 321 of file ixgb_hw.h.

#define IXGB_INT_RXDMT0 0x00000010

Definition at line 323 of file ixgb_hw.h.

#define IXGB_INT_RXO 0x00000040

Definition at line 324 of file ixgb_hw.h.

#define IXGB_INT_RXSEQ 0x00000008

Definition at line 322 of file ixgb_hw.h.

#define IXGB_INT_RXT0 0x00000080

Definition at line 325 of file ixgb_hw.h.

#define IXGB_INT_TXDW 0x00000001

Definition at line 319 of file ixgb_hw.h.

#define IXGB_INT_TXQE 0x00000002

Definition at line 320 of file ixgb_hw.h.

#define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */

Definition at line 198 of file ixgb_hw.h.

#define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */

Definition at line 197 of file ixgb_hw.h.

#define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */

Definition at line 224 of file ixgb_hw.h.

#define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */

Definition at line 223 of file ixgb_hw.h.

#define IXGB_LFC 0x02190 /* Local Fault Count */

Definition at line 235 of file ixgb_hw.h.

#define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */

Definition at line 170 of file ixgb_hw.h.

#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514

Definition at line 618 of file ixgb_hw.h.

#define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00

Definition at line 619 of file ixgb_hw.h.

#define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128

Definition at line 616 of file ixgb_hw.h.

#define IXGB_MAX_PHY_ADDRESS 31

Definition at line 653 of file ixgb_hw.h.

#define IXGB_MAX_PHY_DEV_TYPE 31

Definition at line 654 of file ixgb_hw.h.

#define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF

Definition at line 652 of file ixgb_hw.h.

#define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */

Definition at line 609 of file ixgb_hw.h.

#define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */

Definition at line 238 of file ixgb_hw.h.

#define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */

Definition at line 239 of file ixgb_hw.h.

#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0

Definition at line 613 of file ixgb_hw.h.

#define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */

Definition at line 121 of file ixgb_hw.h.

#define IXGB_MFS_SHIFT 16

Definition at line 316 of file ixgb_hw.h.

#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60

Definition at line 617 of file ixgb_hw.h.

#define IXGB_MPC 0x02080 /* Missed Packets Count */

Definition at line 210 of file ixgb_hw.h.

#define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */

Definition at line 192 of file ixgb_hw.h.

#define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */

Definition at line 191 of file ixgb_hw.h.

#define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */

Definition at line 218 of file ixgb_hw.h.

#define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */

Definition at line 217 of file ixgb_hw.h.

#define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */

Definition at line 174 of file ixgb_hw.h.

#define IXGB_MSCA_ADDR_CYCLE 0x00000000

Definition at line 485 of file ixgb_hw.h.

#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000

Definition at line 476 of file ixgb_hw.h.

#define IXGB_MSCA_DEV_TYPE_SHIFT 16

Definition at line 477 of file ixgb_hw.h.

#define IXGB_MSCA_MDI_COMMAND 0x40000000

Definition at line 497 of file ixgb_hw.h.

#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000

Definition at line 499 of file ixgb_hw.h.

#define IXGB_MSCA_NEW_PROTOCOL 0x00000000

Definition at line 493 of file ixgb_hw.h.

#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF

Definition at line 473 of file ixgb_hw.h.

#define IXGB_MSCA_NP_ADDR_SHIFT 0

Definition at line 474 of file ixgb_hw.h.

#define IXGB_MSCA_OLD_PROTOCOL 0x10000000

Definition at line 494 of file ixgb_hw.h.

#define IXGB_MSCA_OP_CODE_MASK 0x0C000000

Definition at line 480 of file ixgb_hw.h.

#define IXGB_MSCA_OP_CODE_SHIFT 26

Definition at line 489 of file ixgb_hw.h.

#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000

Definition at line 478 of file ixgb_hw.h.

#define IXGB_MSCA_PHY_ADDR_SHIFT 21

Definition at line 479 of file ixgb_hw.h.

#define IXGB_MSCA_READ 0x08000000

Definition at line 487 of file ixgb_hw.h.

#define IXGB_MSCA_READ_AUTOINC 0x0C000000

Definition at line 488 of file ixgb_hw.h.

#define IXGB_MSCA_ST_CODE_MASK 0x30000000

Definition at line 490 of file ixgb_hw.h.

#define IXGB_MSCA_ST_CODE_SHIFT 28

Definition at line 495 of file ixgb_hw.h.

#define IXGB_MSCA_WRITE 0x04000000

Definition at line 486 of file ixgb_hw.h.

#define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */

Definition at line 175 of file ixgb_hw.h.

#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000

Definition at line 504 of file ixgb_hw.h.

#define IXGB_MSRWD_READ_DATA_SHIFT 16

Definition at line 505 of file ixgb_hw.h.

#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF

Definition at line 502 of file ixgb_hw.h.

#define IXGB_MSRWD_WRITE_DATA_SHIFT 0

Definition at line 503 of file ixgb_hw.h.

#define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */

Definition at line 145 of file ixgb_hw.h.

#define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */

Definition at line 622 of file ixgb_hw.h.

#define IXGB_PAP 0x00640 /* Pause and Pace - RW */

Definition at line 159 of file ixgb_hw.h.

#define IXGB_PAP_TXPC_MASK 0x0000FFFF

Definition at line 420 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_10G 0x00000000

Definition at line 422 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_1G 0x00010000

Definition at line 423 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_2G 0x00020000

Definition at line 424 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_3G 0x00030000

Definition at line 425 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_4G 0x00040000

Definition at line 426 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_5G 0x00050000

Definition at line 427 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_6G 0x00060000

Definition at line 428 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_7G 0x00070000

Definition at line 429 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_8G 0x00080000

Definition at line 430 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_9G 0x00090000

Definition at line 431 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_MASK 0x000F0000

Definition at line 421 of file ixgb_hw.h.

#define IXGB_PAP_TXPV_WAN 0x000F0000

Definition at line 432 of file ixgb_hw.h.

#define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */

Definition at line 163 of file ixgb_hw.h.

#define IXGB_PCSC1_LOOPBACK 0x00004000

Definition at line 435 of file ixgb_hw.h.

#define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */

Definition at line 164 of file ixgb_hw.h.

#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001

Definition at line 439 of file ixgb_hw.h.

#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003

Definition at line 438 of file ixgb_hw.h.

#define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */

Definition at line 165 of file ixgb_hw.h.

#define IXGB_PCSS1_LOCAL_FAULT 0x00000080

Definition at line 442 of file ixgb_hw.h.

#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004

Definition at line 443 of file ixgb_hw.h.

#define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */

Definition at line 166 of file ixgb_hw.h.

#define IXGB_PCSS2_10GBR 0x00000001

Definition at line 452 of file ixgb_hw.h.

#define IXGB_PCSS2_10GBW 0x00000004

Definition at line 450 of file ixgb_hw.h.

#define IXGB_PCSS2_10GBX 0x00000002

Definition at line 451 of file ixgb_hw.h.

#define IXGB_PCSS2_DEV_PRES 0x00004000

Definition at line 447 of file ixgb_hw.h.

#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000

Definition at line 446 of file ixgb_hw.h.

#define IXGB_PCSS2_RX_LF 0x00000400

Definition at line 449 of file ixgb_hw.h.

#define IXGB_PCSS2_TX_LF 0x00000800

Definition at line 448 of file ixgb_hw.h.

#define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */

Definition at line 236 of file ixgb_hw.h.

#define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */

Definition at line 237 of file ixgb_hw.h.

#define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */

Definition at line 508 of file ixgb_hw.h.

#define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */

Definition at line 230 of file ixgb_hw.h.

#define IXGB_RA 0x00180 /* Receive Address Array Base - RW */

Definition at line 142 of file ixgb_hw.h.

#define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */

Definition at line 144 of file ixgb_hw.h.

#define IXGB_RAH_ASEL_DEST 0x00000000

Definition at line 396 of file ixgb_hw.h.

#define IXGB_RAH_ASEL_MASK 0x00030000

Definition at line 395 of file ixgb_hw.h.

#define IXGB_RAH_ASEL_SRC 0x00010000

Definition at line 397 of file ixgb_hw.h.

#define IXGB_RAH_AV 0x80000000

Definition at line 398 of file ixgb_hw.h.

#define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */

Definition at line 140 of file ixgb_hw.h.

#define IXGB_RAIDC_DELAY_MASK 0x000FF800

Definition at line 378 of file ixgb_hw.h.

#define IXGB_RAIDC_DELAY_SHIFT 11

Definition at line 379 of file ixgb_hw.h.

#define IXGB_RAIDC_EN 0x80000000

Definition at line 383 of file ixgb_hw.h.

#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F

Definition at line 377 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122

Definition at line 387 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220

Definition at line 385 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61

Definition at line 388 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244

Definition at line 386 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_MASK 0x1FF00000

Definition at line 380 of file ixgb_hw.h.

#define IXGB_RAIDC_POLL_SHIFT 20

Definition at line 381 of file ixgb_hw.h.

#define IXGB_RAIDC_RXT_GATE 0x40000000

Definition at line 382 of file ixgb_hw.h.

#define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */

Definition at line 143 of file ixgb_hw.h.

#define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */

Definition at line 611 of file ixgb_hw.h.

#define IXGB_RCTL 0x00100 /* RX Control - RW */

Definition at line 130 of file ixgb_hw.h.

#define IXGB_RCTL_BAM 0x00008000

Definition at line 347 of file ixgb_hw.h.

#define IXGB_RCTL_BSIZE_16384 0x00030000

Definition at line 352 of file ixgb_hw.h.

#define IXGB_RCTL_BSIZE_2048 0x00000000

Definition at line 349 of file ixgb_hw.h.

#define IXGB_RCTL_BSIZE_4096 0x00010000

Definition at line 350 of file ixgb_hw.h.

#define IXGB_RCTL_BSIZE_8192 0x00020000

Definition at line 351 of file ixgb_hw.h.

#define IXGB_RCTL_BSIZE_MASK 0x00030000

Definition at line 348 of file ixgb_hw.h.

#define IXGB_RCTL_CFF 0x00800000

Definition at line 359 of file ixgb_hw.h.

#define IXGB_RCTL_CFI 0x00100000

Definition at line 355 of file ixgb_hw.h.

#define IXGB_RCTL_CFIEN 0x00080000

Definition at line 354 of file ixgb_hw.h.

#define IXGB_RCTL_IDLE_RX_UNIT 0

Definition at line 363 of file ixgb_hw.h.

#define IXGB_RCTL_MC_ONLY 0x00400000

Definition at line 358 of file ixgb_hw.h.

#define IXGB_RCTL_MO_43_32 0x00003000

Definition at line 345 of file ixgb_hw.h.

#define IXGB_RCTL_MO_45_34 0x00002000

Definition at line 344 of file ixgb_hw.h.

#define IXGB_RCTL_MO_46_35 0x00001000

Definition at line 343 of file ixgb_hw.h.

#define IXGB_RCTL_MO_47_36 0x00000000

Definition at line 342 of file ixgb_hw.h.

#define IXGB_RCTL_MO_MASK 0x00003000

Definition at line 341 of file ixgb_hw.h.

#define IXGB_RCTL_MO_SHIFT 12

Definition at line 346 of file ixgb_hw.h.

#define IXGB_RCTL_MPE 0x00000010

Definition at line 336 of file ixgb_hw.h.

#define IXGB_RCTL_RDMTS_1_2 0x00000000

Definition at line 338 of file ixgb_hw.h.

#define IXGB_RCTL_RDMTS_1_4 0x00000100

Definition at line 339 of file ixgb_hw.h.

#define IXGB_RCTL_RDMTS_1_8 0x00000200

Definition at line 340 of file ixgb_hw.h.

#define IXGB_RCTL_RDMTS_MASK 0x00000300

Definition at line 337 of file ixgb_hw.h.

#define IXGB_RCTL_RPDA_MASK 0x00600000

Definition at line 356 of file ixgb_hw.h.

#define IXGB_RCTL_RPDA_MC_MAC 0x00000000

Definition at line 357 of file ixgb_hw.h.

#define IXGB_RCTL_RXEN 0x00000002

Definition at line 333 of file ixgb_hw.h.

#define IXGB_RCTL_SBP 0x00000004

Definition at line 334 of file ixgb_hw.h.

#define IXGB_RCTL_SECRC 0x04000000

Definition at line 360 of file ixgb_hw.h.

#define IXGB_RCTL_UPE 0x00000008

Definition at line 335 of file ixgb_hw.h.

#define IXGB_RCTL_VFE 0x00040000

Definition at line 353 of file ixgb_hw.h.

#define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */

Definition at line 134 of file ixgb_hw.h.

#define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */

Definition at line 133 of file ixgb_hw.h.

#define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */

Definition at line 136 of file ixgb_hw.h.

#define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */

Definition at line 135 of file ixgb_hw.h.

#define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */

Definition at line 137 of file ixgb_hw.h.

#define IXGB_RDT_FPDB 0x80000000

Definition at line 361 of file ixgb_hw.h.

#define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */

Definition at line 138 of file ixgb_hw.h.

#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8

Definition at line 147 of file ixgb_hw.h.

#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8

Definition at line 160 of file ixgb_hw.h.

#define IXGB_RFC 0x02188 /* Remote Fault Count */

Definition at line 234 of file ixgb_hw.h.

#define IXGB_RJC 0x021D8 /* Receive Jabber Count */

Definition at line 244 of file ixgb_hw.h.

#define IXGB_RLEC 0x02060 /* Receive Length Error Count */

Definition at line 206 of file ixgb_hw.h.

#define IXGB_RNBC 0x02048 /* Receive No Buffers Count */

Definition at line 203 of file ixgb_hw.h.

#define IXGB_ROC 0x02058 /* Receive Oversize Count */

Definition at line 205 of file ixgb_hw.h.

#define IXGB_RUC 0x02050 /* Receive Undersize Count */

Definition at line 204 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_CE 0x01

Definition at line 542 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_IPE 0x40

Definition at line 546 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_P 0x08

Definition at line 544 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_RXE 0x80

Definition at line 547 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_SE 0x02

Definition at line 543 of file ixgb_hw.h.

#define IXGB_RX_DESC_ERRORS_TCPE 0x20

Definition at line 545 of file ixgb_hw.h.

#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */

Definition at line 550 of file ixgb_hw.h.

#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */

Definition at line 551 of file ixgb_hw.h.

#define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */

Definition at line 549 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_DD 0x01

Definition at line 534 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_EOP 0x02

Definition at line 535 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_IPCS 0x40

Definition at line 539 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_IXSM 0x04

Definition at line 536 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_PIF 0x80

Definition at line 540 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_TCPCS 0x20

Definition at line 538 of file ixgb_hw.h.

#define IXGB_RX_DESC_STATUS_VP 0x08

Definition at line 537 of file ixgb_hw.h.

#define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */

Definition at line 141 of file ixgb_hw.h.

#define IXGB_RXCSUM_IPOFL 0x00000100

Definition at line 391 of file ixgb_hw.h.

#define IXGB_RXCSUM_TUOFL 0x00000200

Definition at line 392 of file ixgb_hw.h.

#define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */

Definition at line 139 of file ixgb_hw.h.

#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00

Definition at line 371 of file ixgb_hw.h.

#define IXGB_RXDCTL_HTHRESH_SHIFT 9

Definition at line 372 of file ixgb_hw.h.

#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF

Definition at line 369 of file ixgb_hw.h.

#define IXGB_RXDCTL_PTHRESH_SHIFT 0

Definition at line 370 of file ixgb_hw.h.

#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000

Definition at line 373 of file ixgb_hw.h.

#define IXGB_RXDCTL_WTHRESH_SHIFT 18

Definition at line 374 of file ixgb_hw.h.

#define IXGB_STATUS 0x00010 /* Device Status Register - RO */

Definition at line 119 of file ixgb_hw.h.

#define IXGB_STATUS_AIP 0x00000004

Definition at line 288 of file ixgb_hw.h.

#define IXGB_STATUS_BUS64 0x00001000

Definition at line 297 of file ixgb_hw.h.

#define IXGB_STATUS_LU 0x00000002

Definition at line 287 of file ixgb_hw.h.

#define IXGB_STATUS_PCI_SPD 0x00000800

Definition at line 296 of file ixgb_hw.h.

#define IXGB_STATUS_PCIX_MODE 0x00002000

Definition at line 298 of file ixgb_hw.h.

#define IXGB_STATUS_PCIX_SPD_100 0x00004000

Definition at line 301 of file ixgb_hw.h.

#define IXGB_STATUS_PCIX_SPD_133 0x00008000

Definition at line 302 of file ixgb_hw.h.

#define IXGB_STATUS_PCIX_SPD_66 0x00000000

Definition at line 300 of file ixgb_hw.h.

#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000

Definition at line 299 of file ixgb_hw.h.

#define IXGB_STATUS_RES 0x00000040

Definition at line 291 of file ixgb_hw.h.

#define IXGB_STATUS_REV_ID_MASK 0x000F0000

Definition at line 303 of file ixgb_hw.h.

#define IXGB_STATUS_REV_ID_SHIFT 16

Definition at line 304 of file ixgb_hw.h.

#define IXGB_STATUS_RIE 0x00000100

Definition at line 293 of file ixgb_hw.h.

#define IXGB_STATUS_RIS 0x00000080

Definition at line 292 of file ixgb_hw.h.

#define IXGB_STATUS_RLF 0x00000200

Definition at line 294 of file ixgb_hw.h.

#define IXGB_STATUS_RRF 0x00000400

Definition at line 295 of file ixgb_hw.h.

#define IXGB_STATUS_TXOFF 0x00000010

Definition at line 289 of file ixgb_hw.h.

#define IXGB_STATUS_XAUIME 0x00000020

Definition at line 290 of file ixgb_hw.h.

#define IXGB_TCTL 0x00600 /* TX Control - RW */

Definition at line 150 of file ixgb_hw.h.

#define IXGB_TCTL_IDLE_TX_UNIT 0

Definition at line 405 of file ixgb_hw.h.

#define IXGB_TCTL_TCE 0x00000001

Definition at line 401 of file ixgb_hw.h.

#define IXGB_TCTL_TPDE 0x00000004

Definition at line 403 of file ixgb_hw.h.

#define IXGB_TCTL_TXEN 0x00000002

Definition at line 402 of file ixgb_hw.h.

#define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */

Definition at line 152 of file ixgb_hw.h.

#define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */

Definition at line 151 of file ixgb_hw.h.

#define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */

Definition at line 154 of file ixgb_hw.h.

#define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */

Definition at line 153 of file ixgb_hw.h.

#define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */

Definition at line 155 of file ixgb_hw.h.

#define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */

Definition at line 156 of file ixgb_hw.h.

#define IXGB_TORH 0x02044 /* Total Octets Received (High) */

Definition at line 202 of file ixgb_hw.h.

#define IXGB_TORL 0x02040 /* Total Octets Received (Low) */

Definition at line 201 of file ixgb_hw.h.

#define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */

Definition at line 228 of file ixgb_hw.h.

#define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */

Definition at line 227 of file ixgb_hw.h.

#define IXGB_TPRH 0x02004 /* Total Packets Received (High) */

Definition at line 186 of file ixgb_hw.h.

#define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */

Definition at line 185 of file ixgb_hw.h.

#define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */

Definition at line 212 of file ixgb_hw.h.

#define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */

Definition at line 211 of file ixgb_hw.h.

#define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */

Definition at line 231 of file ixgb_hw.h.

#define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */

Definition at line 232 of file ixgb_hw.h.

#define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */

Definition at line 158 of file ixgb_hw.h.

#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF

Definition at line 415 of file ixgb_hw.h.

#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000

Definition at line 416 of file ixgb_hw.h.

#define IXGB_TSPMT_TSPBP_SHIFT 16

Definition at line 417 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_EOP 0x01000000

Definition at line 571 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_IDE 0x80000000

Definition at line 575 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_MASK 0xFF000000

Definition at line 569 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_RS 0x08000000

Definition at line 573 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_SHIFT 24

Definition at line 570 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_TSE 0x04000000

Definition at line 572 of file ixgb_hw.h.

#define IXGB_TX_DESC_CMD_VLE 0x40000000

Definition at line 574 of file ixgb_hw.h.

#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF

Definition at line 566 of file ixgb_hw.h.

#define IXGB_TX_DESC_POPTS_IXSM 0x01

Definition at line 581 of file ixgb_hw.h.

#define IXGB_TX_DESC_POPTS_TXSM 0x02

Definition at line 582 of file ixgb_hw.h.

#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */

Definition at line 583 of file ixgb_hw.h.

#define IXGB_TX_DESC_STATUS_DD 0x01

Definition at line 579 of file ixgb_hw.h.

#define IXGB_TX_DESC_TYPE 0x00100000

Definition at line 577 of file ixgb_hw.h.

#define IXGB_TX_DESC_TYPE_MASK 0x00F00000

Definition at line 567 of file ixgb_hw.h.

#define IXGB_TX_DESC_TYPE_SHIFT 20

Definition at line 568 of file ixgb_hw.h.

#define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */

Definition at line 157 of file ixgb_hw.h.

#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00

Definition at line 409 of file ixgb_hw.h.

#define IXGB_TXDCTL_HTHRESH_SHIFT 8

Definition at line 410 of file ixgb_hw.h.

#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F

Definition at line 408 of file ixgb_hw.h.

#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000

Definition at line 411 of file ixgb_hw.h.

#define IXGB_TXDCTL_WTHRESH_SHIFT 16

Definition at line 412 of file ixgb_hw.h.

#define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */

Definition at line 168 of file ixgb_hw.h.

#define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */

Definition at line 194 of file ixgb_hw.h.

#define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */

Definition at line 193 of file ixgb_hw.h.

#define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */

Definition at line 220 of file ixgb_hw.h.

#define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */

Definition at line 219 of file ixgb_hw.h.

#define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */

Definition at line 146 of file ixgb_hw.h.

#define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */

Definition at line 610 of file ixgb_hw.h.

#define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */

Definition at line 196 of file ixgb_hw.h.

#define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */

Definition at line 195 of file ixgb_hw.h.

#define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */

Definition at line 222 of file ixgb_hw.h.

#define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */

Definition at line 221 of file ixgb_hw.h.

#define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */

Definition at line 178 of file ixgb_hw.h.

#define IXGB_WUS 0x00810 /* Wake Up Status - RO */

Definition at line 179 of file ixgb_hw.h.

#define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */

Definition at line 623 of file ixgb_hw.h.

#define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */

Definition at line 242 of file ixgb_hw.h.

#define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */

Definition at line 243 of file ixgb_hw.h.

#define IXGB_XONRXC 0x021B8 /* XON Received Count */

Definition at line 240 of file ixgb_hw.h.

#define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */

Definition at line 241 of file ixgb_hw.h.

#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */

Definition at line 167 of file ixgb_hw.h.

#define IXGB_XPCSS_ALIGN_STATUS 0x00001000

Definition at line 455 of file ixgb_hw.h.

#define IXGB_XPCSS_LANE_0_SYNC 0x00000001

Definition at line 460 of file ixgb_hw.h.

#define IXGB_XPCSS_LANE_1_SYNC 0x00000002

Definition at line 459 of file ixgb_hw.h.

#define IXGB_XPCSS_LANE_2_SYNC 0x00000004

Definition at line 458 of file ixgb_hw.h.

#define IXGB_XPCSS_LANE_3_SYNC 0x00000008

Definition at line 457 of file ixgb_hw.h.

#define IXGB_XPCSS_PATTERN_TEST 0x00000800

Definition at line 456 of file ixgb_hw.h.

#define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */

Definition at line 169 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000

Definition at line 469 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001

Definition at line 468 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003

Definition at line 467 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000

Definition at line 465 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17

Definition at line 466 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_SST 0x00100000

Definition at line 464 of file ixgb_hw.h.

#define IXGB_XPCSTC_BERT_TRIG 0x00200000

Definition at line 463 of file ixgb_hw.h.

#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */

Definition at line 106 of file ixgb_hw.h.

#define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */

Definition at line 114 of file ixgb_hw.h.

#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */

Definition at line 510 of file ixgb_hw.h.

#define MIN_NUMBER_OF_DESCRIPTORS 8

Definition at line 105 of file ixgb_hw.h.

#define SPEED_10000 10000

Definition at line 102 of file ixgb_hw.h.

Enumeration Type Documentation

enum ixgb_bus_speed

Enumerator:

ixgb_bus_speed_unknown
ixgb_bus_speed_33
ixgb_bus_speed_66
ixgb_bus_speed_100
ixgb_bus_speed_133
ixgb_bus_speed_reserved

Definition at line 84 of file ixgb_hw.h.

enum ixgb_bus_type

Enumerator:

ixgb_bus_type_unknown
ixgb_bus_type_pci
ixgb_bus_type_pcix

Definition at line 77 of file ixgb_hw.h.

enum ixgb_bus_width

Enumerator:

ixgb_bus_width_unknown
ixgb_bus_width_32
ixgb_bus_width_64

Definition at line 94 of file ixgb_hw.h.

enum ixgb_fc_type

Enumerator:

ixgb_fc_none
ixgb_fc_rx_pause
ixgb_fc_tx_pause
ixgb_fc_full
ixgb_fc_default

Definition at line 68 of file ixgb_hw.h.

enum ixgb_mac_type

Enumerator:

ixgb_mac_unknown
ixgb_82597
ixgb_num_macs

Definition at line 37 of file ixgb_hw.h.

enum ixgb_media_type

Enumerator:

ixgb_media_type_unknown
ixgb_media_type_fiber
ixgb_media_type_copper
ixgb_num_media_types

Definition at line 60 of file ixgb_hw.h.

enum ixgb_phy_type

Enumerator:

ixgb_phy_type_unknown
ixgb_phy_type_g6005
ixgb_phy_type_g6104
ixgb_phy_type_txn17201
ixgb_phy_type_txn17401
ixgb_phy_type_bcm

Definition at line 44 of file ixgb_hw.h.

enum ixgb_xpak_vendor

Enumerator:

ixgb_xpak_vendor_intel
ixgb_xpak_vendor_infineon

Definition at line 54 of file ixgb_hw.h.

Function Documentation

bool ixgb_adapter_start ( struct ixgb_hw * hw )

bool ixgb_adapter_stop ( struct ixgb_hw * hw )

Definition at line 123 of file ixgb_hw.c.

bool ixgb_check_for_bad_link ( struct ixgb_hw * hw )

Definition at line 949 of file ixgb_hw.c.

void ixgb_check_for_link ( struct ixgb_hw * hw )

Definition at line 913 of file ixgb_hw.c.

u16 ixgb_get_ee_device_id ( struct ixgb_hw * hw )

Definition at line 596 of file ixgb_ee.c.

void ixgb_get_ee_mac_addr	(	struct ixgb_hw *	hw,
		u8 *	mac_addr
	)

Definition at line 551 of file ixgb_ee.c.

u32 ixgb_get_ee_pba_number ( struct ixgb_hw * hw )

Definition at line 577 of file ixgb_ee.c.

bool ixgb_get_eeprom_data ( struct ixgb_hw * hw )

Definition at line 465 of file ixgb_ee.c.

__le16 ixgb_get_eeprom_word	(	struct ixgb_hw *	hw,
		u16	index
	)

Definition at line 533 of file ixgb_ee.c.

bool ixgb_init_hw ( struct ixgb_hw * hw )

Definition at line 299 of file ixgb_hw.c.

void ixgb_led_off ( struct ixgb_hw * hw )

Definition at line 1070 of file ixgb_hw.c.

void ixgb_led_on ( struct ixgb_hw * hw )

Definition at line 1055 of file ixgb_hw.c.

void ixgb_mc_addr_list_update	(	struct ixgb_hw *	hw,
		u8 *	mc_addr_list,
		u32	mc_addr_count,
		u32	pad
	)

Definition at line 434 of file ixgb_hw.c.

void ixgb_rar_set	(	struct ixgb_hw *	hw,
		u8 *	addr,
		u32	index
	)

Definition at line 578 of file ixgb_hw.c.

void ixgb_write_pci_cfg	(	struct ixgb_hw *	hw,
		u32	reg,
		u16 *	value
	)

void ixgb_write_vfta	(	struct ixgb_hw *	hw,
		u32	offset,
		u32	value
	)

Definition at line 610 of file ixgb_hw.c.

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation