#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h>
Go to the source code of this file.
| #define JZ_NAND_CTRL_ASSERT_CHIP |
( |
|
x | ) |
BIT(((x) << 1) + 1) |
| #define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa |
| #define JZ_NAND_CTRL_ENABLE_CHIP |
( |
|
x | ) |
BIT((x) << 1) |
| #define JZ_NAND_ECC_CTRL_ENABLE BIT(0) |
| #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) |
| #define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) |
| #define JZ_NAND_ECC_CTRL_RESET BIT(1) |
| #define JZ_NAND_ECC_CTRL_RS BIT(2) |
| #define JZ_NAND_MEM_ADDR_OFFSET 0x10000 |
| #define JZ_NAND_MEM_CMD_OFFSET 0x08000 |
| #define JZ_NAND_STATUS_DEC_FINISH BIT(3) |
| #define JZ_NAND_STATUS_ENC_FINISH BIT(2) |
| #define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) |
| #define JZ_NAND_STATUS_ERROR BIT(0) |
| #define JZ_NAND_STATUS_PAD_FINISH BIT(4) |
| #define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) |
| #define JZ_REG_NAND_CTRL 0x50 |
| #define JZ_REG_NAND_DATA 0x104 |
| #define JZ_REG_NAND_ECC_CTRL 0x100 |
| #define JZ_REG_NAND_ERR |
( |
|
x | ) |
(0x11C + ((x) << 2)) |
| #define JZ_REG_NAND_IRQ_CTRL 0x118 |
| #define JZ_REG_NAND_IRQ_STAT 0x114 |
| #define JZ_REG_NAND_PAR0 0x108 |
| #define JZ_REG_NAND_PAR1 0x10C |
| #define JZ_REG_NAND_PAR2 0x110 |
| MODULE_ALIAS |
( |
"platform:jz4740-nand" |
| ) |
|
| module_platform_driver |
( |
jz_nand_driver |
| ) |
|