Data Structures
struct	lis3l02dq_state

Macros
#define	LIS3L02DQ_READ_REG(a) ((a) \| 0x80)

#define	LIS3L02DQ_WRITE_REG(a) a

#define	LIS3L02DQ_REG_OFFSET_X_ADDR 0x16

#define	LIS3L02DQ_REG_OFFSET_Y_ADDR 0x17

#define	LIS3L02DQ_REG_OFFSET_Z_ADDR 0x18

#define	LIS3L02DQ_REG_GAIN_X_ADDR 0x19

#define	LIS3L02DQ_REG_GAIN_Y_ADDR 0x1A

#define	LIS3L02DQ_REG_GAIN_Z_ADDR 0x1B

#define	LIS3L02DQ_REG_CTRL_1_ADDR 0x20

#define	LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0

#define	LIS3L02DQ_DEC_MASK 0x30

#define	LIS3L02DQ_REG_CTRL_1_DF_128 0x00

#define	LIS3L02DQ_REG_CTRL_1_DF_64 0x10

#define	LIS3L02DQ_REG_CTRL_1_DF_32 0x20

#define	LIS3L02DQ_REG_CTRL_1_DF_8 (0x10 \| 0x20)

#define	LIS3L02DQ_REG_CTRL_1_SELF_TEST_ON 0x08

#define	LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE 0x04

#define	LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE 0x02

#define	LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE 0x01

#define	LIS3L02DQ_REG_CTRL_2_ADDR 0x21

#define	LIS3L02DQ_REG_CTRL_2_BLOCK_UPDATE 0x40

#define	LIS3L02DQ_REG_CTRL_2_BIG_ENDIAN 0x20

#define	LIS3L02DQ_REG_CTRL_2_REBOOT_MEMORY 0x10

#define	LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT 0x08

#define	LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION 0x04

#define	LIS3L02DQ_REG_CTRL_2_THREE_WIRE_SPI_MODE 0x02

#define	LIS3L02DQ_REG_CTRL_2_DATA_ALIGNMENT_16_BIT_LEFT_JUSTIFIED 0x01

#define	LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23

#define	LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80

#define	LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH 0x08

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW 0x04

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH 0x02

#define	LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW 0x01

#define	LIS3L02DQ_REG_WAKE_UP_SRC_ADDR 0x24

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_ACTIVATED 0x40

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH 0x20

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW 0x10

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH 0x08

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW 0x04

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH 0x02

#define	LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW 0x01

#define	LIS3L02DQ_REG_WAKE_UP_ACK_ADDR 0x25

#define	LIS3L02DQ_REG_STATUS_ADDR 0x27

#define	LIS3L02DQ_REG_STATUS_XYZ_OVERRUN 0x80

#define	LIS3L02DQ_REG_STATUS_Z_OVERRUN 0x40

#define	LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20

#define	LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10

#define	LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08

#define	LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04

#define	LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02

#define	LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01

#define	LIS3L02DQ_REG_OUT_X_L_ADDR 0x28

#define	LIS3L02DQ_REG_OUT_X_H_ADDR 0x29

#define	LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A

#define	LIS3L02DQ_REG_OUT_Y_H_ADDR 0x2B

#define	LIS3L02DQ_REG_OUT_Z_L_ADDR 0x2C

#define	LIS3L02DQ_REG_OUT_Z_H_ADDR 0x2D

#define	LIS3L02DQ_REG_THS_L_ADDR 0x2E

#define	LIS3L02DQ_REG_THS_H_ADDR 0x2F

#define	LIS3L02DQ_DEFAULT_CTRL1

#define	LIS3L02DQ_DEFAULT_CTRL2 0

#define	LIS3L02DQ_MAX_TX 12

#define	LIS3L02DQ_MAX_RX 12

#define	lis3l02dq_th lis3l02dq_nobuffer

Functions
int	lis3l02dq_spi_read_reg_8 (struct iio_dev indio_dev, u8 reg_address, u8 val)

int	lis3l02dq_spi_write_reg_8 (struct iio_dev *indio_dev, u8 reg_address, u8 val)

int	lis3l02dq_disable_all_events (struct iio_dev *indio_dev)

Macro Definition Documentation

#define LIS3L02DQ_DEC_MASK 0x30

Definition at line 34 of file lis3l02dq.h.

#define LIS3L02DQ_DEFAULT_CTRL1

Value:

(LIS3L02DQ_REG_CTRL_1_PD_ON       \
                 | LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE \
                 | LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE \
                 | LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE \
                 | LIS3L02DQ_REG_CTRL_1_DF_128)

Definition at line 139 of file lis3l02dq.h.

#define LIS3L02DQ_DEFAULT_CTRL2 0

Definition at line 145 of file lis3l02dq.h.

#define LIS3L02DQ_MAX_RX 12

Definition at line 148 of file lis3l02dq.h.

#define LIS3L02DQ_MAX_TX 12

Definition at line 147 of file lis3l02dq.h.

#define LIS3L02DQ_READ_REG ( a ) ((a) | 0x80)

Definition at line 16 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_ADDR 0x20

Definition at line 29 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE 0x01

Definition at line 46 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE 0x02

Definition at line 45 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE 0x04

Definition at line 44 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_DF_128 0x00

Definition at line 35 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_DF_32 0x20

Definition at line 37 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_DF_64 0x10

Definition at line 36 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_DF_8 (0x10 | 0x20)

Definition at line 38 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0

Definition at line 31 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_1_SELF_TEST_ON 0x08

Definition at line 41 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_ADDR 0x21

Definition at line 49 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_BIG_ENDIAN 0x20

Definition at line 55 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_BLOCK_UPDATE 0x40

Definition at line 52 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_DATA_ALIGNMENT_16_BIT_LEFT_JUSTIFIED 0x01

Definition at line 71 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION 0x04

Definition at line 64 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT 0x08

Definition at line 61 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_REBOOT_MEMORY 0x10

Definition at line 58 of file lis3l02dq.h.

#define LIS3L02DQ_REG_CTRL_2_THREE_WIRE_SPI_MODE 0x02

Definition at line 67 of file lis3l02dq.h.

#define LIS3L02DQ_REG_GAIN_X_ADDR 0x19

Definition at line 24 of file lis3l02dq.h.

#define LIS3L02DQ_REG_GAIN_Y_ADDR 0x1A

Definition at line 25 of file lis3l02dq.h.

#define LIS3L02DQ_REG_GAIN_Z_ADDR 0x1B

Definition at line 26 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OFFSET_X_ADDR 0x16

Definition at line 20 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OFFSET_Y_ADDR 0x17

Definition at line 21 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OFFSET_Z_ADDR 0x18

Definition at line 22 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_X_H_ADDR 0x29

Definition at line 128 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_X_L_ADDR 0x28

Definition at line 127 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_Y_H_ADDR 0x2B

Definition at line 130 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A

Definition at line 129 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_Z_H_ADDR 0x2D

Definition at line 132 of file lis3l02dq.h.

#define LIS3L02DQ_REG_OUT_Z_L_ADDR 0x2C

Definition at line 131 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_ADDR 0x27

Definition at line 113 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01

Definition at line 123 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10

Definition at line 118 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08

Definition at line 120 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_XYZ_OVERRUN 0x80

Definition at line 115 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02

Definition at line 122 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20

Definition at line 117 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04

Definition at line 121 of file lis3l02dq.h.

#define LIS3L02DQ_REG_STATUS_Z_OVERRUN 0x40

Definition at line 116 of file lis3l02dq.h.

#define LIS3L02DQ_REG_THS_H_ADDR 0x2F

Definition at line 137 of file lis3l02dq.h.

#define LIS3L02DQ_REG_THS_L_ADDR 0x2E

Definition at line 136 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_ACK_ADDR 0x25

Definition at line 110 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23

Definition at line 74 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80

Definition at line 77 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH 0x02

Definition at line 92 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW 0x01

Definition at line 94 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH 0x08

Definition at line 88 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW 0x04

Definition at line 90 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20

Definition at line 84 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10

Definition at line 86 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40

Definition at line 81 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_ADDR 0x24

Definition at line 98 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_ACTIVATED 0x40

Definition at line 101 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH 0x02

Definition at line 107 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW 0x01

Definition at line 108 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH 0x08

Definition at line 105 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW 0x04

Definition at line 106 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH 0x20

Definition at line 103 of file lis3l02dq.h.

#define LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW 0x10

Definition at line 104 of file lis3l02dq.h.

#define lis3l02dq_th lis3l02dq_nobuffer

Definition at line 199 of file lis3l02dq.h.

#define LIS3L02DQ_WRITE_REG ( a ) a

Definition at line 17 of file lis3l02dq.h.

Function Documentation

int lis3l02dq_disable_all_events ( struct iio_dev * indio_dev )

Definition at line 567 of file lis3l02dq_core.c.

int lis3l02dq_spi_read_reg_8	(	struct iio_dev *	indio_dev,
		u8	reg_address,
		u8 *	val
	)

lis3l02dq_spi_read_reg_8() - read single byte from a single register : iio_dev for this actual device : the address of the register to be read : pass back the resulting value

Definition at line 51 of file lis3l02dq_core.c.

int lis3l02dq_spi_write_reg_8	(	struct iio_dev *	indio_dev,
		u8	reg_address,
		u8	val
	)

lis3l02dq_spi_write_reg_8() - write single byte to a register : iio_dev for this device : the address of the register to be written : the value to write

Definition at line 83 of file lis3l02dq_core.c.

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation