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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | cdmac_bd |
| struct | temac_local |
Macros | |
| #define | XTE_HDR_SIZE 14 /* size of Ethernet header */ |
| #define | XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ |
| #define | XTE_JUMBO_MTU 9000 |
| #define | XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE) |
| #define | XTE_OPTION_PROMISC (1 << 0) |
| #define | XTE_OPTION_JUMBO (1 << 1) |
| #define | XTE_OPTION_VLAN (1 << 2) |
| #define | XTE_OPTION_FLOW_CONTROL (1 << 4) |
| #define | XTE_OPTION_FCS_STRIP (1 << 5) |
| #define | XTE_OPTION_FCS_INSERT (1 << 6) |
| #define | XTE_OPTION_LENTYPE_ERR (1 << 7) |
| #define | XTE_OPTION_TXEN (1 << 11) |
| #define | XTE_OPTION_RXEN (1 << 12) |
| #define | XTE_OPTION_DEFAULTS |
| #define | TX_NXTDESC_PTR 0x00 /* r */ |
| #define | TX_CURBUF_ADDR 0x01 /* r */ |
| #define | TX_CURBUF_LENGTH 0x02 /* r */ |
| #define | TX_CURDESC_PTR 0x03 /* rw */ |
| #define | TX_TAILDESC_PTR 0x04 /* rw */ |
| #define | TX_CHNL_CTRL 0x05 /* rw */ |
| #define | CHNL_CTRL_IRQ_IOE (1 << 9) |
| #define | CHNL_CTRL_IRQ_EN (1 << 7) |
| #define | CHNL_CTRL_IRQ_ERR_EN (1 << 2) |
| #define | CHNL_CTRL_IRQ_DLY_EN (1 << 1) |
| #define | CHNL_CTRL_IRQ_COAL_EN (1 << 0) |
| #define | TX_IRQ_REG 0x06 /* rw */ |
| #define | TX_CHNL_STS 0x07 /* r */ |
| #define | RX_NXTDESC_PTR 0x08 /* r */ |
| #define | RX_CURBUF_ADDR 0x09 /* r */ |
| #define | RX_CURBUF_LENGTH 0x0a /* r */ |
| #define | RX_CURDESC_PTR 0x0b /* rw */ |
| #define | RX_TAILDESC_PTR 0x0c /* rw */ |
| #define | RX_CHNL_CTRL 0x0d /* rw */ |
| #define | RX_IRQ_REG 0x0e /* rw */ |
| #define | IRQ_COAL (1 << 0) |
| #define | IRQ_DLY (1 << 1) |
| #define | IRQ_ERR (1 << 2) |
| #define | IRQ_DMAERR (1 << 7) /* this is not documented ??? */ |
| #define | RX_CHNL_STS 0x0f /* r */ |
| #define | CHNL_STS_ENGBUSY (1 << 1) |
| #define | CHNL_STS_EOP (1 << 2) |
| #define | CHNL_STS_SOP (1 << 3) |
| #define | CHNL_STS_CMPLT (1 << 4) |
| #define | CHNL_STS_SOE (1 << 5) |
| #define | CHNL_STS_IOE (1 << 6) |
| #define | CHNL_STS_ERR (1 << 7) |
| #define | CHNL_STS_BSYWR (1 << 16) |
| #define | CHNL_STS_CURPERR (1 << 17) |
| #define | CHNL_STS_NXTPERR (1 << 18) |
| #define | CHNL_STS_ADDRERR (1 << 19) |
| #define | CHNL_STS_CMPERR (1 << 20) |
| #define | CHNL_STS_TAILERR (1 << 21) |
| #define | DMA_CONTROL_REG 0x10 /* rw */ |
| #define | DMA_CONTROL_RST (1 << 0) |
| #define | DMA_TAIL_ENABLE (1 << 2) |
| #define | XTE_RAF0_OFFSET 0x00 |
| #define | RAF0_RST (1 << 0) |
| #define | RAF0_MCSTREJ (1 << 1) |
| #define | RAF0_BCSTREJ (1 << 2) |
| #define | XTE_TPF0_OFFSET 0x04 |
| #define | XTE_IFGP0_OFFSET 0x08 |
| #define | XTE_ISR0_OFFSET 0x0c |
| #define | ISR0_HARDACSCMPLT (1 << 0) |
| #define | ISR0_AUTONEG (1 << 1) |
| #define | ISR0_RXCMPLT (1 << 2) |
| #define | ISR0_RXREJ (1 << 3) |
| #define | ISR0_RXFIFOOVR (1 << 4) |
| #define | ISR0_TXCMPLT (1 << 5) |
| #define | ISR0_RXDCMLCK (1 << 6) |
| #define | XTE_IPR0_OFFSET 0x10 |
| #define | XTE_IER0_OFFSET 0x14 |
| #define | XTE_MSW0_OFFSET 0x20 |
| #define | XTE_LSW0_OFFSET 0x24 |
| #define | XTE_CTL0_OFFSET 0x28 |
| #define | XTE_RDY0_OFFSET 0x2c |
| #define | XTE_RSE_MIIM_RR_MASK 0x0002 |
| #define | XTE_RSE_MIIM_WR_MASK 0x0004 |
| #define | XTE_RSE_CFG_RR_MASK 0x0020 |
| #define | XTE_RSE_CFG_WR_MASK 0x0040 |
| #define | XTE_RDY0_HARD_ACS_RDY_MASK (0x10000) |
| #define | XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */ |
| #define | XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */ |
| #define | XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */ |
| #define | XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */ |
| #define | XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */ |
| #define | XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */ |
| #define | XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */ |
| #define | XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */ |
| #define | XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */ |
| #define | XTE_TXC_OFFSET 0x00000280 /* Tx configuration */ |
| #define | XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */ |
| #define | XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */ |
| #define | XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */ |
| #define | XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */ |
| #define | XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */ |
| #define | XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */ |
| #define | XTE_FCC_OFFSET 0x000002C0 /* Flow control config */ |
| #define | XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */ |
| #define | XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */ |
| #define | XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */ |
| #define | XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */ |
| #define | XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */ |
| #define | XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */ |
| #define | XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */ |
| #define | XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */ |
| #define | XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */ |
| #define | XTE_MC_OFFSET 0x00000340 /* MDIO configuration */ |
| #define | XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */ |
| #define | XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */ |
| #define | XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */ |
| #define | XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */ |
| #define | XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */ |
| #define | XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */ |
| #define | XTE_TIS_OFFSET 0x000003A0 |
| #define | TIS_FRIS (1 << 0) |
| #define | TIS_MRIS (1 << 1) |
| #define | TIS_MWIS (1 << 2) |
| #define | TIS_ARIS (1 << 3) |
| #define | TIS_AWIS (1 << 4) |
| #define | TIS_CRIS (1 << 5) |
| #define | TIS_CWIS (1 << 6) |
| #define | XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */ |
| #define | XTE_MGTDR_OFFSET 0x000003B0 /* MII data */ |
| #define | XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */ |
| #define | CNTLREG_WRITE_ENABLE_MASK 0x8000 |
| #define | CNTLREG_EMAC1SEL_MASK 0x0400 |
| #define | CNTLREG_ADDRESSCODE_MASK 0x03ff |
| #define | STS_CTRL_APP0_ERR (1 << 31) |
| #define | STS_CTRL_APP0_IRQONEND (1 << 30) |
| #define | STS_CTRL_APP0_STOPONEND (1 << 29) |
| #define | STS_CTRL_APP0_CMPLT (1 << 28) |
| #define | STS_CTRL_APP0_SOP (1 << 27) |
| #define | STS_CTRL_APP0_EOP (1 << 26) |
| #define | STS_CTRL_APP0_ENGBUSY (1 << 25) |
| #define | STS_CTRL_APP0_ENGRST (1 << 24) |
| #define | TX_CONTROL_CALC_CSUM_MASK 1 |
| #define | MULTICAST_CAM_TABLE_NUM 4 |
| #define | TEMAC_FEATURE_RX_CSUM (1 << 0) |
| #define | TEMAC_FEATURE_TX_CSUM (1 << 1) |
Functions | |
| u32 | temac_ior (struct temac_local *lp, int offset) |
| void | temac_iow (struct temac_local *lp, int offset, u32 value) |
| int | temac_indirect_busywait (struct temac_local *lp) |
| u32 | temac_indirect_in32 (struct temac_local *lp, int reg) |
| void | temac_indirect_out32 (struct temac_local *lp, int reg, u32 value) |
| int | temac_mdio_setup (struct temac_local *lp, struct device_node *np) |
| void | temac_mdio_teardown (struct temac_local *lp) |
| #define CHNL_CTRL_IRQ_COAL_EN (1 << 0) |
Definition at line 86 of file ll_temac.h.
| #define CHNL_CTRL_IRQ_DLY_EN (1 << 1) |
Definition at line 85 of file ll_temac.h.
| #define CHNL_CTRL_IRQ_EN (1 << 7) |
Definition at line 83 of file ll_temac.h.
| #define CHNL_CTRL_IRQ_ERR_EN (1 << 2) |
Definition at line 84 of file ll_temac.h.
| #define CHNL_CTRL_IRQ_IOE (1 << 9) |
Definition at line 82 of file ll_temac.h.
| #define CHNL_STS_ADDRERR (1 << 19) |
Definition at line 163 of file ll_temac.h.
| #define CHNL_STS_BSYWR (1 << 16) |
Definition at line 160 of file ll_temac.h.
| #define CHNL_STS_CMPERR (1 << 20) |
Definition at line 164 of file ll_temac.h.
| #define CHNL_STS_CMPLT (1 << 4) |
Definition at line 155 of file ll_temac.h.
| #define CHNL_STS_CURPERR (1 << 17) |
Definition at line 161 of file ll_temac.h.
| #define CHNL_STS_ENGBUSY (1 << 1) |
Definition at line 152 of file ll_temac.h.
| #define CHNL_STS_EOP (1 << 2) |
Definition at line 153 of file ll_temac.h.
| #define CHNL_STS_ERR (1 << 7) |
Definition at line 158 of file ll_temac.h.
| #define CHNL_STS_IOE (1 << 6) |
Definition at line 157 of file ll_temac.h.
| #define CHNL_STS_NXTPERR (1 << 18) |
Definition at line 162 of file ll_temac.h.
| #define CHNL_STS_SOE (1 << 5) |
Definition at line 156 of file ll_temac.h.
| #define CHNL_STS_SOP (1 << 3) |
Definition at line 154 of file ll_temac.h.
| #define CHNL_STS_TAILERR (1 << 21) |
Definition at line 165 of file ll_temac.h.
| #define CNTLREG_ADDRESSCODE_MASK 0x03ff |
Definition at line 279 of file ll_temac.h.
| #define CNTLREG_EMAC1SEL_MASK 0x0400 |
Definition at line 278 of file ll_temac.h.
| #define CNTLREG_WRITE_ENABLE_MASK 0x8000 |
Definition at line 277 of file ll_temac.h.
| #define DMA_CONTROL_REG 0x10 /* rw */ |
Definition at line 185 of file ll_temac.h.
| #define DMA_CONTROL_RST (1 << 0) |
Definition at line 186 of file ll_temac.h.
| #define DMA_TAIL_ENABLE (1 << 2) |
Definition at line 187 of file ll_temac.h.
| #define IRQ_COAL (1 << 0) |
Definition at line 139 of file ll_temac.h.
| #define IRQ_DLY (1 << 1) |
Definition at line 140 of file ll_temac.h.
| #define IRQ_DMAERR (1 << 7) /* this is not documented ??? */ |
Definition at line 142 of file ll_temac.h.
| #define IRQ_ERR (1 << 2) |
Definition at line 141 of file ll_temac.h.
| #define ISR0_AUTONEG (1 << 1) |
Definition at line 199 of file ll_temac.h.
| #define ISR0_HARDACSCMPLT (1 << 0) |
Definition at line 198 of file ll_temac.h.
| #define ISR0_RXCMPLT (1 << 2) |
Definition at line 200 of file ll_temac.h.
| #define ISR0_RXDCMLCK (1 << 6) |
Definition at line 204 of file ll_temac.h.
| #define ISR0_RXFIFOOVR (1 << 4) |
Definition at line 202 of file ll_temac.h.
| #define ISR0_RXREJ (1 << 3) |
Definition at line 201 of file ll_temac.h.
| #define ISR0_TXCMPLT (1 << 5) |
Definition at line 203 of file ll_temac.h.
| #define MULTICAST_CAM_TABLE_NUM 4 |
Definition at line 296 of file ll_temac.h.
| #define RAF0_BCSTREJ (1 << 2) |
Definition at line 194 of file ll_temac.h.
| #define RAF0_MCSTREJ (1 << 1) |
Definition at line 193 of file ll_temac.h.
| #define RAF0_RST (1 << 0) |
Definition at line 192 of file ll_temac.h.
| #define RX_CHNL_CTRL 0x0d /* rw */ |
Definition at line 124 of file ll_temac.h.
| #define RX_CHNL_STS 0x0f /* r */ |
Definition at line 151 of file ll_temac.h.
| #define RX_CURBUF_ADDR 0x09 /* r */ |
Definition at line 120 of file ll_temac.h.
| #define RX_CURBUF_LENGTH 0x0a /* r */ |
Definition at line 121 of file ll_temac.h.
| #define RX_CURDESC_PTR 0x0b /* rw */ |
Definition at line 122 of file ll_temac.h.
| #define RX_IRQ_REG 0x0e /* rw */ |
Definition at line 138 of file ll_temac.h.
| #define RX_NXTDESC_PTR 0x08 /* r */ |
Definition at line 119 of file ll_temac.h.
| #define RX_TAILDESC_PTR 0x0c /* rw */ |
Definition at line 123 of file ll_temac.h.
| #define STS_CTRL_APP0_CMPLT (1 << 28) |
Definition at line 287 of file ll_temac.h.
| #define STS_CTRL_APP0_ENGBUSY (1 << 25) |
Definition at line 290 of file ll_temac.h.
| #define STS_CTRL_APP0_ENGRST (1 << 24) |
Definition at line 292 of file ll_temac.h.
| #define STS_CTRL_APP0_EOP (1 << 26) |
Definition at line 289 of file ll_temac.h.
| #define STS_CTRL_APP0_ERR (1 << 31) |
Definition at line 283 of file ll_temac.h.
| #define STS_CTRL_APP0_IRQONEND (1 << 30) |
Definition at line 284 of file ll_temac.h.
| #define STS_CTRL_APP0_SOP (1 << 27) |
Definition at line 288 of file ll_temac.h.
| #define STS_CTRL_APP0_STOPONEND (1 << 29) |
Definition at line 286 of file ll_temac.h.
| #define TEMAC_FEATURE_RX_CSUM (1 << 0) |
Definition at line 299 of file ll_temac.h.
| #define TEMAC_FEATURE_TX_CSUM (1 << 1) |
Definition at line 300 of file ll_temac.h.
| #define TIS_ARIS (1 << 3) |
Definition at line 266 of file ll_temac.h.
| #define TIS_AWIS (1 << 4) |
Definition at line 267 of file ll_temac.h.
| #define TIS_CRIS (1 << 5) |
Definition at line 268 of file ll_temac.h.
| #define TIS_CWIS (1 << 6) |
Definition at line 269 of file ll_temac.h.
| #define TIS_FRIS (1 << 0) |
Definition at line 263 of file ll_temac.h.
| #define TIS_MRIS (1 << 1) |
Definition at line 264 of file ll_temac.h.
| #define TIS_MWIS (1 << 2) |
Definition at line 265 of file ll_temac.h.
| #define TX_CHNL_CTRL 0x05 /* rw */ |
Definition at line 68 of file ll_temac.h.
| #define TX_CHNL_STS 0x07 /* r */ |
Definition at line 99 of file ll_temac.h.
| #define TX_CONTROL_CALC_CSUM_MASK 1 |
Definition at line 294 of file ll_temac.h.
| #define TX_CURBUF_ADDR 0x01 /* r */ |
Definition at line 64 of file ll_temac.h.
| #define TX_CURBUF_LENGTH 0x02 /* r */ |
Definition at line 65 of file ll_temac.h.
| #define TX_CURDESC_PTR 0x03 /* rw */ |
Definition at line 66 of file ll_temac.h.
| #define TX_IRQ_REG 0x06 /* rw */ |
Definition at line 87 of file ll_temac.h.
| #define TX_NXTDESC_PTR 0x00 /* r */ |
Definition at line 63 of file ll_temac.h.
| #define TX_TAILDESC_PTR 0x04 /* rw */ |
Definition at line 67 of file ll_temac.h.
Definition at line 259 of file ll_temac.h.
| #define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */ |
Definition at line 258 of file ll_temac.h.
| #define XTE_CTL0_OFFSET 0x28 |
Definition at line 211 of file ll_temac.h.
Definition at line 246 of file ll_temac.h.
| #define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */ |
Definition at line 247 of file ll_temac.h.
| #define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */ |
Definition at line 248 of file ll_temac.h.
| #define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */ |
Definition at line 249 of file ll_temac.h.
| #define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */ |
Definition at line 245 of file ll_temac.h.
| #define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */ |
Definition at line 244 of file ll_temac.h.
| #define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */ |
Definition at line 240 of file ll_temac.h.
Definition at line 241 of file ll_temac.h.
Definition at line 242 of file ll_temac.h.
| #define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */ |
Definition at line 251 of file ll_temac.h.
Definition at line 15 of file ll_temac.h.
| #define XTE_IER0_OFFSET 0x14 |
Definition at line 207 of file ll_temac.h.
| #define XTE_IFGP0_OFFSET 0x08 |
Definition at line 196 of file ll_temac.h.
| #define XTE_IPR0_OFFSET 0x10 |
Definition at line 206 of file ll_temac.h.
| #define XTE_ISR0_OFFSET 0x0c |
Definition at line 197 of file ll_temac.h.
| #define XTE_JUMBO_MTU 9000 |
Definition at line 17 of file ll_temac.h.
| #define XTE_LSW0_OFFSET 0x24 |
Definition at line 210 of file ll_temac.h.
| #define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */ |
Definition at line 256 of file ll_temac.h.
| #define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */ |
Definition at line 257 of file ll_temac.h.
| #define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE) |
Definition at line 18 of file ll_temac.h.
| #define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */ |
Definition at line 252 of file ll_temac.h.
| #define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */ |
MII Mamagement Control register (MGTCR)
Definition at line 274 of file ll_temac.h.
| #define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */ |
Definition at line 275 of file ll_temac.h.
| #define XTE_MSW0_OFFSET 0x20 |
Definition at line 209 of file ll_temac.h.
| #define XTE_OPTION_DEFAULTS |
Definition at line 56 of file ll_temac.h.
| #define XTE_OPTION_FCS_INSERT (1 << 6) |
Definition at line 40 of file ll_temac.h.
| #define XTE_OPTION_FCS_STRIP (1 << 5) |
Definition at line 37 of file ll_temac.h.
| #define XTE_OPTION_FLOW_CONTROL (1 << 4) |
Definition at line 33 of file ll_temac.h.
| #define XTE_OPTION_JUMBO (1 << 1) |
Definition at line 27 of file ll_temac.h.
| #define XTE_OPTION_LENTYPE_ERR (1 << 7) |
Definition at line 47 of file ll_temac.h.
| #define XTE_OPTION_PROMISC (1 << 0) |
Definition at line 24 of file ll_temac.h.
| #define XTE_OPTION_RXEN (1 << 12) |
Definition at line 53 of file ll_temac.h.
| #define XTE_OPTION_TXEN (1 << 11) |
Definition at line 50 of file ll_temac.h.
| #define XTE_OPTION_VLAN (1 << 2) |
Definition at line 30 of file ll_temac.h.
| #define XTE_RAF0_OFFSET 0x00 |
Definition at line 191 of file ll_temac.h.
| #define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000) |
Definition at line 218 of file ll_temac.h.
| #define XTE_RDY0_OFFSET 0x2c |
Definition at line 212 of file ll_temac.h.
| #define XTE_RSE_CFG_RR_MASK 0x0020 |
Definition at line 216 of file ll_temac.h.
| #define XTE_RSE_CFG_WR_MASK 0x0040 |
Definition at line 217 of file ll_temac.h.
| #define XTE_RSE_MIIM_RR_MASK 0x0002 |
Definition at line 214 of file ll_temac.h.
| #define XTE_RSE_MIIM_WR_MASK 0x0004 |
Definition at line 215 of file ll_temac.h.
| #define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */ |
Definition at line 222 of file ll_temac.h.
| #define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */ |
Definition at line 223 of file ll_temac.h.
| #define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */ |
Definition at line 227 of file ll_temac.h.
| #define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */ |
Definition at line 226 of file ll_temac.h.
| #define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */ |
Definition at line 229 of file ll_temac.h.
Definition at line 225 of file ll_temac.h.
Definition at line 230 of file ll_temac.h.
| #define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */ |
Definition at line 224 of file ll_temac.h.
| #define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */ |
Definition at line 228 of file ll_temac.h.
| #define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */ |
Definition at line 271 of file ll_temac.h.
| #define XTE_TIS_OFFSET 0x000003A0 |
Definition at line 262 of file ll_temac.h.
| #define XTE_TPF0_OFFSET 0x04 |
Definition at line 195 of file ll_temac.h.
Definition at line 16 of file ll_temac.h.
| #define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */ |
Definition at line 232 of file ll_temac.h.
| #define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */ |
Definition at line 236 of file ll_temac.h.
| #define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */ |
Definition at line 235 of file ll_temac.h.
| #define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */ |
Definition at line 238 of file ll_temac.h.
Definition at line 234 of file ll_temac.h.
| #define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */ |
Definition at line 233 of file ll_temac.h.
| #define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */ |
Definition at line 237 of file ll_temac.h.
| #define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */ |
Definition at line 253 of file ll_temac.h.
| #define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */ |
Definition at line 254 of file ll_temac.h.
| int temac_indirect_busywait | ( | struct temac_local * | lp | ) |
Definition at line 73 of file ll_temac_main.c.
| u32 temac_indirect_in32 | ( | struct temac_local * | lp, |
| int | reg | ||
| ) |
temac_indirect_in32
lp->indirect_mutex must be held when calling this function
Definition at line 92 of file ll_temac_main.c.
| void temac_indirect_out32 | ( | struct temac_local * | lp, |
| int | reg, | ||
| u32 | value | ||
| ) |
temac_indirect_out32
lp->indirect_mutex must be held when calling this function
Definition at line 111 of file ll_temac_main.c.
| u32 temac_ior | ( | struct temac_local * | lp, |
| int | offset | ||
| ) |
Definition at line 63 of file ll_temac_main.c.
| void temac_iow | ( | struct temac_local * | lp, |
| int | offset, | ||
| u32 | value | ||
| ) |
Definition at line 68 of file ll_temac_main.c.
| int temac_mdio_setup | ( | struct temac_local * | lp, |
| struct device_node * | np | ||
| ) |
Definition at line 59 of file ll_temac_mdio.c.
| void temac_mdio_teardown | ( | struct temac_local * | lp | ) |
Definition at line 115 of file ll_temac_mdio.c.
1.8.2