Linux Kernel  3.7.1
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lm49453.c
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1 /*
2  * lm49453.c - LM49453 ALSA Soc Audio driver
3  *
4  * Copyright (c) 2012 Texas Instruments, Inc
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * Initially based on sound/soc/codecs/wm8350.c
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/tlv.h>
28 #include <sound/jack.h>
29 #include <sound/initval.h>
30 #include <asm/div64.h>
31 #include "lm49453.h"
32 
33 static struct reg_default lm49453_reg_defs[] = {
34  { 0, 0x00 },
35  { 1, 0x00 },
36  { 2, 0x00 },
37  { 3, 0x00 },
38  { 4, 0x00 },
39  { 5, 0x00 },
40  { 6, 0x00 },
41  { 7, 0x00 },
42  { 8, 0x00 },
43  { 9, 0x00 },
44  { 10, 0x00 },
45  { 11, 0x00 },
46  { 12, 0x00 },
47  { 13, 0x00 },
48  { 14, 0x00 },
49  { 15, 0x00 },
50  { 16, 0x00 },
51  { 17, 0x00 },
52  { 18, 0x00 },
53  { 19, 0x00 },
54  { 20, 0x00 },
55  { 21, 0x00 },
56  { 22, 0x00 },
57  { 23, 0x00 },
58  { 32, 0x00 },
59  { 33, 0x00 },
60  { 35, 0x00 },
61  { 36, 0x00 },
62  { 37, 0x00 },
63  { 46, 0x00 },
64  { 48, 0x00 },
65  { 49, 0x00 },
66  { 51, 0x00 },
67  { 56, 0x00 },
68  { 58, 0x00 },
69  { 59, 0x00 },
70  { 60, 0x00 },
71  { 61, 0x00 },
72  { 62, 0x00 },
73  { 63, 0x00 },
74  { 64, 0x00 },
75  { 65, 0x00 },
76  { 66, 0x00 },
77  { 67, 0x00 },
78  { 68, 0x00 },
79  { 69, 0x00 },
80  { 70, 0x00 },
81  { 71, 0x00 },
82  { 72, 0x00 },
83  { 73, 0x00 },
84  { 74, 0x00 },
85  { 75, 0x00 },
86  { 76, 0x00 },
87  { 77, 0x00 },
88  { 78, 0x00 },
89  { 79, 0x00 },
90  { 80, 0x00 },
91  { 81, 0x00 },
92  { 82, 0x00 },
93  { 83, 0x00 },
94  { 85, 0x00 },
95  { 85, 0x00 },
96  { 86, 0x00 },
97  { 87, 0x00 },
98  { 88, 0x00 },
99  { 89, 0x00 },
100  { 90, 0x00 },
101  { 91, 0x00 },
102  { 92, 0x00 },
103  { 93, 0x00 },
104  { 94, 0x00 },
105  { 95, 0x00 },
106  { 96, 0x01 },
107  { 97, 0x00 },
108  { 98, 0x00 },
109  { 99, 0x00 },
110  { 100, 0x00 },
111  { 101, 0x00 },
112  { 102, 0x00 },
113  { 103, 0x01 },
114  { 105, 0x01 },
115  { 106, 0x00 },
116  { 107, 0x01 },
117  { 107, 0x00 },
118  { 108, 0x00 },
119  { 109, 0x00 },
120  { 110, 0x00 },
121  { 111, 0x02 },
122  { 112, 0x02 },
123  { 113, 0x00 },
124  { 121, 0x80 },
125  { 122, 0xBB },
126  { 123, 0x80 },
127  { 124, 0xBB },
128  { 128, 0x00 },
129  { 130, 0x00 },
130  { 131, 0x00 },
131  { 132, 0x00 },
132  { 133, 0x0A },
133  { 134, 0x0A },
134  { 135, 0x0A },
135  { 136, 0x0F },
136  { 137, 0x00 },
137  { 138, 0x73 },
138  { 139, 0x33 },
139  { 140, 0x73 },
140  { 141, 0x33 },
141  { 142, 0x73 },
142  { 143, 0x33 },
143  { 144, 0x73 },
144  { 145, 0x33 },
145  { 146, 0x73 },
146  { 147, 0x33 },
147  { 148, 0x73 },
148  { 149, 0x33 },
149  { 150, 0x73 },
150  { 151, 0x33 },
151  { 152, 0x00 },
152  { 153, 0x00 },
153  { 154, 0x00 },
154  { 155, 0x00 },
155  { 176, 0x00 },
156  { 177, 0x00 },
157  { 178, 0x00 },
158  { 179, 0x00 },
159  { 180, 0x00 },
160  { 181, 0x00 },
161  { 182, 0x00 },
162  { 183, 0x00 },
163  { 184, 0x00 },
164  { 185, 0x00 },
165  { 186, 0x00 },
166  { 189, 0x00 },
167  { 188, 0x00 },
168  { 194, 0x00 },
169  { 195, 0x00 },
170  { 196, 0x00 },
171  { 197, 0x00 },
172  { 200, 0x00 },
173  { 201, 0x00 },
174  { 202, 0x00 },
175  { 203, 0x00 },
176  { 204, 0x00 },
177  { 205, 0x00 },
178  { 208, 0x00 },
179  { 209, 0x00 },
180  { 210, 0x00 },
181  { 211, 0x00 },
182  { 213, 0x00 },
183  { 214, 0x00 },
184  { 215, 0x00 },
185  { 216, 0x00 },
186  { 217, 0x00 },
187  { 218, 0x00 },
188  { 219, 0x00 },
189  { 221, 0x00 },
190  { 222, 0x00 },
191  { 224, 0x00 },
192  { 225, 0x00 },
193  { 226, 0x00 },
194  { 227, 0x00 },
195  { 228, 0x00 },
196  { 229, 0x00 },
197  { 230, 0x13 },
198  { 231, 0x00 },
199  { 232, 0x80 },
200  { 233, 0x0C },
201  { 234, 0xDD },
202  { 235, 0x00 },
203  { 236, 0x04 },
204  { 237, 0x00 },
205  { 238, 0x00 },
206  { 239, 0x00 },
207  { 240, 0x00 },
208  { 241, 0x00 },
209  { 242, 0x00 },
210  { 243, 0x00 },
211  { 244, 0x00 },
212  { 245, 0x00 },
213  { 248, 0x00 },
214  { 249, 0x00 },
215  { 254, 0x00 },
216  { 255, 0x00 },
217 };
218 
219 /* codec private data */
220 struct lm49453_priv {
221  struct regmap *regmap;
222  int fs_rate;
223 };
224 
225 /* capture path controls */
226 
227 static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
228 
229 static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
230  lm49453_mic2mode_text);
231 
232 static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
233 
234 static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
235  LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
236  7, lm49453_dmic_cfg_text);
237 
238 static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
239  LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
240  7, lm49453_dmic_cfg_text);
241 
242 /* MUX Controls */
243 static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
244 
245 static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
246 
247 static const struct soc_enum lm49453_adcl_enum =
248  SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
249  ARRAY_SIZE(lm49453_adcl_mux_text),
250  lm49453_adcl_mux_text);
251 
252 static const struct soc_enum lm49453_adcr_enum =
253  SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
254  ARRAY_SIZE(lm49453_adcr_mux_text),
255  lm49453_adcr_mux_text);
256 
257 static const struct snd_kcontrol_new lm49453_adcl_mux_control =
258  SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
259 
260 static const struct snd_kcontrol_new lm49453_adcr_mux_control =
261  SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
262 
263 static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
264 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
265 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
266 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
267 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
268 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
269 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
270 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
271 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
272 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
273 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
274 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
275 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
276 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
277 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
278 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
279 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
280 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
281 };
282 
283 static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
284 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
285 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
286 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
287 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
288 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
289 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
290 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
291 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
292 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
293 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
294 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
295 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
296 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
297 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
298 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
299 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
300 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
301 };
302 
303 static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
304 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
305 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
306 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
307 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
308 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
309 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
310 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
311 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
312 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
313 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
314 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
315 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
316 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
317 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
318 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
319 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
320 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
321 };
322 
323 static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
324 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
325 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
326 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
327 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
328 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
329 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
330 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
331 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
332 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
333 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
334 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
335 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
336 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
337 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
338 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
339 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
340 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
341 };
342 
343 static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
344 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
345 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
346 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
347 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
348 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
349 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
350 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
351 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
352 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
353 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
354 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
355 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
356 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
357 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
358 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
359 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
360 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
361 };
362 
363 static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
364 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
365 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
366 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
367 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
368 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
369 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
370 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
371 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
372 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
373 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
374 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
375 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
376 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
377 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
378 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
379 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
380 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
381 };
382 
383 static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
384 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
385 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
386 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
387 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
388 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
389 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
390 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
391 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
392 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
393 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
394 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
395 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
396 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
397 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
398 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
399 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
400 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
401 };
402 
403 static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
404 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
405 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
406 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
407 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
408 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
409 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
410 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
411 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
412 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
413 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
414 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
415 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
416 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
417 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
418 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
419 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
420 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
421 };
422 
423 static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
424 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
425 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
426 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
427 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
428 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
429 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
430 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
431 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
432 };
433 
434 static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
435 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
436 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
437 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
438 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
439 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
440 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
441 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
442 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
443 };
444 
445 static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
446 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
447 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
448 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
449 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
450 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
451 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
452 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
453 };
454 
455 static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
456 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
457 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
458 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
459 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
460 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
461 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
462 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
463 };
464 
465 static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
466 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
467 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
468 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
469 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
470 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
471 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
472 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
473 };
474 
475 static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
476 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
477 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
478 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
479 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
480 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
481 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
482 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
483 };
484 
485 static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
486 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
487 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
488 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
489 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
490 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
491 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
492 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
493 };
494 
495 static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
496 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
497 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
498 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
499 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
500 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
501 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
502 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
503 };
504 
505 static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
506 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
507 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
508 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
509 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
510 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
511 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
512 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
513 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
514 };
515 
516 static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
517 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
518 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
519 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
520 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
521 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
522 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
523 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
524 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
525 };
526 
527 /* TLV Declarations */
528 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7650, 150, 1);
529 static const DECLARE_TLV_DB_SCALE(port_tlv, 0, 600, 0);
530 
531 static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
532 /* Sidetone supports mono only */
533 SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
534  0, 0x3F, 0, digital_tlv),
535 SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
536  0, 0x3F, 0, digital_tlv),
537 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
538  0, 0x3F, 0, digital_tlv),
539 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
540  0, 0x3F, 0, digital_tlv),
541 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
542  0, 0x3F, 0, digital_tlv),
543 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
544  0, 0x3F, 0, digital_tlv),
545 };
546 
547 static const struct snd_kcontrol_new lm49453_snd_controls[] = {
548  /* mic1 and mic2 supports mono only */
549  SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_ADC_LEVELL_REG, 0, 6,
550  0, digital_tlv),
551  SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_ADC_LEVELR_REG, 0, 6,
552  0, digital_tlv),
553 
554  SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
555  LM49453_P0_DMIC1_LEVELR_REG, 0, 6, 0, digital_tlv),
556  SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
557  LM49453_P0_DMIC2_LEVELR_REG, 0, 6, 0, digital_tlv),
558 
559  SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
560  SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
561  SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
562 
563  /* Capture path filter enable */
564  SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
565  0, 1, 0),
566  SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
567  1, 1, 0),
568  SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
569  2, 1, 0),
570 
571  SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
572  LM49453_P0_DAC_HP_LEVELR_REG, 0, 6, 0, digital_tlv),
573  SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
574  LM49453_P0_DAC_LO_LEVELR_REG, 0, 6, 0, digital_tlv),
575  SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
576  LM49453_P0_DAC_LS_LEVELR_REG, 0, 6, 0, digital_tlv),
577  SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
578  LM49453_P0_DAC_HA_LEVELR_REG, 0, 6, 0, digital_tlv),
579 
580  SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
581  0, 6, 0, digital_tlv),
582 
583  SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
584  0, 3, 0, port_tlv),
585  SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
586  2, 3, 0, port_tlv),
587  SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
588  4, 3, 0, port_tlv),
589  SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
590  6, 3, 0, port_tlv),
591  SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
592  0, 3, 0, port_tlv),
593  SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
594  2, 3, 0, port_tlv),
595  SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
596  4, 3, 0, port_tlv),
597  SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
598  6, 3, 0, port_tlv),
599 
600  SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
601  0, 3, 0, port_tlv),
602  SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
603  2, 3, 0, port_tlv),
604 
605  SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
606  1, 1, 0),
607  SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
608  1, 1, 0),
609  SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
610  2, 1, 0),
611  SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
612  2, 1, 0)
613 
614 };
615 
616 /* DAPM widgets */
617 static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
618 
619  /* All end points HP,EP, LS, Lineout and Haptic */
620  SND_SOC_DAPM_OUTPUT("HPOUTL"),
621  SND_SOC_DAPM_OUTPUT("HPOUTR"),
622  SND_SOC_DAPM_OUTPUT("EPOUT"),
623  SND_SOC_DAPM_OUTPUT("LSOUTL"),
624  SND_SOC_DAPM_OUTPUT("LSOUTR"),
625  SND_SOC_DAPM_OUTPUT("LOOUTR"),
626  SND_SOC_DAPM_OUTPUT("LOOUTL"),
627  SND_SOC_DAPM_OUTPUT("HAOUTL"),
628  SND_SOC_DAPM_OUTPUT("HAOUTR"),
629 
630  SND_SOC_DAPM_INPUT("AMIC1"),
631  SND_SOC_DAPM_INPUT("AMIC2"),
632  SND_SOC_DAPM_INPUT("DMIC1DAT"),
633  SND_SOC_DAPM_INPUT("DMIC2DAT"),
634  SND_SOC_DAPM_INPUT("AUXL"),
635  SND_SOC_DAPM_INPUT("AUXR"),
636 
637  SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
638  SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
639  SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
640  SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
641  SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
642  SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
643  SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
644  SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
645  SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
646  SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
647 
648  SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
649  SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
650 
651  /* playback path driver enables */
652  SND_SOC_DAPM_OUT_DRV("Headset Switch",
653  LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
654  SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
655  LM49453_P0_EP_REG, 0, 0, NULL, 0),
656  SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
657  LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
658  SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
659  LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
660  SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
661  LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
662  SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
663  LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
664 
665  /* DAC */
666  SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
667  SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
668  SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
669  SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
670  SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
671  SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
672  SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
673  SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
674 
675 
676  SND_SOC_DAPM_PGA("AUXL Input",
677  LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
678  SND_SOC_DAPM_PGA("AUXR Input",
679  LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
680 
681  SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
682 
683  /* ADC */
684  SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
685  SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
686  SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
687  SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
688 
689  SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
690  SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
691 
692  SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
693  &lm49453_adcl_mux_control),
694  SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
695  &lm49453_adcr_mux_control),
696 
697  SND_SOC_DAPM_MUX("Mic1 Input",
698  SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
699 
700  SND_SOC_DAPM_MUX("Mic2 Input",
701  SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
702 
703  /* AIF */
704  SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
705  LM49453_P0_PULL_CONFIG1_REG, 2, 0),
706  SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
707  LM49453_P0_PULL_CONFIG1_REG, 6, 0),
708 
709  SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
710  LM49453_P0_PULL_CONFIG1_REG, 3, 0),
711  SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
712  LM49453_P0_PULL_CONFIG1_REG, 7, 0),
713 
714  /* Port1 TX controls */
715  SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
716  SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
717  SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
718  SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
719  SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
720  SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
721  SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
722  SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
723 
724  /* Port2 TX controls */
725  SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
726  SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
727 
728  /* Sidetone Mixer */
729  SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
730  lm49453_sidetone_mixer_controls,
731  ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
732 
733  /* DAC MIXERS */
734  SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
735  lm49453_headset_left_mixer,
736  ARRAY_SIZE(lm49453_headset_left_mixer)),
737  SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
738  lm49453_headset_right_mixer,
739  ARRAY_SIZE(lm49453_headset_right_mixer)),
740  SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
741  lm49453_lineout_left_mixer,
742  ARRAY_SIZE(lm49453_lineout_left_mixer)),
743  SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
744  lm49453_lineout_right_mixer,
745  ARRAY_SIZE(lm49453_lineout_right_mixer)),
746  SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
747  lm49453_speaker_left_mixer,
748  ARRAY_SIZE(lm49453_speaker_left_mixer)),
749  SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
750  lm49453_speaker_right_mixer,
751  ARRAY_SIZE(lm49453_speaker_right_mixer)),
752  SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
753  lm49453_haptic_left_mixer,
754  ARRAY_SIZE(lm49453_haptic_left_mixer)),
755  SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
756  lm49453_haptic_right_mixer,
757  ARRAY_SIZE(lm49453_haptic_right_mixer)),
758 
759  /* Capture Mixer */
760  SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
761  lm49453_port1_tx1_mixer,
762  ARRAY_SIZE(lm49453_port1_tx1_mixer)),
763  SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
764  lm49453_port1_tx2_mixer,
765  ARRAY_SIZE(lm49453_port1_tx2_mixer)),
766  SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
767  lm49453_port1_tx3_mixer,
768  ARRAY_SIZE(lm49453_port1_tx3_mixer)),
769  SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
770  lm49453_port1_tx4_mixer,
771  ARRAY_SIZE(lm49453_port1_tx4_mixer)),
772  SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
773  lm49453_port1_tx5_mixer,
774  ARRAY_SIZE(lm49453_port1_tx5_mixer)),
775  SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
776  lm49453_port1_tx6_mixer,
777  ARRAY_SIZE(lm49453_port1_tx6_mixer)),
778  SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
779  lm49453_port1_tx7_mixer,
780  ARRAY_SIZE(lm49453_port1_tx7_mixer)),
781  SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
782  lm49453_port1_tx8_mixer,
783  ARRAY_SIZE(lm49453_port1_tx8_mixer)),
784 
785  SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
786  lm49453_port2_tx1_mixer,
787  ARRAY_SIZE(lm49453_port2_tx1_mixer)),
788  SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
789  lm49453_port2_tx2_mixer,
790  ARRAY_SIZE(lm49453_port2_tx2_mixer)),
791 };
792 
793 static const struct snd_soc_dapm_route lm49453_audio_map[] = {
794  /* Port SDI mapping */
795  { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
796  { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
797  { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
798  { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
799  { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
800  { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
801  { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
802  { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
803 
804  { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
805  { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
806 
807  /* HP mapping */
808  { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
809  { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
810  { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
811  { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
812  { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
813  { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
814  { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
815  { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
816 
817  { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
818  { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
819 
820  { "HPL Mixer", "ADCL Switch", "ADC Left" },
821  { "HPL Mixer", "ADCR Switch", "ADC Right" },
822  { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
823  { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
824  { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
825  { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
826  { "HPL Mixer", "Sidetone Switch", "Sidetone" },
827 
828  { "HPL DAC", NULL, "HPL Mixer" },
829 
830  { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
831  { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
832  { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
833  { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
834  { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
835  { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
836  { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
837  { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
838 
839  /* Port 2 */
840  { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
841  { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
842 
843  { "HPR Mixer", "ADCL Switch", "ADC Left" },
844  { "HPR Mixer", "ADCR Switch", "ADC Right" },
845  { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
846  { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
847  { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
848  { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
849  { "HPR Mixer", "Sidetone Switch", "Sidetone" },
850 
851  { "HPR DAC", NULL, "HPR Mixer" },
852 
853  { "HPOUTL", "Headset Switch", "HPL DAC"},
854  { "HPOUTR", "Headset Switch", "HPR DAC"},
855 
856  /* EP map */
857  { "EPOUT", "Earpiece Switch", "HPL DAC" },
858 
859  /* Speaker map */
860  { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
861  { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
862  { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
863  { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
864  { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
865  { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
866  { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
867  { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
868 
869  /* Port 2 */
870  { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
871  { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
872 
873  { "LSL Mixer", "ADCL Switch", "ADC Left" },
874  { "LSL Mixer", "ADCR Switch", "ADC Right" },
875  { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
876  { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
877  { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
878  { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
879  { "LSL Mixer", "Sidetone Switch", "Sidetone" },
880 
881  { "LSL DAC", NULL, "LSL Mixer" },
882 
883  { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
884  { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
885  { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
886  { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
887  { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
888  { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
889  { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
890  { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
891 
892  /* Port 2 */
893  { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
894  { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
895 
896  { "LSR Mixer", "ADCL Switch", "ADC Left" },
897  { "LSR Mixer", "ADCR Switch", "ADC Right" },
898  { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
899  { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
900  { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
901  { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
902  { "LSR Mixer", "Sidetone Switch", "Sidetone" },
903 
904  { "LSR DAC", NULL, "LSR Mixer" },
905 
906  { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
907  { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
908 
909  /* Haptic map */
910  { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
911  { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
912  { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
913  { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
914  { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
915  { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
916  { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
917  { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
918 
919  /* Port 2 */
920  { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
921  { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
922 
923  { "HAL Mixer", "ADCL Switch", "ADC Left" },
924  { "HAL Mixer", "ADCR Switch", "ADC Right" },
925  { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
926  { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
927  { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
928  { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
929  { "HAL Mixer", "Sidetone Switch", "Sidetone" },
930 
931  { "HAL DAC", NULL, "HAL Mixer" },
932 
933  { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
934  { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
935  { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
936  { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
937  { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
938  { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
939  { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
940  { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
941 
942  /* Port 2 */
943  { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
944  { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
945 
946  { "HAR Mixer", "ADCL Switch", "ADC Left" },
947  { "HAR Mixer", "ADCR Switch", "ADC Right" },
948  { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
949  { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
950  { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
951  { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
952  { "HAR Mixer", "Sideton Switch", "Sidetone" },
953 
954  { "HAR DAC", NULL, "HAR Mixer" },
955 
956  { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
957  { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
958 
959  /* Lineout map */
960  { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
961  { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
962  { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
963  { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
964  { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
965  { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
966  { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
967  { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
968 
969  /* Port 2 */
970  { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
971  { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
972 
973  { "LOL Mixer", "ADCL Switch", "ADC Left" },
974  { "LOL Mixer", "ADCR Switch", "ADC Right" },
975  { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
976  { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
977  { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
978  { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
979  { "LOL Mixer", "Sidetone Switch", "Sidetone" },
980 
981  { "LOL DAC", NULL, "LOL Mixer" },
982 
983  { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
984  { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
985  { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
986  { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
987  { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
988  { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
989  { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
990  { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
991 
992  /* Port 2 */
993  { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
994  { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
995 
996  { "LOR Mixer", "ADCL Switch", "ADC Left" },
997  { "LOR Mixer", "ADCR Switch", "ADC Right" },
998  { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
999  { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
1000  { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
1001  { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
1002  { "LOR Mixer", "Sidetone Switch", "Sidetone" },
1003 
1004  { "LOR DAC", NULL, "LOR Mixer" },
1005 
1006  { "LOOUTL", NULL, "LOL DAC" },
1007  { "LOOUTR", NULL, "LOR DAC" },
1008 
1009  /* TX map */
1010  /* Port1 mappings */
1011  { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
1012  { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
1013  { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1014  { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1015  { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1016  { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1017 
1018  { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
1019  { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
1020  { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1021  { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1022  { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1023  { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1024 
1025  { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
1026  { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1027  { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1028  { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1029  { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1030  { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1031 
1032  { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1033  { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1034  { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1035  { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1036  { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1037  { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1038 
1039  { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1040  { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1041  { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1042  { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1043  { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1044  { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1045 
1046  { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1047  { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1048  { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1049  { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1050  { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1051  { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1052 
1053  { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1054  { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1055  { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1056  { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1057  { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1058  { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1059 
1060  { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1061  { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1062  { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1063  { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1064  { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1065  { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1066 
1067  { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1068  { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1069  { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1070  { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1071  { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1072  { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1073 
1074  { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1075  { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1076  { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1077  { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1078  { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1079  { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1080 
1081  { "P1_1_TX", NULL, "Port1_1 Mixer" },
1082  { "P1_2_TX", NULL, "Port1_2 Mixer" },
1083  { "P1_3_TX", NULL, "Port1_3 Mixer" },
1084  { "P1_4_TX", NULL, "Port1_4 Mixer" },
1085  { "P1_5_TX", NULL, "Port1_5 Mixer" },
1086  { "P1_6_TX", NULL, "Port1_6 Mixer" },
1087  { "P1_7_TX", NULL, "Port1_7 Mixer" },
1088  { "P1_8_TX", NULL, "Port1_8 Mixer" },
1089 
1090  { "P2_1_TX", NULL, "Port2_1 Mixer" },
1091  { "P2_2_TX", NULL, "Port2_2 Mixer" },
1092 
1093  { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1094  { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1095  { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1096  { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1097  { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1098  { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1099  { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1100  { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1101 
1102  { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1103  { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1104 
1105  { "Mic1 Input", NULL, "AMIC1" },
1106  { "Mic2 Input", NULL, "AMIC2" },
1107 
1108  { "AUXL Input", NULL, "AUXL" },
1109  { "AUXR Input", NULL, "AUXR" },
1110 
1111  /* AUX connections */
1112  { "ADCL Mux", "Aux_L", "AUXL Input" },
1113  { "ADCL Mux", "MIC1", "Mic1 Input" },
1114 
1115  { "ADCR Mux", "Aux_R", "AUXR Input" },
1116  { "ADCR Mux", "MIC2", "Mic2 Input" },
1117 
1118  /* ADC connection */
1119  { "ADC Left", NULL, "ADCL Mux"},
1120  { "ADC Right", NULL, "ADCR Mux"},
1121 
1122  { "DMIC1 Left", NULL, "DMIC1DAT"},
1123  { "DMIC1 Right", NULL, "DMIC1DAT"},
1124  { "DMIC2 Left", NULL, "DMIC2DAT"},
1125  { "DMIC2 Right", NULL, "DMIC2DAT"},
1126 
1127  /* Sidetone map */
1128  { "Sidetone Mixer", NULL, "ADC Left" },
1129  { "Sidetone Mixer", NULL, "ADC Right" },
1130  { "Sidetone Mixer", NULL, "DMIC1 Left" },
1131  { "Sidetone Mixer", NULL, "DMIC1 Right" },
1132  { "Sidetone Mixer", NULL, "DMIC2 Left" },
1133  { "Sidetone Mixer", NULL, "DMIC2 Right" },
1134 
1135  { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1136 };
1137 
1138 static int lm49453_hw_params(struct snd_pcm_substream *substream,
1139  struct snd_pcm_hw_params *params,
1140  struct snd_soc_dai *dai)
1141 {
1142  struct snd_soc_codec *codec = dai->codec;
1143  struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1144  u16 clk_div = 0;
1145 
1146  lm49453->fs_rate = params_rate(params);
1147 
1148  /* Setting DAC clock dividers based on substream sample rate. */
1149  switch (lm49453->fs_rate) {
1150  case 8000:
1151  case 16000:
1152  case 32000:
1153  case 24000:
1154  case 48000:
1155  clk_div = 256;
1156  break;
1157  case 11025:
1158  case 22050:
1159  case 44100:
1160  clk_div = 216;
1161  break;
1162  case 96000:
1163  clk_div = 127;
1164  break;
1165  default:
1166  return -EINVAL;
1167  }
1168 
1169  snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1170  snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1171 
1172  return 0;
1173 }
1174 
1175 static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1176 {
1177  struct snd_soc_codec *codec = codec_dai->codec;
1178 
1179  u16 aif_val;
1180  int mode = 0;
1181  int clk_phase = 0;
1182  int clk_shift = 0;
1183 
1184  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1185  case SND_SOC_DAIFMT_CBS_CFS:
1186  aif_val = 0;
1187  break;
1188  case SND_SOC_DAIFMT_CBS_CFM:
1189  aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1190  break;
1191  case SND_SOC_DAIFMT_CBM_CFS:
1192  aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
1193  break;
1194  case SND_SOC_DAIFMT_CBM_CFM:
1195  aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1196  LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1197  break;
1198  default:
1199  return -EINVAL;
1200  }
1201 
1202 
1203  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1204  case SND_SOC_DAIFMT_I2S:
1205  break;
1206  case SND_SOC_DAIFMT_DSP_A:
1207  mode = 1;
1208  clk_phase = (1 << 5);
1209  clk_shift = 1;
1210  break;
1211  case SND_SOC_DAIFMT_DSP_B:
1212  mode = 1;
1213  clk_phase = (1 << 5);
1214  clk_shift = 0;
1215  break;
1216  default:
1217  return -EINVAL;
1218  }
1219 
1220  snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1221  LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(1)|BIT(5),
1222  (aif_val | mode | clk_phase));
1223 
1224  snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1225 
1226  return 0;
1227 }
1228 
1229 static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1230  unsigned int freq, int dir)
1231 {
1232  struct snd_soc_codec *codec = dai->codec;
1233  u16 pll_clk = 0;
1234 
1235  switch (freq) {
1236  case 12288000:
1237  case 26000000:
1238  case 19200000:
1239  /* pll clk slection */
1240  pll_clk = 0;
1241  break;
1242  case 48000:
1243  case 32576:
1244  /* fll clk slection */
1245  pll_clk = BIT(4);
1246  return 0;
1247  default:
1248  return -EINVAL;
1249  }
1250 
1251  snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1252 
1253  return 0;
1254 }
1255 
1256 static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1257 {
1258  snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1259  (mute ? (BIT(1)|BIT(0)) : 0));
1260  return 0;
1261 }
1262 
1263 static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1264 {
1265  snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1266  (mute ? (BIT(3)|BIT(2)) : 0));
1267  return 0;
1268 }
1269 
1270 static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1271 {
1272  snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1273  (mute ? (BIT(5)|BIT(4)) : 0));
1274  return 0;
1275 }
1276 
1277 static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1278 {
1279  snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1280  (mute ? BIT(4) : 0));
1281  return 0;
1282 }
1283 
1284 static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1285 {
1286  snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1287  (mute ? (BIT(7)|BIT(6)) : 0));
1288  return 0;
1289 }
1290 
1291 static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1292  enum snd_soc_bias_level level)
1293 {
1294  struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1295 
1296  switch (level) {
1297  case SND_SOC_BIAS_ON:
1298  case SND_SOC_BIAS_PREPARE:
1299  break;
1300 
1301  case SND_SOC_BIAS_STANDBY:
1302  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1303  regcache_sync(lm49453->regmap);
1304 
1305  snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1306  LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1307  break;
1308 
1309  case SND_SOC_BIAS_OFF:
1310  snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1311  LM49453_PMC_SETUP_CHIP_EN, 0);
1312  break;
1313  }
1314 
1315  codec->dapm.bias_level = level;
1316 
1317  return 0;
1318 }
1319 
1320 /* Formates supported by LM49453 driver. */
1321 #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1322  SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1323 
1324 static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1325  .hw_params = lm49453_hw_params,
1326  .set_sysclk = lm49453_set_dai_sysclk,
1327  .set_fmt = lm49453_set_dai_fmt,
1328  .digital_mute = lm49453_hp_mute,
1329 };
1330 
1331 static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1332  .hw_params = lm49453_hw_params,
1333  .set_sysclk = lm49453_set_dai_sysclk,
1334  .set_fmt = lm49453_set_dai_fmt,
1335  .digital_mute = lm49453_ls_mute,
1336 };
1337 
1338 static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1339  .hw_params = lm49453_hw_params,
1340  .set_sysclk = lm49453_set_dai_sysclk,
1341  .set_fmt = lm49453_set_dai_fmt,
1342  .digital_mute = lm49453_ha_mute,
1343 };
1344 
1345 static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1346  .hw_params = lm49453_hw_params,
1347  .set_sysclk = lm49453_set_dai_sysclk,
1348  .set_fmt = lm49453_set_dai_fmt,
1349  .digital_mute = lm49453_ep_mute,
1350 };
1351 
1352 static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1353  .hw_params = lm49453_hw_params,
1354  .set_sysclk = lm49453_set_dai_sysclk,
1355  .set_fmt = lm49453_set_dai_fmt,
1356  .digital_mute = lm49453_lo_mute,
1357 };
1358 
1359 /* LM49453 dai structure. */
1360 static struct snd_soc_dai_driver lm49453_dai[] = {
1361  {
1362  .name = "LM49453 Headset",
1363  .playback = {
1364  .stream_name = "Headset",
1365  .channels_min = 2,
1366  .channels_max = 2,
1367  .rates = SNDRV_PCM_RATE_8000_192000,
1368  .formats = LM49453_FORMATS,
1369  },
1370  .capture = {
1371  .stream_name = "Capture",
1372  .channels_min = 1,
1373  .channels_max = 5,
1374  .rates = SNDRV_PCM_RATE_8000_192000,
1375  .formats = LM49453_FORMATS,
1376  },
1377  .ops = &lm49453_headset_dai_ops,
1378  .symmetric_rates = 1,
1379  },
1380  {
1381  .name = "LM49453 Speaker",
1382  .playback = {
1383  .stream_name = "Speaker",
1384  .channels_min = 2,
1385  .channels_max = 2,
1386  .rates = SNDRV_PCM_RATE_8000_192000,
1387  .formats = LM49453_FORMATS,
1388  },
1389  .ops = &lm49453_speaker_dai_ops,
1390  },
1391  {
1392  .name = "LM49453 Haptic",
1393  .playback = {
1394  .stream_name = "Haptic",
1395  .channels_min = 2,
1396  .channels_max = 2,
1397  .rates = SNDRV_PCM_RATE_8000_192000,
1398  .formats = LM49453_FORMATS,
1399  },
1400  .ops = &lm49453_haptic_dai_ops,
1401  },
1402  {
1403  .name = "LM49453 Earpiece",
1404  .playback = {
1405  .stream_name = "Earpiece",
1406  .channels_min = 1,
1407  .channels_max = 1,
1408  .rates = SNDRV_PCM_RATE_8000_192000,
1409  .formats = LM49453_FORMATS,
1410  },
1411  .ops = &lm49453_ep_dai_ops,
1412  },
1413  {
1414  .name = "LM49453 line out",
1415  .playback = {
1416  .stream_name = "Lineout",
1417  .channels_min = 2,
1418  .channels_max = 2,
1419  .rates = SNDRV_PCM_RATE_8000_192000,
1420  .formats = LM49453_FORMATS,
1421  },
1422  .ops = &lm49453_lineout_dai_ops,
1423  },
1424 };
1425 
1426 static int lm49453_suspend(struct snd_soc_codec *codec)
1427 {
1428  lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1429  return 0;
1430 }
1431 
1432 static int lm49453_resume(struct snd_soc_codec *codec)
1433 {
1434  lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1435  return 0;
1436 }
1437 
1438 static int lm49453_probe(struct snd_soc_codec *codec)
1439 {
1440  struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1441  int ret = 0;
1442 
1443  codec->control_data = lm49453->regmap;
1444 
1445  ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1446  if (ret < 0) {
1447  dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1448  return ret;
1449  }
1450 
1451  return 0;
1452 }
1453 
1454 /* power down chip */
1455 static int lm49453_remove(struct snd_soc_codec *codec)
1456 {
1457  lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1458  return 0;
1459 }
1460 
1461 static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1462  .probe = lm49453_probe,
1463  .remove = lm49453_remove,
1464  .suspend = lm49453_suspend,
1465  .resume = lm49453_resume,
1466  .set_bias_level = lm49453_set_bias_level,
1467  .controls = lm49453_snd_controls,
1468  .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1469  .dapm_widgets = lm49453_dapm_widgets,
1470  .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1471  .dapm_routes = lm49453_audio_map,
1472  .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1473  .idle_bias_off = true,
1474 };
1475 
1476 static const struct regmap_config lm49453_regmap_config = {
1477  .reg_bits = 8,
1478  .val_bits = 8,
1479 
1480  .max_register = LM49453_MAX_REGISTER,
1481  .reg_defaults = lm49453_reg_defs,
1482  .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1483  .cache_type = REGCACHE_RBTREE,
1484 };
1485 
1486 static __devinit int lm49453_i2c_probe(struct i2c_client *i2c,
1487  const struct i2c_device_id *id)
1488 {
1489  struct lm49453_priv *lm49453;
1490  int ret = 0;
1491 
1492  lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1493  GFP_KERNEL);
1494 
1495  if (lm49453 == NULL)
1496  return -ENOMEM;
1497 
1498  i2c_set_clientdata(i2c, lm49453);
1499 
1500  lm49453->regmap = regmap_init_i2c(i2c, &lm49453_regmap_config);
1501  if (IS_ERR(lm49453->regmap)) {
1502  ret = PTR_ERR(lm49453->regmap);
1503  dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1504  ret);
1505  return ret;
1506  }
1507 
1508  ret = snd_soc_register_codec(&i2c->dev,
1509  &soc_codec_dev_lm49453,
1510  lm49453_dai, ARRAY_SIZE(lm49453_dai));
1511  if (ret < 0) {
1512  dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1513  regmap_exit(lm49453->regmap);
1514  return ret;
1515  }
1516 
1517  return ret;
1518 }
1519 
1520 static int __devexit lm49453_i2c_remove(struct i2c_client *client)
1521 {
1522  struct lm49453_priv *lm49453 = i2c_get_clientdata(client);
1523 
1524  snd_soc_unregister_codec(&client->dev);
1525  regmap_exit(lm49453->regmap);
1526  return 0;
1527 }
1528 
1529 static const struct i2c_device_id lm49453_i2c_id[] = {
1530  { "lm49453", 0 },
1531  { }
1532 };
1533 MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1534 
1535 static struct i2c_driver lm49453_i2c_driver = {
1536  .driver = {
1537  .name = "lm49453",
1538  .owner = THIS_MODULE,
1539  },
1540  .probe = lm49453_i2c_probe,
1541  .remove = __devexit_p(lm49453_i2c_remove),
1542  .id_table = lm49453_i2c_id,
1543 };
1544 
1545 module_i2c_driver(lm49453_i2c_driver);
1546 
1547 MODULE_DESCRIPTION("ASoC LM49453 driver");
1548 MODULE_AUTHOR("M R Swami Reddy <[email protected]>");
1549 MODULE_LICENSE("GPL v2");
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