Linux Kernel
3.7.1
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Macros | |
#define | FDMI_DID 0xfffffaU |
#define | NameServer_DID 0xfffffcU |
#define | SCR_DID 0xfffffdU |
#define | Fabric_DID 0xfffffeU |
#define | Bcast_DID 0xffffffU |
#define | Mask_DID 0xffffffU |
#define | CT_DID_MASK 0xffff00U |
#define | Fabric_DID_MASK 0xfff000U |
#define | WELL_KNOWN_DID_MASK 0xfffff0U |
#define | PT2PT_LocalID 1 |
#define | PT2PT_RemoteID 2 |
#define | FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ |
#define | FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ |
#define | FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ |
#define | FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ |
#define | LPFC_BUF_RING0 |
#define | FCELSSIZE 1024 /* maximum ELS transfer size */ |
#define | LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ |
#define | LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ |
#define | LPFC_ELS_RING 2 /* ring 2 for ELS commands */ |
#define | LPFC_FCP_NEXT_RING 3 |
#define | SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ |
#define | SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ |
#define | SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ |
#define | SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ |
#define | SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ |
#define | SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ |
#define | SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ |
#define | SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ |
#define | SLI2_IOCB_CMD_R3_ENTRIES 0 |
#define | SLI2_IOCB_RSP_R3_ENTRIES 0 |
#define | SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 |
#define | SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 |
#define | SLI2_IOCB_CMD_SIZE 32 |
#define | SLI2_IOCB_RSP_SIZE 32 |
#define | SLI3_IOCB_CMD_SIZE 128 |
#define | SLI3_IOCB_RSP_SIZE 64 |
#define | LPFC_UNREG_ALL_RPIS_VPORT 0xffff |
#define | LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff |
#define | LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) |
#define | FW_REV_STR_SIZE 32 |
#define | FC4_FEATURE_INIT 0x2 |
#define | FC4_FEATURE_TARGET 0x1 |
#define | FCP_TYPE_FEATURE_OFFSET 7 |
#define | SLI_CT_REVISION 1 |
#define | GID_REQUEST_SZ |
#define | GFF_REQUEST_SZ |
#define | RFT_REQUEST_SZ |
#define | RFF_REQUEST_SZ |
#define | RNN_REQUEST_SZ |
#define | RSNN_REQUEST_SZ |
#define | DA_ID_REQUEST_SZ |
#define | RSPN_REQUEST_SZ |
#define | SLI_CT_MANAGEMENT_SERVICE 0xFA |
#define | SLI_CT_TIME_SERVICE 0xFB |
#define | SLI_CT_DIRECTORY_SERVICE 0xFC |
#define | SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD |
#define | SLI_CT_DIRECTORY_NAME_SERVER 0x02 |
#define | SLI_CT_RESPONSE_FS_RJT 0x8001 |
#define | SLI_CT_RESPONSE_FS_ACC 0x8002 |
#define | SLI_CT_NO_ADDITIONAL_EXPL 0x0 |
#define | SLI_CT_INVALID_COMMAND 0x01 |
#define | SLI_CT_INVALID_VERSION 0x02 |
#define | SLI_CT_LOGICAL_ERROR 0x03 |
#define | SLI_CT_INVALID_IU_SIZE 0x04 |
#define | SLI_CT_LOGICAL_BUSY 0x05 |
#define | SLI_CT_PROTOCOL_ERROR 0x07 |
#define | SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 |
#define | SLI_CT_REQ_NOT_SUPPORTED 0x0b |
#define | SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 |
#define | SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 |
#define | SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 |
#define | SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 |
#define | SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 |
#define | SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 |
#define | SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 |
#define | SLI_CT_VENDOR_UNIQUE 0xff |
#define | SLI_CT_NO_PORT_ID 0x01 |
#define | SLI_CT_NO_PORT_NAME 0x02 |
#define | SLI_CT_NO_NODE_NAME 0x03 |
#define | SLI_CT_NO_CLASS_OF_SERVICE 0x04 |
#define | SLI_CT_NO_IP_ADDRESS 0x05 |
#define | SLI_CT_NO_IPA 0x06 |
#define | SLI_CT_NO_FC4_TYPES 0x07 |
#define | SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 |
#define | SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 |
#define | SLI_CT_NO_PORT_TYPE 0x0A |
#define | SLI_CT_ACCESS_DENIED 0x10 |
#define | SLI_CT_INVALID_PORT_ID 0x11 |
#define | SLI_CT_DATABASE_EMPTY 0x12 |
#define | SLI_CTNS_GA_NXT 0x0100 |
#define | SLI_CTNS_GPN_ID 0x0112 |
#define | SLI_CTNS_GNN_ID 0x0113 |
#define | SLI_CTNS_GCS_ID 0x0114 |
#define | SLI_CTNS_GFT_ID 0x0117 |
#define | SLI_CTNS_GSPN_ID 0x0118 |
#define | SLI_CTNS_GPT_ID 0x011A |
#define | SLI_CTNS_GFF_ID 0x011F |
#define | SLI_CTNS_GID_PN 0x0121 |
#define | SLI_CTNS_GID_NN 0x0131 |
#define | SLI_CTNS_GIP_NN 0x0135 |
#define | SLI_CTNS_GIPA_NN 0x0136 |
#define | SLI_CTNS_GSNN_NN 0x0139 |
#define | SLI_CTNS_GNN_IP 0x0153 |
#define | SLI_CTNS_GIPA_IP 0x0156 |
#define | SLI_CTNS_GID_FT 0x0171 |
#define | SLI_CTNS_GID_PT 0x01A1 |
#define | SLI_CTNS_RPN_ID 0x0212 |
#define | SLI_CTNS_RNN_ID 0x0213 |
#define | SLI_CTNS_RCS_ID 0x0214 |
#define | SLI_CTNS_RFT_ID 0x0217 |
#define | SLI_CTNS_RSPN_ID 0x0218 |
#define | SLI_CTNS_RPT_ID 0x021A |
#define | SLI_CTNS_RFF_ID 0x021F |
#define | SLI_CTNS_RIP_NN 0x0235 |
#define | SLI_CTNS_RIPA_NN 0x0236 |
#define | SLI_CTNS_RSNN_NN 0x0239 |
#define | SLI_CTNS_DA_ID 0x0300 |
#define | SLI_CTPT_N_PORT 0x01 |
#define | SLI_CTPT_NL_PORT 0x02 |
#define | SLI_CTPT_FNL_PORT 0x03 |
#define | SLI_CTPT_IP 0x04 |
#define | SLI_CTPT_FCP 0x08 |
#define | SLI_CTPT_NX_PORT 0x7F |
#define | SLI_CTPT_F_PORT 0x81 |
#define | SLI_CTPT_FL_PORT 0x82 |
#define | SLI_CTPT_E_PORT 0x84 |
#define | SLI_CT_LAST_ENTRY 0x80000000 |
#define | FC_PH_4_0 6 /* FC-PH version 4.0 */ |
#define | FC_PH_4_1 7 /* FC-PH version 4.1 */ |
#define | FC_PH_4_2 8 /* FC-PH version 4.2 */ |
#define | FC_PH_4_3 9 /* FC-PH version 4.3 */ |
#define | FC_PH_LOW 8 /* Lowest supported FC-PH version */ |
#define | FC_PH_HIGH 9 /* Highest supported FC-PH version */ |
#define | FC_PH3 0x20 /* FC-PH-3 version */ |
#define | FF_FRAME_SIZE 2048 |
#define | NAME_IEEE 0x1 /* IEEE name - nameType */ |
#define | NAME_IEEE_EXT 0x2 /* IEEE extended name */ |
#define | NAME_FC_TYPE 0x3 /* FC native name type */ |
#define | NAME_IP_TYPE 0x4 /* IP address */ |
#define | NAME_CCITT_TYPE 0xC |
#define | NAME_CCITT_GR_TYPE 0xE |
#define | clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ |
#define | virtual_fabric_support randomOffset /* Word 1, bit 30 */ |
#define | fc_vft_hdr_r_ctl_SHIFT 24 |
#define | fc_vft_hdr_r_ctl_MASK 0xFF |
#define | fc_vft_hdr_r_ctl_WORD word0 |
#define | fc_vft_hdr_ver_SHIFT 22 |
#define | fc_vft_hdr_ver_MASK 0x3 |
#define | fc_vft_hdr_ver_WORD word0 |
#define | fc_vft_hdr_type_SHIFT 18 |
#define | fc_vft_hdr_type_MASK 0xF |
#define | fc_vft_hdr_type_WORD word0 |
#define | fc_vft_hdr_e_SHIFT 16 |
#define | fc_vft_hdr_e_MASK 0x1 |
#define | fc_vft_hdr_e_WORD word0 |
#define | fc_vft_hdr_priority_SHIFT 13 |
#define | fc_vft_hdr_priority_MASK 0x7 |
#define | fc_vft_hdr_priority_WORD word0 |
#define | fc_vft_hdr_vf_id_SHIFT 1 |
#define | fc_vft_hdr_vf_id_MASK 0xFFF |
#define | fc_vft_hdr_vf_id_WORD word0 |
#define | fc_vft_hdr_hopct_SHIFT 24 |
#define | fc_vft_hdr_hopct_MASK 0xFF |
#define | fc_vft_hdr_hopct_WORD word1 |
#define | ELS_CMD_MASK 0xffff |
#define | ELS_RSP_MASK 0xff |
#define | ELS_CMD_LS_RJT 0x01 |
#define | ELS_CMD_ACC 0x02 |
#define | ELS_CMD_PLOGI 0x03 |
#define | ELS_CMD_FLOGI 0x04 |
#define | ELS_CMD_LOGO 0x05 |
#define | ELS_CMD_ABTX 0x06 |
#define | ELS_CMD_RCS 0x07 |
#define | ELS_CMD_RES 0x08 |
#define | ELS_CMD_RSS 0x09 |
#define | ELS_CMD_RSI 0x0A |
#define | ELS_CMD_ESTS 0x0B |
#define | ELS_CMD_ESTC 0x0C |
#define | ELS_CMD_ADVC 0x0D |
#define | ELS_CMD_RTV 0x0E |
#define | ELS_CMD_RLS 0x0F |
#define | ELS_CMD_ECHO 0x10 |
#define | ELS_CMD_TEST 0x11 |
#define | ELS_CMD_RRQ 0x12 |
#define | ELS_CMD_PRLI 0x14001020 |
#define | ELS_CMD_PRLO 0x14001021 |
#define | ELS_CMD_PRLO_ACC 0x14001002 |
#define | ELS_CMD_PDISC 0x50 |
#define | ELS_CMD_FDISC 0x51 |
#define | ELS_CMD_ADISC 0x52 |
#define | ELS_CMD_FARP 0x54 |
#define | ELS_CMD_FARPR 0x55 |
#define | ELS_CMD_RPS 0x56 |
#define | ELS_CMD_RPL 0x57 |
#define | ELS_CMD_FAN 0x60 |
#define | ELS_CMD_RSCN 0x0461 |
#define | ELS_CMD_SCR 0x62 |
#define | ELS_CMD_RNID 0x78 |
#define | ELS_CMD_LIRR 0x7A |
#define | LSRJT_INVALID_CMD 0x01 |
#define | LSRJT_LOGICAL_ERR 0x03 |
#define | LSRJT_LOGICAL_BSY 0x05 |
#define | LSRJT_PROTOCOL_ERR 0x07 |
#define | LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ |
#define | LSRJT_CMD_UNSUPPORTED 0x0B |
#define | LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ |
#define | LSEXP_NOTHING_MORE 0x00 |
#define | LSEXP_SPARM_OPTIONS 0x01 |
#define | LSEXP_SPARM_ICTL 0x03 |
#define | LSEXP_SPARM_RCTL 0x05 |
#define | LSEXP_SPARM_RCV_SIZE 0x07 |
#define | LSEXP_SPARM_CONCUR_SEQ 0x09 |
#define | LSEXP_SPARM_CREDIT 0x0B |
#define | LSEXP_INVALID_PNAME 0x0D |
#define | LSEXP_INVALID_NNAME 0x0E |
#define | LSEXP_INVALID_CSP 0x0F |
#define | LSEXP_INVALID_ASSOC_HDR 0x11 |
#define | LSEXP_ASSOC_HDR_REQ 0x13 |
#define | LSEXP_INVALID_O_SID 0x15 |
#define | LSEXP_INVALID_OX_RX 0x17 |
#define | LSEXP_CMD_IN_PROGRESS 0x19 |
#define | LSEXP_PORT_LOGIN_REQ 0x1E |
#define | LSEXP_INVALID_NPORT_ID 0x1F |
#define | LSEXP_INVALID_SEQ_ID 0x21 |
#define | LSEXP_INVALID_XCHG 0x23 |
#define | LSEXP_INACTIVE_XCHG 0x25 |
#define | LSEXP_RQ_REQUIRED 0x27 |
#define | LSEXP_OUT_OF_RESOURCE 0x29 |
#define | LSEXP_CANT_GIVE_DATA 0x2A |
#define | LSEXP_REQ_UNSUPPORTED 0x2C |
#define | PRLX_PAGE_LEN 0x10 |
#define | TPRLO_PAGE_LEN 0x14 |
#define | PRLI_FCP_TYPE 0x08 |
#define | PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ |
#define | PRLI_NO_RESOURCES 0x2 |
#define | PRLI_INIT_INCOMPLETE 0x3 |
#define | PRLI_NO_SUCH_PA 0x4 |
#define | PRLI_PREDEF_CONFIG 0x5 |
#define | PRLI_PARTIAL_SUCCESS 0x6 |
#define | PRLI_INVALID_PAGE_CNT 0x7 |
#define | PRLO_FCP_TYPE 0x08 |
#define | PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ |
#define | PRLO_NO_SUCH_IMAGE 0x4 |
#define | PRLO_INVALID_PAGE_CNT 0x7 |
#define | FARP_NO_ACTION |
#define | FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ |
#define | FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ |
#define | FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ |
#define | FARP_MATCH_IPV4 |
#define | FARP_MATCH_IPV6 |
#define | FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ |
#define | FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ |
#define | SCR_FUNC_FABRIC 0x01 |
#define | SCR_FUNC_NPORT 0x02 |
#define | SCR_FUNC_FULL 0x03 |
#define | SCR_CLEAR 0xff |
#define | RNID_HBA 0x7 |
#define | RNID_HOST 0xa |
#define | RNID_DRIVER 0xd |
#define | RNID_IPV4 0x1 |
#define | RNID_IPV6 0x2 |
#define | RNID_TD_SUPPORT 0x1 |
#define | RNID_LP_VALID 0x2 |
#define | RNID_TOPOLOGY_DISC 0xdf |
#define | rls_rsvd_SHIFT 24 |
#define | rls_rsvd_MASK 0x000000ff |
#define | rls_rsvd_WORD rls |
#define | rls_did_SHIFT 0 |
#define | rls_did_MASK 0x00ffffff |
#define | rls_did_WORD rls |
#define | rrq_rsvd_SHIFT 24 |
#define | rrq_rsvd_MASK 0x000000ff |
#define | rrq_rsvd_WORD rrq |
#define | rrq_did_SHIFT 0 |
#define | rrq_did_MASK 0x00ffffff |
#define | rrq_did_WORD rrq |
#define | rrq_oxid_SHIFT 16 |
#define | rrq_oxid_MASK 0xffff |
#define | rrq_oxid_WORD rrq_exchg |
#define | rrq_rxid_SHIFT 0 |
#define | rrq_rxid_MASK 0xffff |
#define | rrq_rxid_WORD rrq_exchg |
#define | LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ |
#define | LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ |
#define | qtov_rsvd0_SHIFT 28 |
#define | qtov_rsvd0_MASK 0x0000000f |
#define | qtov_rsvd0_WORD qtov /* reserved */ |
#define | qtov_edtovres_SHIFT 27 |
#define | qtov_edtovres_MASK 0x00000001 |
#define | qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ |
#define | qtov__rsvd1_SHIFT 19 |
#define | qtov_rsvd1_MASK 0x0000003f |
#define | qtov_rsvd1_WORD qtov /* reserved */ |
#define | qtov_rttov_SHIFT 18 |
#define | qtov_rttov_MASK 0x00000001 |
#define | qtov_rttov_WORD qtov /* R_T_TOV value */ |
#define | qtov_rsvd2_SHIFT 0 |
#define | qtov_rsvd2_MASK 0x0003ffff |
#define | qtov_rsvd2_WORD qtov /* reserved */ |
#define | RSCN_ADDRESS_FORMAT_PORT 0x0 |
#define | RSCN_ADDRESS_FORMAT_AREA 0x1 |
#define | RSCN_ADDRESS_FORMAT_DOMAIN 0x2 |
#define | RSCN_ADDRESS_FORMAT_FABRIC 0x3 |
#define | RSCN_ADDRESS_FORMAT_MASK 0x3 |
#define | SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ |
#define | SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ |
#define | SLI_MGMT_GRPL 0x102 /* Get registered Port list */ |
#define | SLI_MGMT_GPAT 0x110 /* Get Port attributes */ |
#define | SLI_MGMT_RHBA 0x200 /* Register HBA */ |
#define | SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ |
#define | SLI_MGMT_RPRT 0x210 /* Register Port */ |
#define | SLI_MGMT_RPA 0x211 /* Register Port attributes */ |
#define | SLI_MGMT_DHBA 0x300 /* De-register HBA */ |
#define | SLI_MGMT_DPRT 0x310 /* De-register Port */ |
#define | SLI_CT_FDMI_Subtypes 0x10 |
#define | REJECT_CODE 0x9 /* Unable to perform command request */ |
#define | NODE_NAME 0x1 |
#define | MANUFACTURER 0x2 |
#define | SERIAL_NUMBER 0x3 |
#define | MODEL 0x4 |
#define | MODEL_DESCRIPTION 0x5 |
#define | HARDWARE_VERSION 0x6 |
#define | DRIVER_VERSION 0x7 |
#define | OPTION_ROM_VERSION 0x8 |
#define | FIRMWARE_VERSION 0x9 |
#define | OS_NAME_VERSION 0xa |
#define | MAX_CT_PAYLOAD_LEN 0xb |
#define | SUPPORTED_FC4_TYPES 0x1 |
#define | SUPPORTED_SPEED 0x2 |
#define | PORT_SPEED 0x3 |
#define | MAX_FRAME_SIZE 0x4 |
#define | OS_DEVICE_NAME 0x5 |
#define | HOST_NAME 0x6 |
#define | MAX_SLI3_CONFIGURED_RINGS 3 |
#define | MAX_SLI3_RINGS 4 |
#define | OWN_CHIP 1 |
#define | OWN_HOST 0 |
#define | IOCB_WORD_SZ 8 |
#define | FC_NET_HDR 0x20 |
#define | PCI_VENDOR_ID_EMULEX 0x10df |
#define | PCI_DEVICE_ID_FIREFLY 0x1ae5 |
#define | PCI_DEVICE_ID_PROTEUS_VF 0xe100 |
#define | PCI_DEVICE_ID_BALIUS 0xe131 |
#define | PCI_DEVICE_ID_PROTEUS_PF 0xe180 |
#define | PCI_DEVICE_ID_LANCER_FC 0xe200 |
#define | PCI_DEVICE_ID_LANCER_FC_VF 0xe208 |
#define | PCI_DEVICE_ID_LANCER_FCOE 0xe260 |
#define | PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 |
#define | PCI_DEVICE_ID_SAT_SMB 0xf011 |
#define | PCI_DEVICE_ID_SAT_MID 0xf015 |
#define | PCI_DEVICE_ID_RFLY 0xf095 |
#define | PCI_DEVICE_ID_PFLY 0xf098 |
#define | PCI_DEVICE_ID_LP101 0xf0a1 |
#define | PCI_DEVICE_ID_TFLY 0xf0a5 |
#define | PCI_DEVICE_ID_BSMB 0xf0d1 |
#define | PCI_DEVICE_ID_BMID 0xf0d5 |
#define | PCI_DEVICE_ID_ZSMB 0xf0e1 |
#define | PCI_DEVICE_ID_ZMID 0xf0e5 |
#define | PCI_DEVICE_ID_NEPTUNE 0xf0f5 |
#define | PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 |
#define | PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 |
#define | PCI_DEVICE_ID_SAT 0xf100 |
#define | PCI_DEVICE_ID_SAT_SCSP 0xf111 |
#define | PCI_DEVICE_ID_SAT_DCSP 0xf112 |
#define | PCI_DEVICE_ID_FALCON 0xf180 |
#define | PCI_DEVICE_ID_SUPERFLY 0xf700 |
#define | PCI_DEVICE_ID_DRAGONFLY 0xf800 |
#define | PCI_DEVICE_ID_CENTAUR 0xf900 |
#define | PCI_DEVICE_ID_PEGASUS 0xf980 |
#define | PCI_DEVICE_ID_THOR 0xfa00 |
#define | PCI_DEVICE_ID_VIPER 0xfb00 |
#define | PCI_DEVICE_ID_LP10000S 0xfc00 |
#define | PCI_DEVICE_ID_LP11000S 0xfc10 |
#define | PCI_DEVICE_ID_LPE11000S 0xfc20 |
#define | PCI_DEVICE_ID_SAT_S 0xfc40 |
#define | PCI_DEVICE_ID_PROTEUS_S 0xfc50 |
#define | PCI_DEVICE_ID_HELIOS 0xfd00 |
#define | PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 |
#define | PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 |
#define | PCI_DEVICE_ID_ZEPHYR 0xfe00 |
#define | PCI_DEVICE_ID_HORNET 0xfe05 |
#define | PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 |
#define | PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 |
#define | PCI_VENDOR_ID_SERVERENGINE 0x19a2 |
#define | PCI_DEVICE_ID_TIGERSHARK 0x0704 |
#define | PCI_DEVICE_ID_TOMCAT 0x0714 |
#define | PCI_DEVICE_ID_SKYHAWK 0x0724 |
#define | PCI_DEVICE_ID_SKYHAWK_VF 0x072c |
#define | JEDEC_ID_ADDRESS 0x0080001c |
#define | FIREFLY_JEDEC_ID 0x1ACC |
#define | SUPERFLY_JEDEC_ID 0x0020 |
#define | DRAGONFLY_JEDEC_ID 0x0021 |
#define | DRAGONFLY_V2_JEDEC_ID 0x0025 |
#define | CENTAUR_2G_JEDEC_ID 0x0026 |
#define | CENTAUR_1G_JEDEC_ID 0x0028 |
#define | PEGASUS_ORION_JEDEC_ID 0x0036 |
#define | PEGASUS_JEDEC_ID 0x0038 |
#define | THOR_JEDEC_ID 0x0012 |
#define | HELIOS_JEDEC_ID 0x0364 |
#define | ZEPHYR_JEDEC_ID 0x0577 |
#define | VIPER_JEDEC_ID 0x4838 |
#define | SATURN_JEDEC_ID 0x1004 |
#define | HORNET_JDEC_ID 0x2057706D |
#define | JEDEC_ID_MASK 0x0FFFF000 |
#define | JEDEC_ID_SHIFT 12 |
#define | FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) |
#define | FF_REG_AREA_SIZE 256 |
#define | HA_REG_OFFSET 0 /* Byte offset from register base address */ |
#define | HA_R0RE_REQ 0x00000001 /* Bit 0 */ |
#define | HA_R0CE_RSP 0x00000002 /* Bit 1 */ |
#define | HA_R0ATT 0x00000008 /* Bit 3 */ |
#define | HA_R1RE_REQ 0x00000010 /* Bit 4 */ |
#define | HA_R1CE_RSP 0x00000020 /* Bit 5 */ |
#define | HA_R1ATT 0x00000080 /* Bit 7 */ |
#define | HA_R2RE_REQ 0x00000100 /* Bit 8 */ |
#define | HA_R2CE_RSP 0x00000200 /* Bit 9 */ |
#define | HA_R2ATT 0x00000800 /* Bit 11 */ |
#define | HA_R3RE_REQ 0x00001000 /* Bit 12 */ |
#define | HA_R3CE_RSP 0x00002000 /* Bit 13 */ |
#define | HA_R3ATT 0x00008000 /* Bit 15 */ |
#define | HA_LATT 0x20000000 /* Bit 29 */ |
#define | HA_MBATT 0x40000000 /* Bit 30 */ |
#define | HA_ERATT 0x80000000 /* Bit 31 */ |
#define | HA_RXRE_REQ 0x00000001 /* Bit 0 */ |
#define | HA_RXCE_RSP 0x00000002 /* Bit 1 */ |
#define | HA_RXATT 0x00000008 /* Bit 3 */ |
#define | HA_RXMASK 0x0000000f |
#define | HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) |
#define | HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) |
#define | HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) |
#define | HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) |
#define | HA_R0_POS 3 |
#define | HA_R1_POS 7 |
#define | HA_R2_POS 11 |
#define | HA_R3_POS 15 |
#define | HA_LE_POS 29 |
#define | HA_MB_POS 30 |
#define | HA_ER_POS 31 |
#define | CA_REG_OFFSET 4 /* Byte offset from register base address */ |
#define | CA_R0CE_REQ 0x00000001 /* Bit 0 */ |
#define | CA_R0RE_RSP 0x00000002 /* Bit 1 */ |
#define | CA_R0ATT 0x00000008 /* Bit 3 */ |
#define | CA_R1CE_REQ 0x00000010 /* Bit 4 */ |
#define | CA_R1RE_RSP 0x00000020 /* Bit 5 */ |
#define | CA_R1ATT 0x00000080 /* Bit 7 */ |
#define | CA_R2CE_REQ 0x00000100 /* Bit 8 */ |
#define | CA_R2RE_RSP 0x00000200 /* Bit 9 */ |
#define | CA_R2ATT 0x00000800 /* Bit 11 */ |
#define | CA_R3CE_REQ 0x00001000 /* Bit 12 */ |
#define | CA_R3RE_RSP 0x00002000 /* Bit 13 */ |
#define | CA_R3ATT 0x00008000 /* Bit 15 */ |
#define | CA_MBATT 0x40000000 /* Bit 30 */ |
#define | HS_REG_OFFSET 8 /* Byte offset from register base address */ |
#define | HS_MBRDY 0x00400000 /* Bit 22 */ |
#define | HS_FFRDY 0x00800000 /* Bit 23 */ |
#define | HS_FFER8 0x01000000 /* Bit 24 */ |
#define | HS_FFER7 0x02000000 /* Bit 25 */ |
#define | HS_FFER6 0x04000000 /* Bit 26 */ |
#define | HS_FFER5 0x08000000 /* Bit 27 */ |
#define | HS_FFER4 0x10000000 /* Bit 28 */ |
#define | HS_FFER3 0x20000000 /* Bit 29 */ |
#define | HS_FFER2 0x40000000 /* Bit 30 */ |
#define | HS_FFER1 0x80000000 /* Bit 31 */ |
#define | HS_CRIT_TEMP 0x00000100 /* Bit 8 */ |
#define | HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ |
#define | UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ |
#define | HC_REG_OFFSET 12 /* Byte offset from register base address */ |
#define | HC_MBINT_ENA 0x00000001 /* Bit 0 */ |
#define | HC_R0INT_ENA 0x00000002 /* Bit 1 */ |
#define | HC_R1INT_ENA 0x00000004 /* Bit 2 */ |
#define | HC_R2INT_ENA 0x00000008 /* Bit 3 */ |
#define | HC_R3INT_ENA 0x00000010 /* Bit 4 */ |
#define | HC_INITHBI 0x02000000 /* Bit 25 */ |
#define | HC_INITMB 0x04000000 /* Bit 26 */ |
#define | HC_INITFF 0x08000000 /* Bit 27 */ |
#define | HC_LAINT_ENA 0x20000000 /* Bit 29 */ |
#define | HC_ERINT_ENA 0x80000000 /* Bit 31 */ |
#define | MSIX_DFLT_ID 0 |
#define | MSIX_RNG0_ID 0 |
#define | MSIX_RNG1_ID 1 |
#define | MSIX_RNG2_ID 2 |
#define | MSIX_RNG3_ID 3 |
#define | MSIX_LINK_ID 4 |
#define | MSIX_MBOX_ID 5 |
#define | MSIX_SPARE0_ID 6 |
#define | MSIX_SPARE1_ID 7 |
#define | MBX_SHUTDOWN 0x00 /* terminate testing */ |
#define | MBX_LOAD_SM 0x01 |
#define | MBX_READ_NV 0x02 |
#define | MBX_WRITE_NV 0x03 |
#define | MBX_RUN_BIU_DIAG 0x04 |
#define | MBX_INIT_LINK 0x05 |
#define | MBX_DOWN_LINK 0x06 |
#define | MBX_CONFIG_LINK 0x07 |
#define | MBX_CONFIG_RING 0x09 |
#define | MBX_RESET_RING 0x0A |
#define | MBX_READ_CONFIG 0x0B |
#define | MBX_READ_RCONFIG 0x0C |
#define | MBX_READ_SPARM 0x0D |
#define | MBX_READ_STATUS 0x0E |
#define | MBX_READ_RPI 0x0F |
#define | MBX_READ_XRI 0x10 |
#define | MBX_READ_REV 0x11 |
#define | MBX_READ_LNK_STAT 0x12 |
#define | MBX_REG_LOGIN 0x13 |
#define | MBX_UNREG_LOGIN 0x14 |
#define | MBX_CLEAR_LA 0x16 |
#define | MBX_DUMP_MEMORY 0x17 |
#define | MBX_DUMP_CONTEXT 0x18 |
#define | MBX_RUN_DIAGS 0x19 |
#define | MBX_RESTART 0x1A |
#define | MBX_UPDATE_CFG 0x1B |
#define | MBX_DOWN_LOAD 0x1C |
#define | MBX_DEL_LD_ENTRY 0x1D |
#define | MBX_RUN_PROGRAM 0x1E |
#define | MBX_SET_MASK 0x20 |
#define | MBX_SET_VARIABLE 0x21 |
#define | MBX_UNREG_D_ID 0x23 |
#define | MBX_KILL_BOARD 0x24 |
#define | MBX_CONFIG_FARP 0x25 |
#define | MBX_BEACON 0x2A |
#define | MBX_CONFIG_MSI 0x30 |
#define | MBX_HEARTBEAT 0x31 |
#define | MBX_WRITE_VPARMS 0x32 |
#define | MBX_ASYNCEVT_ENABLE 0x33 |
#define | MBX_READ_EVENT_LOG_STATUS 0x37 |
#define | MBX_READ_EVENT_LOG 0x38 |
#define | MBX_WRITE_EVENT_LOG 0x39 |
#define | MBX_PORT_CAPABILITIES 0x3B |
#define | MBX_PORT_IOV_CONTROL 0x3C |
#define | MBX_CONFIG_HBQ 0x7C |
#define | MBX_LOAD_AREA 0x81 |
#define | MBX_RUN_BIU_DIAG64 0x84 |
#define | MBX_CONFIG_PORT 0x88 |
#define | MBX_READ_SPARM64 0x8D |
#define | MBX_READ_RPI64 0x8F |
#define | MBX_REG_LOGIN64 0x93 |
#define | MBX_READ_TOPOLOGY 0x95 |
#define | MBX_REG_VPI 0x96 |
#define | MBX_UNREG_VPI 0x97 |
#define | MBX_WRITE_WWN 0x98 |
#define | MBX_SET_DEBUG 0x99 |
#define | MBX_LOAD_EXP_ROM 0x9C |
#define | MBX_SLI4_CONFIG 0x9B |
#define | MBX_SLI4_REQ_FTRS 0x9D |
#define | MBX_MAX_CMDS 0x9E |
#define | MBX_RESUME_RPI 0x9E |
#define | MBX_SLI2_CMD_MASK 0x80 |
#define | MBX_REG_VFI 0x9F |
#define | MBX_REG_FCFI 0xA0 |
#define | MBX_UNREG_VFI 0xA1 |
#define | MBX_UNREG_FCFI 0xA2 |
#define | MBX_INIT_VFI 0xA3 |
#define | MBX_INIT_VPI 0xA4 |
#define | MBX_ACCESS_VDATA 0xA5 |
#define | MBX_AUTH_PORT 0xF8 |
#define | MBX_SECURITY_MGMT 0xF9 |
#define | CMD_RCV_SEQUENCE_CX 0x01 |
#define | CMD_XMIT_SEQUENCE_CR 0x02 |
#define | CMD_XMIT_SEQUENCE_CX 0x03 |
#define | CMD_XMIT_BCAST_CN 0x04 |
#define | CMD_XMIT_BCAST_CX 0x05 |
#define | CMD_QUE_RING_BUF_CN 0x06 |
#define | CMD_QUE_XRI_BUF_CX 0x07 |
#define | CMD_IOCB_CONTINUE_CN 0x08 |
#define | CMD_RET_XRI_BUF_CX 0x09 |
#define | CMD_ELS_REQUEST_CR 0x0A |
#define | CMD_ELS_REQUEST_CX 0x0B |
#define | CMD_RCV_ELS_REQ_CX 0x0D |
#define | CMD_ABORT_XRI_CN 0x0E |
#define | CMD_ABORT_XRI_CX 0x0F |
#define | CMD_CLOSE_XRI_CN 0x10 |
#define | CMD_CLOSE_XRI_CX 0x11 |
#define | CMD_CREATE_XRI_CR 0x12 |
#define | CMD_CREATE_XRI_CX 0x13 |
#define | CMD_GET_RPI_CN 0x14 |
#define | CMD_XMIT_ELS_RSP_CX 0x15 |
#define | CMD_GET_RPI_CR 0x16 |
#define | CMD_XRI_ABORTED_CX 0x17 |
#define | CMD_FCP_IWRITE_CR 0x18 |
#define | CMD_FCP_IWRITE_CX 0x19 |
#define | CMD_FCP_IREAD_CR 0x1A |
#define | CMD_FCP_IREAD_CX 0x1B |
#define | CMD_FCP_ICMND_CR 0x1C |
#define | CMD_FCP_ICMND_CX 0x1D |
#define | CMD_FCP_TSEND_CX 0x1F |
#define | CMD_FCP_TRECEIVE_CX 0x21 |
#define | CMD_FCP_TRSP_CX 0x23 |
#define | CMD_FCP_AUTO_TRSP_CX 0x29 |
#define | CMD_ADAPTER_MSG 0x20 |
#define | CMD_ADAPTER_DUMP 0x22 |
#define | CMD_ASYNC_STATUS 0x7C |
#define | CMD_RCV_SEQUENCE64_CX 0x81 |
#define | CMD_XMIT_SEQUENCE64_CR 0x82 |
#define | CMD_XMIT_SEQUENCE64_CX 0x83 |
#define | CMD_XMIT_BCAST64_CN 0x84 |
#define | CMD_XMIT_BCAST64_CX 0x85 |
#define | CMD_QUE_RING_BUF64_CN 0x86 |
#define | CMD_QUE_XRI_BUF64_CX 0x87 |
#define | CMD_IOCB_CONTINUE64_CN 0x88 |
#define | CMD_RET_XRI_BUF64_CX 0x89 |
#define | CMD_ELS_REQUEST64_CR 0x8A |
#define | CMD_ELS_REQUEST64_CX 0x8B |
#define | CMD_ABORT_MXRI64_CN 0x8C |
#define | CMD_RCV_ELS_REQ64_CX 0x8D |
#define | CMD_XMIT_ELS_RSP64_CX 0x95 |
#define | CMD_XMIT_BLS_RSP64_CX 0x97 |
#define | CMD_FCP_IWRITE64_CR 0x98 |
#define | CMD_FCP_IWRITE64_CX 0x99 |
#define | CMD_FCP_IREAD64_CR 0x9A |
#define | CMD_FCP_IREAD64_CX 0x9B |
#define | CMD_FCP_ICMND64_CR 0x9C |
#define | CMD_FCP_ICMND64_CX 0x9D |
#define | CMD_FCP_TSEND64_CX 0x9F |
#define | CMD_FCP_TRECEIVE64_CX 0xA1 |
#define | CMD_FCP_TRSP64_CX 0xA3 |
#define | CMD_QUE_XRI64_CX 0xB3 |
#define | CMD_IOCB_RCV_SEQ64_CX 0xB5 |
#define | CMD_IOCB_RCV_ELS64_CX 0xB7 |
#define | CMD_IOCB_RET_XRI64_CX 0xB9 |
#define | CMD_IOCB_RCV_CONT64_CX 0xBB |
#define | CMD_GEN_REQUEST64_CR 0xC2 |
#define | CMD_GEN_REQUEST64_CX 0xC3 |
#define | CMD_IOCB_XMIT_MSEQ64_CR 0xB0 |
#define | CMD_IOCB_XMIT_MSEQ64_CX 0xB1 |
#define | CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 |
#define | CMD_IOCB_RCV_ELS_LIST64_CX 0xCD |
#define | CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 |
#define | CMD_IOCB_ABORT_EXTENDED_CN 0xBA |
#define | CMD_IOCB_RET_HBQE64_CN 0xCA |
#define | CMD_IOCB_FCP_IBIDIR64_CR 0xAC |
#define | CMD_IOCB_FCP_IBIDIR64_CX 0xAD |
#define | CMD_IOCB_FCP_ITASKMGT64_CX 0xAF |
#define | CMD_IOCB_LOGENTRY_CN 0x94 |
#define | CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 |
#define | DSSCMD_IWRITE64_CR 0xF8 |
#define | DSSCMD_IWRITE64_CX 0xF9 |
#define | DSSCMD_IREAD64_CR 0xFA |
#define | DSSCMD_IREAD64_CX 0xFB |
#define | CMD_MAX_IOCB_CMD 0xFB |
#define | CMD_IOCB_MASK 0xff |
#define | MAX_MSG_DATA |
#define | LPFC_MAX_ADPTMSG 32 /* max msg data */ |
#define | MBX_SUCCESS 0 |
#define | MBXERR_NUM_RINGS 1 |
#define | MBXERR_NUM_IOCBS 2 |
#define | MBXERR_IOCBS_EXCEEDED 3 |
#define | MBXERR_BAD_RING_NUMBER 4 |
#define | MBXERR_MASK_ENTRIES_RANGE 5 |
#define | MBXERR_MASKS_EXCEEDED 6 |
#define | MBXERR_BAD_PROFILE 7 |
#define | MBXERR_BAD_DEF_CLASS 8 |
#define | MBXERR_BAD_MAX_RESPONDER 9 |
#define | MBXERR_BAD_MAX_ORIGINATOR 10 |
#define | MBXERR_RPI_REGISTERED 11 |
#define | MBXERR_RPI_FULL 12 |
#define | MBXERR_NO_RESOURCES 13 |
#define | MBXERR_BAD_RCV_LENGTH 14 |
#define | MBXERR_DMA_ERROR 15 |
#define | MBXERR_ERROR 16 |
#define | MBXERR_LINK_DOWN 0x33 |
#define | MBXERR_SEC_NO_PERMISSION 0xF02 |
#define | MBX_NOT_FINISHED 255 |
#define | MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ |
#define | MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ |
#define | TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ |
#define | LPFC_PDE5_DESCRIPTOR 0x85 |
#define | LPFC_PDE6_DESCRIPTOR 0x86 |
#define | LPFC_PDE7_DESCRIPTOR 0x87 |
#define | BG_OP_IN_NODIF_OUT_CRC 0x0 |
#define | BG_OP_IN_CRC_OUT_NODIF 0x1 |
#define | BG_OP_IN_NODIF_OUT_CSUM 0x2 |
#define | BG_OP_IN_CSUM_OUT_NODIF 0x3 |
#define | BG_OP_IN_CRC_OUT_CRC 0x4 |
#define | BG_OP_IN_CSUM_OUT_CSUM 0x5 |
#define | BG_OP_IN_CRC_OUT_CSUM 0x6 |
#define | BG_OP_IN_CSUM_OUT_CRC 0x7 |
#define | pde5_type_SHIFT 24 |
#define | pde5_type_MASK 0x000000ff |
#define | pde5_type_WORD word0 |
#define | pde5_rsvd0_SHIFT 0 |
#define | pde5_rsvd0_MASK 0x00ffffff |
#define | pde5_rsvd0_WORD word0 |
#define | pde6_type_SHIFT 24 |
#define | pde6_type_MASK 0x000000ff |
#define | pde6_type_WORD word0 |
#define | pde6_rsvd0_SHIFT 0 |
#define | pde6_rsvd0_MASK 0x00ffffff |
#define | pde6_rsvd0_WORD word0 |
#define | pde6_rsvd1_SHIFT 26 |
#define | pde6_rsvd1_MASK 0x0000003f |
#define | pde6_rsvd1_WORD word1 |
#define | pde6_na_SHIFT 25 |
#define | pde6_na_MASK 0x00000001 |
#define | pde6_na_WORD word1 |
#define | pde6_rsvd2_SHIFT 16 |
#define | pde6_rsvd2_MASK 0x000001FF |
#define | pde6_rsvd2_WORD word1 |
#define | pde6_apptagtr_SHIFT 0 |
#define | pde6_apptagtr_MASK 0x0000ffff |
#define | pde6_apptagtr_WORD word1 |
#define | pde6_optx_SHIFT 28 |
#define | pde6_optx_MASK 0x0000000f |
#define | pde6_optx_WORD word2 |
#define | pde6_oprx_SHIFT 24 |
#define | pde6_oprx_MASK 0x0000000f |
#define | pde6_oprx_WORD word2 |
#define | pde6_nr_SHIFT 23 |
#define | pde6_nr_MASK 0x00000001 |
#define | pde6_nr_WORD word2 |
#define | pde6_ce_SHIFT 22 |
#define | pde6_ce_MASK 0x00000001 |
#define | pde6_ce_WORD word2 |
#define | pde6_re_SHIFT 21 |
#define | pde6_re_MASK 0x00000001 |
#define | pde6_re_WORD word2 |
#define | pde6_ae_SHIFT 20 |
#define | pde6_ae_MASK 0x00000001 |
#define | pde6_ae_WORD word2 |
#define | pde6_ai_SHIFT 19 |
#define | pde6_ai_MASK 0x00000001 |
#define | pde6_ai_WORD word2 |
#define | pde6_bs_SHIFT 16 |
#define | pde6_bs_MASK 0x00000007 |
#define | pde6_bs_WORD word2 |
#define | pde6_apptagval_SHIFT 0 |
#define | pde6_apptagval_MASK 0x0000ffff |
#define | pde6_apptagval_WORD word2 |
#define | pde7_type_SHIFT 24 |
#define | pde7_type_MASK 0x000000ff |
#define | pde7_type_WORD word0 |
#define | pde7_rsvd0_SHIFT 0 |
#define | pde7_rsvd0_MASK 0x00ffffff |
#define | pde7_rsvd0_WORD word0 |
#define | lpfc_event_log_SHIFT 29 |
#define | lpfc_event_log_MASK 0x00000001 |
#define | lpfc_event_log_WORD word1 |
#define | USE_MAILBOX_RESPONSE 1 |
#define | FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ |
#define | FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ |
#define | FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ |
#define | FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ |
#define | FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ |
#define | FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ |
#define | FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ |
#define | FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ |
#define | FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ |
#define | FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ |
#define | LINK_SPEED_AUTO 0x0 /* Auto selection */ |
#define | LINK_SPEED_1G 0x1 /* 1 Gigabaud */ |
#define | LINK_SPEED_2G 0x2 /* 2 Gigabaud */ |
#define | LINK_SPEED_4G 0x4 /* 4 Gigabaud */ |
#define | LINK_SPEED_8G 0x8 /* 8 Gigabaud */ |
#define | LINK_SPEED_10G 0x10 /* 10 Gigabaud */ |
#define | LINK_SPEED_16G 0x11 /* 16 Gigabaud */ |
#define | LMT_RESERVED 0x000 /* Not used */ |
#define | LMT_1Gb 0x004 |
#define | LMT_2Gb 0x008 |
#define | LMT_4Gb 0x040 |
#define | LMT_8Gb 0x080 |
#define | LMT_10Gb 0x100 |
#define | LMT_16Gb 0x200 |
#define | lpfc_mbx_read_top_fa_SHIFT 12 |
#define | lpfc_mbx_read_top_fa_MASK 0x00000001 |
#define | lpfc_mbx_read_top_fa_WORD word2 |
#define | lpfc_mbx_read_top_mm_SHIFT 11 |
#define | lpfc_mbx_read_top_mm_MASK 0x00000001 |
#define | lpfc_mbx_read_top_mm_WORD word2 |
#define | lpfc_mbx_read_top_pb_SHIFT 9 |
#define | lpfc_mbx_read_top_pb_MASK 0X00000001 |
#define | lpfc_mbx_read_top_pb_WORD word2 |
#define | lpfc_mbx_read_top_il_SHIFT 8 |
#define | lpfc_mbx_read_top_il_MASK 0x00000001 |
#define | lpfc_mbx_read_top_il_WORD word2 |
#define | lpfc_mbx_read_top_att_type_SHIFT 0 |
#define | lpfc_mbx_read_top_att_type_MASK 0x000000FF |
#define | lpfc_mbx_read_top_att_type_WORD word2 |
#define | LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ |
#define | LPFC_ATT_LINK_UP 0x01 /* Link is up */ |
#define | LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ |
#define | lpfc_mbx_read_top_alpa_granted_SHIFT 24 |
#define | lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF |
#define | lpfc_mbx_read_top_alpa_granted_WORD word3 |
#define | lpfc_mbx_read_top_lip_alps_SHIFT 16 |
#define | lpfc_mbx_read_top_lip_alps_MASK 0x000000FF |
#define | lpfc_mbx_read_top_lip_alps_WORD word3 |
#define | lpfc_mbx_read_top_lip_type_SHIFT 8 |
#define | lpfc_mbx_read_top_lip_type_MASK 0x000000FF |
#define | lpfc_mbx_read_top_lip_type_WORD word3 |
#define | lpfc_mbx_read_top_topology_SHIFT 0 |
#define | lpfc_mbx_read_top_topology_MASK 0x000000FF |
#define | lpfc_mbx_read_top_topology_WORD word3 |
#define | LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ |
#define | LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ |
#define | LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ |
#define | LPFC_ALPA_MAP_SIZE 128 |
#define | lpfc_mbx_read_top_ld_lu_SHIFT 31 |
#define | lpfc_mbx_read_top_ld_lu_MASK 0x00000001 |
#define | lpfc_mbx_read_top_ld_lu_WORD word7 |
#define | lpfc_mbx_read_top_ld_tf_SHIFT 30 |
#define | lpfc_mbx_read_top_ld_tf_MASK 0x00000001 |
#define | lpfc_mbx_read_top_ld_tf_WORD word7 |
#define | lpfc_mbx_read_top_ld_link_spd_SHIFT 8 |
#define | lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF |
#define | lpfc_mbx_read_top_ld_link_spd_WORD word7 |
#define | lpfc_mbx_read_top_ld_nl_port_SHIFT 4 |
#define | lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F |
#define | lpfc_mbx_read_top_ld_nl_port_WORD word7 |
#define | lpfc_mbx_read_top_ld_tx_SHIFT 2 |
#define | lpfc_mbx_read_top_ld_tx_MASK 0x00000003 |
#define | lpfc_mbx_read_top_ld_tx_WORD word7 |
#define | lpfc_mbx_read_top_ld_rx_SHIFT 0 |
#define | lpfc_mbx_read_top_ld_rx_MASK 0x00000003 |
#define | lpfc_mbx_read_top_ld_rx_WORD word7 |
#define | lpfc_mbx_read_top_lu_SHIFT 31 |
#define | lpfc_mbx_read_top_lu_MASK 0x00000001 |
#define | lpfc_mbx_read_top_lu_WORD word8 |
#define | lpfc_mbx_read_top_tf_SHIFT 30 |
#define | lpfc_mbx_read_top_tf_MASK 0x00000001 |
#define | lpfc_mbx_read_top_tf_WORD word8 |
#define | lpfc_mbx_read_top_link_spd_SHIFT 8 |
#define | lpfc_mbx_read_top_link_spd_MASK 0x000000FF |
#define | lpfc_mbx_read_top_link_spd_WORD word8 |
#define | lpfc_mbx_read_top_nl_port_SHIFT 4 |
#define | lpfc_mbx_read_top_nl_port_MASK 0x0000000F |
#define | lpfc_mbx_read_top_nl_port_WORD word8 |
#define | lpfc_mbx_read_top_tx_SHIFT 2 |
#define | lpfc_mbx_read_top_tx_MASK 0x00000003 |
#define | lpfc_mbx_read_top_tx_WORD word8 |
#define | lpfc_mbx_read_top_rx_SHIFT 0 |
#define | lpfc_mbx_read_top_rx_MASK 0x00000003 |
#define | lpfc_mbx_read_top_rx_WORD word8 |
#define | LPFC_LINK_SPEED_UNKNOWN 0x0 |
#define | LPFC_LINK_SPEED_1GHZ 0x04 |
#define | LPFC_LINK_SPEED_2GHZ 0x08 |
#define | LPFC_LINK_SPEED_4GHZ 0x10 |
#define | LPFC_LINK_SPEED_8GHZ 0x20 |
#define | LPFC_LINK_SPEED_10GHZ 0x40 |
#define | LPFC_LINK_SPEED_16GHZ 0x80 |
#define | DMP_MEM_REG 0x1 |
#define | DMP_NV_PARAMS 0x2 |
#define | DMP_LMSD 0x3 /* Link Module Serial Data */ |
#define | DMP_WELL_KNOWN 0x4 |
#define | DMP_REGION_VPD 0xe |
#define | DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ |
#define | DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ |
#define | DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ |
#define | DMP_REGION_VPORT 0x16 /* VPort info region */ |
#define | DMP_VPORT_REGION_SIZE 0x200 |
#define | DMP_MBOX_OFFSET_WORD 0x5 |
#define | DMP_REGION_23 0x17 /* fcoe param and port state region */ |
#define | DMP_RGN23_SIZE 0x400 |
#define | WAKE_UP_PARMS_REGION_ID 4 |
#define | WAKE_UP_PARMS_WORD_SIZE 15 |
#define | VPORT_INFO_SIG 0x32324752 |
#define | VPORT_INFO_REV_MASK 0xff |
#define | VPORT_INFO_REV 0x1 |
#define | MAX_STATIC_VPORT_COUNT 16 |
#define | SLIMOFF 0x30 /* WORD */ |
#define | FEATURE_INITIAL_SLI2 0x01 |
#define | TYPE_NATIVE_SLI2 0x01 |
#define | MAILBOX_CMD_WSIZE 32 |
#define | MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) |
#define | MAILBOX_EXT_WSIZE 512 |
#define | MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) |
#define | MAILBOX_HBA_EXT_OFFSET 0x100 |
#define | MAILBOX_SYSFS_MAX 4096 |
#define | RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ |
#define | RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ |
#define | RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ |
#define | RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ |
#define | RJT_UNSUP_CLASS 0x05 /* Class not supported */ |
#define | RJT_DELIM_ERR 0x06 /* Delimiter usage error */ |
#define | RJT_UNSUP_TYPE 0x07 /* Type not supported */ |
#define | RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ |
#define | RJT_BAD_RCTL 0x09 /* R_CTL invalid */ |
#define | RJT_BAD_FCTL 0x0A /* F_CTL invalid */ |
#define | RJT_BAD_OXID 0x0B /* OX_ID invalid */ |
#define | RJT_BAD_RXID 0x0C /* RX_ID invalid */ |
#define | RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ |
#define | RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ |
#define | RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ |
#define | RJT_BAD_PARM 0x10 /* Param. field invalid */ |
#define | RJT_XCHG_ERR 0x11 /* Exchange error */ |
#define | RJT_PROT_ERR 0x12 /* Protocol error */ |
#define | RJT_BAD_LENGTH 0x13 /* Invalid Length */ |
#define | RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ |
#define | RJT_LOGIN_REQUIRED 0x16 /* Login required */ |
#define | RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ |
#define | RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ |
#define | RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ |
#define | RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ |
#define | RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ |
#define | IOERR_SUCCESS 0x00 /* statLocalError */ |
#define | IOERR_MISSING_CONTINUE 0x01 |
#define | IOERR_SEQUENCE_TIMEOUT 0x02 |
#define | IOERR_INTERNAL_ERROR 0x03 |
#define | IOERR_INVALID_RPI 0x04 |
#define | IOERR_NO_XRI 0x05 |
#define | IOERR_ILLEGAL_COMMAND 0x06 |
#define | IOERR_XCHG_DROPPED 0x07 |
#define | IOERR_ILLEGAL_FIELD 0x08 |
#define | IOERR_BAD_CONTINUE 0x09 |
#define | IOERR_TOO_MANY_BUFFERS 0x0A |
#define | IOERR_RCV_BUFFER_WAITING 0x0B |
#define | IOERR_NO_CONNECTION 0x0C |
#define | IOERR_TX_DMA_FAILED 0x0D |
#define | IOERR_RX_DMA_FAILED 0x0E |
#define | IOERR_ILLEGAL_FRAME 0x0F |
#define | IOERR_EXTRA_DATA 0x10 |
#define | IOERR_NO_RESOURCES 0x11 |
#define | IOERR_RESERVED 0x12 |
#define | IOERR_ILLEGAL_LENGTH 0x13 |
#define | IOERR_UNSUPPORTED_FEATURE 0x14 |
#define | IOERR_ABORT_IN_PROGRESS 0x15 |
#define | IOERR_ABORT_REQUESTED 0x16 |
#define | IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 |
#define | IOERR_LOOP_OPEN_FAILURE 0x18 |
#define | IOERR_RING_RESET 0x19 |
#define | IOERR_LINK_DOWN 0x1A |
#define | IOERR_CORRUPTED_DATA 0x1B |
#define | IOERR_CORRUPTED_RPI 0x1C |
#define | IOERR_OUT_OF_ORDER_DATA 0x1D |
#define | IOERR_OUT_OF_ORDER_ACK 0x1E |
#define | IOERR_DUP_FRAME 0x1F |
#define | IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ |
#define | IOERR_BAD_HOST_ADDRESS 0x21 |
#define | IOERR_RCV_HDRBUF_WAITING 0x22 |
#define | IOERR_MISSING_HDR_BUFFER 0x23 |
#define | IOERR_MSEQ_CHAIN_CORRUPTED 0x24 |
#define | IOERR_ABORTMULT_REQUESTED 0x25 |
#define | IOERR_BUFFER_SHORTAGE 0x28 |
#define | IOERR_DEFAULT 0x29 |
#define | IOERR_CNT 0x2A |
#define | IOERR_SLER_FAILURE 0x46 |
#define | IOERR_SLER_CMD_RCV_FAILURE 0x47 |
#define | IOERR_SLER_REC_RJT_ERR 0x48 |
#define | IOERR_SLER_REC_SRR_RETRY_ERR 0x49 |
#define | IOERR_SLER_SRR_RJT_ERR 0x4A |
#define | IOERR_SLER_RRQ_RJT_ERR 0x4C |
#define | IOERR_SLER_RRQ_RETRY_ERR 0x4D |
#define | IOERR_SLER_ABTS_ERR 0x4E |
#define | IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 |
#define | IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 |
#define | IOERR_ELXSEC_CRYPTO_ERROR 0xF2 |
#define | IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 |
#define | IOERR_DRVR_MASK 0x100 |
#define | IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ |
#define | IOERR_SLI_BRESET 0x102 |
#define | IOERR_SLI_ABORTED 0x103 |
#define | IOERR_PARAM_MASK 0x1ff |
#define | BC 0x02 /* Broadcast Received - Fctl */ |
#define | SI 0x04 /* Sequence Initiative */ |
#define | LA 0x08 /* Ignore Link Attention state */ |
#define | LS 0x80 /* Last Sequence */ |
#define | ABORT_TYPE_ABTX 0x00000000 |
#define | ABORT_TYPE_ABTS 0x00000001 |
#define | xmit_els_remoteID xrsqRo |
#define | ASYNC_TEMP_WARN 0x100 |
#define | ASYNC_TEMP_SAFE 0x101 |
#define | ASYNC_STATUS_CN 0x102 |
#define | BGS_BIDIR_BG_PROF_MASK 0xff000000 |
#define | BGS_BIDIR_BG_PROF_SHIFT 24 |
#define | BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 |
#define | BGS_BIDIR_ERR_COND_SHIFT 16 |
#define | BGS_BG_PROFILE_MASK 0x0000ff00 |
#define | BGS_BG_PROFILE_SHIFT 8 |
#define | BGS_INVALID_PROF_MASK 0x00000020 |
#define | BGS_INVALID_PROF_SHIFT 5 |
#define | BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 |
#define | BGS_UNINIT_DIF_BLOCK_SHIFT 4 |
#define | BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 |
#define | BGS_HI_WATER_MARK_PRESENT_SHIFT 3 |
#define | BGS_REFTAG_ERR_MASK 0x00000004 |
#define | BGS_REFTAG_ERR_SHIFT 2 |
#define | BGS_APPTAG_ERR_MASK 0x00000002 |
#define | BGS_APPTAG_ERR_SHIFT 1 |
#define | BGS_GUARD_ERR_MASK 0x00000001 |
#define | BGS_GUARD_ERR_SHIFT 0 |
#define | LPFC_EXT_DATA_BDE_COUNT 3 |
#define | ulpContext un1.t1.ulpContext |
#define | ulpIoTag un1.t1.ulpIoTag |
#define | ulpIoTag0 un1.t2.ulpIoTag0 |
#define | ulpCt_h ulpXS |
#define | ulpCt_l ulpFCP2Rcvy |
#define | IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ |
#define | IOCB_IP 2 /* IOCB is used for IP ELS cmds */ |
#define | PARM_UNUSED 0 /* PU field (Word 4) not used */ |
#define | PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ |
#define | PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ |
#define | PARM_NPIV_DID 3 |
#define | CLASS1 0 /* Class 1 */ |
#define | CLASS2 1 /* Class 2 */ |
#define | CLASS3 2 /* Class 3 */ |
#define | CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ |
#define | IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ |
#define | IOSTAT_FCP_RSP_ERROR 0x1 |
#define | IOSTAT_REMOTE_STOP 0x2 |
#define | IOSTAT_LOCAL_REJECT 0x3 |
#define | IOSTAT_NPORT_RJT 0x4 |
#define | IOSTAT_FABRIC_RJT 0x5 |
#define | IOSTAT_NPORT_BSY 0x6 |
#define | IOSTAT_FABRIC_BSY 0x7 |
#define | IOSTAT_INTERMED_RSP 0x8 |
#define | IOSTAT_LS_RJT 0x9 |
#define | IOSTAT_BA_RJT 0xA |
#define | IOSTAT_RSVD1 0xB |
#define | IOSTAT_RSVD2 0xC |
#define | IOSTAT_RSVD3 0xD |
#define | IOSTAT_RSVD4 0xE |
#define | IOSTAT_NEED_BUFFER 0xF |
#define | IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ |
#define | IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ |
#define | IOSTAT_CNT 0x11 |
#define | SLI1_SLIM_SIZE (4 * 1024) |
#define | SLI2_SLIM_SIZE (64 * 1024) |
#define | MAX_SLI2_IOCB 498 |
#define | MAX_SLIM_IOCB_SIZE |
#define | LPFC_TOTAL_HBQ_SIZE |
#define | MENLO_TRANSPORT_TYPE 0xfe |
#define | MENLO_CONTEXT 0 |
#define | MENLO_PU 3 |
#define | MENLO_TIMEOUT 30 |
#define | SETVAR_MLOMNT 0x103107 |
#define | SETVAR_MLORST 0x103007 |
#define | BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ |
Typedefs | |
typedef struct _LOGO | LOGO |
typedef struct _PRLI | PRLI |
typedef struct _PRLO | PRLO |
typedef struct _ADISC | ADISC |
typedef struct _FARP | FARP |
typedef struct _FAN | FAN |
typedef struct _SCR | SCR |
typedef struct _RNID_TOP_DISC | RNID_TOP_DISC |
typedef struct _RNID | RNID |
typedef struct _RPS | RPS |
typedef struct _RPS_RSP | RPS_RSP |
typedef struct _RPL | RPL |
typedef struct _PORT_NUM_BLK | PORT_NUM_BLK |
typedef struct _RPL_RSP | RPL_RSP |
typedef struct _D_ID | D_ID |
typedef struct _ELS_PKT | ELS_PKT |
typedef struct ULP_BDL | ULP_BDL |
typedef struct _SLI2_RDSC | SLI2_RDSC |
typedef struct _PCB | PCB_t |
typedef struct _IOCB | IOCB_t |
Enumerations | |
enum | lpfc_protgrp_type { LPFC_PG_TYPE_INVALID = 0, LPFC_PG_TYPE_NO_DIF, LPFC_PG_TYPE_EMBD_DIF, LPFC_PG_TYPE_DIF_BUF } |
#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ |
#define DA_ID_REQUEST_SZ |
#define DMP_REGION_23 0x17 /* fcoe param and port state region */ |
#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ |
#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ |
#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ |
#define FARP_MATCH_IPV4 |
#define FARP_MATCH_IPV6 |
#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ |
#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ |
#define FARP_NO_ACTION |
#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ |
#define FC_JEDEC_ID | ( | id | ) | ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) |
#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ |
#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ |
#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ |
#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ |
#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ |
#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ |
#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ |
#define GFF_REQUEST_SZ |
#define GID_REQUEST_SZ |
#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) |
#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) |
#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) |
#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) |
#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ |
#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ |
#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ |
#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ |
#define LPFC_BUF_RING0 |
#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ |
#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ |
#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) |
#define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ |
#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ |
#define LPFC_TOTAL_HBQ_SIZE |
#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ |
#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) |
#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) |
#define MAX_MSG_DATA |
#define MAX_SLIM_IOCB_SIZE |
#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ |
#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ |
#define REJECT_CODE 0x9 /* Unable to perform command request */ |
#define RFF_REQUEST_SZ |
#define RFT_REQUEST_SZ |
#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ |
#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ |
#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ |
#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ |
#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ |
#define RNN_REQUEST_SZ |
#define RSNN_REQUEST_SZ |
#define RSPN_REQUEST_SZ |
#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ |
#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ |
#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ |
#define SLI_MGMT_RPA 0x211 /* Register Port attributes */ |
#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ |
#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ |
#define virtual_fabric_support randomOffset /* Word 1, bit 30 */ |
typedef struct _PORT_NUM_BLK PORT_NUM_BLK |
typedef struct _RNID_TOP_DISC RNID_TOP_DISC |
typedef struct _SLI2_RDSC SLI2_RDSC |
enum lpfc_protgrp_type |