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lpfc_hw.h
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1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for *
3  * Fibre Channel Host Bus Adapters. *
4  * Copyright (C) 2004-2011 Emulex. All rights reserved. *
5  * EMULEX and SLI are trademarks of Emulex. *
6  * www.emulex.com *
7  * *
8  * This program is free software; you can redistribute it and/or *
9  * modify it under the terms of version 2 of the GNU General *
10  * Public License as published by the Free Software Foundation. *
11  * This program is distributed in the hope that it will be useful. *
12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16  * TO BE LEGALLY INVALID. See the GNU General Public License for *
17  * more details, a copy of which can be found in the file COPYING *
18  * included with this package. *
19  *******************************************************************/
20 
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30 
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33 
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38 
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40  0 */
41 
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43 
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48 
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61 
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
66 
67 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
68 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
69 
70 /* vendor ID used in SCSI netlink calls */
71 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
72 
73 #define FW_REV_STR_SIZE 32
74 /* Common Transport structures and definitions */
75 
76 union CtRevisionId {
77  /* Structure is in Big Endian format */
78  struct {
79  uint32_t Revision:8;
80  uint32_t InId:24;
81  } bits;
82  uint32_t word;
83 };
84 
85 union CtCommandResponse {
86  /* Structure is in Big Endian format */
87  struct {
88  uint32_t CmdRsp:16;
89  uint32_t Size:16;
90  } bits;
91  uint32_t word;
92 };
93 
94 #define FC4_FEATURE_INIT 0x2
95 #define FC4_FEATURE_TARGET 0x1
96 
97 struct lpfc_sli_ct_request {
98  /* Structure is in Big Endian format */
99  union CtRevisionId RevisionId;
100  uint8_t FsType;
101  uint8_t FsSubType;
102  uint8_t Options;
103  uint8_t Rsrvd1;
104  union CtCommandResponse CommandResponse;
105  uint8_t Rsrvd2;
106  uint8_t ReasonCode;
107  uint8_t Explanation;
108  uint8_t VendorUnique;
109 
110  union {
111  uint32_t PortID;
112  struct gid {
113  uint8_t PortType; /* for GID_PT requests */
114  uint8_t DomainScope;
115  uint8_t AreaScope;
116  uint8_t Fc4Type; /* for GID_FT requests */
117  } gid;
118  struct rft {
119  uint32_t PortId; /* For RFT_ID requests */
120 
121 #ifdef __BIG_ENDIAN_BITFIELD
122  uint32_t rsvd0:16;
123  uint32_t rsvd1:7;
124  uint32_t fcpReg:1; /* Type 8 */
125  uint32_t rsvd2:2;
126  uint32_t ipReg:1; /* Type 5 */
127  uint32_t rsvd3:5;
128 #else /* __LITTLE_ENDIAN_BITFIELD */
129  uint32_t rsvd0:16;
130  uint32_t fcpReg:1; /* Type 8 */
131  uint32_t rsvd1:7;
132  uint32_t rsvd3:5;
133  uint32_t ipReg:1; /* Type 5 */
134  uint32_t rsvd2:2;
135 #endif
136 
137  uint32_t rsvd[7];
138  } rft;
139  struct rnn {
140  uint32_t PortId; /* For RNN_ID requests */
141  uint8_t wwnn[8];
142  } rnn;
143  struct rsnn { /* For RSNN_ID requests */
144  uint8_t wwnn[8];
145  uint8_t len;
146  uint8_t symbname[255];
147  } rsnn;
148  struct da_id { /* For DA_ID requests */
149  uint32_t port_id;
150  } da_id;
151  struct rspn { /* For RSPN_ID requests */
152  uint32_t PortId;
153  uint8_t len;
154  uint8_t symbname[255];
155  } rspn;
156  struct gff {
157  uint32_t PortId;
158  } gff;
159  struct gff_acc {
160  uint8_t fbits[128];
161  } gff_acc;
162 #define FCP_TYPE_FEATURE_OFFSET 7
163  struct rff {
164  uint32_t PortId;
165  uint8_t reserved[2];
166  uint8_t fbits;
167  uint8_t type_code; /* type=8 for FCP */
168  } rff;
169  } un;
170 };
171 
172 #define SLI_CT_REVISION 1
173 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
174  sizeof(struct gid))
175 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
176  sizeof(struct gff))
177 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178  sizeof(struct rft))
179 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180  sizeof(struct rff))
181 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182  sizeof(struct rnn))
183 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
184  sizeof(struct rsnn))
185 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186  sizeof(struct da_id))
187 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188  sizeof(struct rspn))
189 
190 /*
191  * FsType Definitions
192  */
193 
194 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
195 #define SLI_CT_TIME_SERVICE 0xFB
196 #define SLI_CT_DIRECTORY_SERVICE 0xFC
197 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
198 
199 /*
200  * Directory Service Subtypes
201  */
202 
203 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
204 
205 /*
206  * Response Codes
207  */
208 
209 #define SLI_CT_RESPONSE_FS_RJT 0x8001
210 #define SLI_CT_RESPONSE_FS_ACC 0x8002
211 
212 /*
213  * Reason Codes
214  */
215 
216 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
217 #define SLI_CT_INVALID_COMMAND 0x01
218 #define SLI_CT_INVALID_VERSION 0x02
219 #define SLI_CT_LOGICAL_ERROR 0x03
220 #define SLI_CT_INVALID_IU_SIZE 0x04
221 #define SLI_CT_LOGICAL_BUSY 0x05
222 #define SLI_CT_PROTOCOL_ERROR 0x07
223 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
224 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
225 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
226 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
227 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
228 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
229 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
230 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
231 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
232 #define SLI_CT_VENDOR_UNIQUE 0xff
233 
234 /*
235  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
236  */
237 
238 #define SLI_CT_NO_PORT_ID 0x01
239 #define SLI_CT_NO_PORT_NAME 0x02
240 #define SLI_CT_NO_NODE_NAME 0x03
241 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
242 #define SLI_CT_NO_IP_ADDRESS 0x05
243 #define SLI_CT_NO_IPA 0x06
244 #define SLI_CT_NO_FC4_TYPES 0x07
245 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
246 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
247 #define SLI_CT_NO_PORT_TYPE 0x0A
248 #define SLI_CT_ACCESS_DENIED 0x10
249 #define SLI_CT_INVALID_PORT_ID 0x11
250 #define SLI_CT_DATABASE_EMPTY 0x12
251 
252 /*
253  * Name Server Command Codes
254  */
255 
256 #define SLI_CTNS_GA_NXT 0x0100
257 #define SLI_CTNS_GPN_ID 0x0112
258 #define SLI_CTNS_GNN_ID 0x0113
259 #define SLI_CTNS_GCS_ID 0x0114
260 #define SLI_CTNS_GFT_ID 0x0117
261 #define SLI_CTNS_GSPN_ID 0x0118
262 #define SLI_CTNS_GPT_ID 0x011A
263 #define SLI_CTNS_GFF_ID 0x011F
264 #define SLI_CTNS_GID_PN 0x0121
265 #define SLI_CTNS_GID_NN 0x0131
266 #define SLI_CTNS_GIP_NN 0x0135
267 #define SLI_CTNS_GIPA_NN 0x0136
268 #define SLI_CTNS_GSNN_NN 0x0139
269 #define SLI_CTNS_GNN_IP 0x0153
270 #define SLI_CTNS_GIPA_IP 0x0156
271 #define SLI_CTNS_GID_FT 0x0171
272 #define SLI_CTNS_GID_PT 0x01A1
273 #define SLI_CTNS_RPN_ID 0x0212
274 #define SLI_CTNS_RNN_ID 0x0213
275 #define SLI_CTNS_RCS_ID 0x0214
276 #define SLI_CTNS_RFT_ID 0x0217
277 #define SLI_CTNS_RSPN_ID 0x0218
278 #define SLI_CTNS_RPT_ID 0x021A
279 #define SLI_CTNS_RFF_ID 0x021F
280 #define SLI_CTNS_RIP_NN 0x0235
281 #define SLI_CTNS_RIPA_NN 0x0236
282 #define SLI_CTNS_RSNN_NN 0x0239
283 #define SLI_CTNS_DA_ID 0x0300
284 
285 /*
286  * Port Types
287  */
288 
289 #define SLI_CTPT_N_PORT 0x01
290 #define SLI_CTPT_NL_PORT 0x02
291 #define SLI_CTPT_FNL_PORT 0x03
292 #define SLI_CTPT_IP 0x04
293 #define SLI_CTPT_FCP 0x08
294 #define SLI_CTPT_NX_PORT 0x7F
295 #define SLI_CTPT_F_PORT 0x81
296 #define SLI_CTPT_FL_PORT 0x82
297 #define SLI_CTPT_E_PORT 0x84
298 
299 #define SLI_CT_LAST_ENTRY 0x80000000
300 
301 /* Fibre Channel Service Parameter definitions */
302 
303 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
304 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
305 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
306 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
307 
308 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
309 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
310 #define FC_PH3 0x20 /* FC-PH-3 version */
311 
312 #define FF_FRAME_SIZE 2048
313 
314 struct lpfc_name {
315  union {
316  struct {
317 #ifdef __BIG_ENDIAN_BITFIELD
318  uint8_t nameType:4; /* FC Word 0, bit 28:31 */
319  uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
320  8:11 of IEEE ext */
321 #else /* __LITTLE_ENDIAN_BITFIELD */
322  uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
323  8:11 of IEEE ext */
324  uint8_t nameType:4; /* FC Word 0, bit 28:31 */
325 #endif
326 
327 #define NAME_IEEE 0x1 /* IEEE name - nameType */
328 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
329 #define NAME_FC_TYPE 0x3 /* FC native name type */
330 #define NAME_IP_TYPE 0x4 /* IP address */
331 #define NAME_CCITT_TYPE 0xC
332 #define NAME_CCITT_GR_TYPE 0xE
333  uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
334  extended Lsb */
335  uint8_t IEEE[6]; /* FC IEEE address */
336  } s;
337  uint8_t wwn[8];
338  } u;
339 };
340 
341 struct csp {
342  uint8_t fcphHigh; /* FC Word 0, byte 0 */
343  uint8_t fcphLow;
344  uint8_t bbCreditMsb;
345  uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
346 
347 /*
348  * Word 1 Bit 31 in common service parameter is overloaded.
349  * Word 1 Bit 31 in FLOGI request is multiple NPort request
350  * Word 1 Bit 31 in FLOGI response is clean address bit
351  */
352 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
353 /*
354  * Word 1 Bit 30 in common service parameter is overloaded.
355  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
356  * Word 1 Bit 30 in PLOGI request is random offset
357  */
358 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
359 #ifdef __BIG_ENDIAN_BITFIELD
360  uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
361  uint16_t randomOffset:1; /* FC Word 1, bit 30 */
362  uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
363  uint16_t fPort:1; /* FC Word 1, bit 28 */
364  uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
365  uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
366  uint16_t multicast:1; /* FC Word 1, bit 25 */
367  uint16_t broadcast:1; /* FC Word 1, bit 24 */
368 
369  uint16_t huntgroup:1; /* FC Word 1, bit 23 */
370  uint16_t simplex:1; /* FC Word 1, bit 22 */
371  uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
372  uint16_t dhd:1; /* FC Word 1, bit 18 */
373  uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
374  uint16_t payloadlength:1; /* FC Word 1, bit 16 */
375 #else /* __LITTLE_ENDIAN_BITFIELD */
376  uint16_t broadcast:1; /* FC Word 1, bit 24 */
377  uint16_t multicast:1; /* FC Word 1, bit 25 */
378  uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
379  uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
380  uint16_t fPort:1; /* FC Word 1, bit 28 */
381  uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
382  uint16_t randomOffset:1; /* FC Word 1, bit 30 */
383  uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
384 
385  uint16_t payloadlength:1; /* FC Word 1, bit 16 */
386  uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
387  uint16_t dhd:1; /* FC Word 1, bit 18 */
388  uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
389  uint16_t simplex:1; /* FC Word 1, bit 22 */
390  uint16_t huntgroup:1; /* FC Word 1, bit 23 */
391 #endif
392 
393  uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
394  uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
395  union {
396  struct {
397  uint8_t word2Reserved1; /* FC Word 2 byte 0 */
398 
399  uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
400  uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
401 
402  uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
403  } nPort;
404  uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
405  } w2;
406 
407  uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
408 };
409 
410 struct class_parms {
411 #ifdef __BIG_ENDIAN_BITFIELD
412  uint8_t classValid:1; /* FC Word 0, bit 31 */
413  uint8_t intermix:1; /* FC Word 0, bit 30 */
414  uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
415  uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
416  uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
417  uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
418 #else /* __LITTLE_ENDIAN_BITFIELD */
419  uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
420  uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
421  uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
422  uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
423  uint8_t intermix:1; /* FC Word 0, bit 30 */
424  uint8_t classValid:1; /* FC Word 0, bit 31 */
425 
426 #endif
427 
428  uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
429 
430 #ifdef __BIG_ENDIAN_BITFIELD
431  uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
432  uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
433  uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
434  uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
435  uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
436 #else /* __LITTLE_ENDIAN_BITFIELD */
437  uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
438  uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
439  uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
440  uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
441  uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
442 #endif
443 
444  uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
445 
446 #ifdef __BIG_ENDIAN_BITFIELD
447  uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
448  uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
449  uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
450  uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
451  uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
452  uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
453 #else /* __LITTLE_ENDIAN_BITFIELD */
454  uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
455  uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
456  uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
457  uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
458  uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
459  uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
460 #endif
461 
462  uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
463  uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
464  uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
465 
466  uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
467  uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
468  uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
469  uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
470 
471  uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
472  uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
473  uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
474  uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
475 };
476 
477 struct serv_parm { /* Structure is in Big Endian format */
478  struct csp cmn;
479  struct lpfc_name portName;
480  struct lpfc_name nodeName;
481  struct class_parms cls1;
482  struct class_parms cls2;
483  struct class_parms cls3;
484  struct class_parms cls4;
485  uint8_t vendorVersion[16];
486 };
487 
488 /*
489  * Virtual Fabric Tagging Header
490  */
491 struct fc_vft_header {
492  uint32_t word0;
493 #define fc_vft_hdr_r_ctl_SHIFT 24
494 #define fc_vft_hdr_r_ctl_MASK 0xFF
495 #define fc_vft_hdr_r_ctl_WORD word0
496 #define fc_vft_hdr_ver_SHIFT 22
497 #define fc_vft_hdr_ver_MASK 0x3
498 #define fc_vft_hdr_ver_WORD word0
499 #define fc_vft_hdr_type_SHIFT 18
500 #define fc_vft_hdr_type_MASK 0xF
501 #define fc_vft_hdr_type_WORD word0
502 #define fc_vft_hdr_e_SHIFT 16
503 #define fc_vft_hdr_e_MASK 0x1
504 #define fc_vft_hdr_e_WORD word0
505 #define fc_vft_hdr_priority_SHIFT 13
506 #define fc_vft_hdr_priority_MASK 0x7
507 #define fc_vft_hdr_priority_WORD word0
508 #define fc_vft_hdr_vf_id_SHIFT 1
509 #define fc_vft_hdr_vf_id_MASK 0xFFF
510 #define fc_vft_hdr_vf_id_WORD word0
511  uint32_t word1;
512 #define fc_vft_hdr_hopct_SHIFT 24
513 #define fc_vft_hdr_hopct_MASK 0xFF
514 #define fc_vft_hdr_hopct_WORD word1
515 };
516 
517 /*
518  * Extended Link Service LS_COMMAND codes (Payload Word 0)
519  */
520 #ifdef __BIG_ENDIAN_BITFIELD
521 #define ELS_CMD_MASK 0xffff0000
522 #define ELS_RSP_MASK 0xff000000
523 #define ELS_CMD_LS_RJT 0x01000000
524 #define ELS_CMD_ACC 0x02000000
525 #define ELS_CMD_PLOGI 0x03000000
526 #define ELS_CMD_FLOGI 0x04000000
527 #define ELS_CMD_LOGO 0x05000000
528 #define ELS_CMD_ABTX 0x06000000
529 #define ELS_CMD_RCS 0x07000000
530 #define ELS_CMD_RES 0x08000000
531 #define ELS_CMD_RSS 0x09000000
532 #define ELS_CMD_RSI 0x0A000000
533 #define ELS_CMD_ESTS 0x0B000000
534 #define ELS_CMD_ESTC 0x0C000000
535 #define ELS_CMD_ADVC 0x0D000000
536 #define ELS_CMD_RTV 0x0E000000
537 #define ELS_CMD_RLS 0x0F000000
538 #define ELS_CMD_ECHO 0x10000000
539 #define ELS_CMD_TEST 0x11000000
540 #define ELS_CMD_RRQ 0x12000000
541 #define ELS_CMD_PRLI 0x20100014
542 #define ELS_CMD_PRLO 0x21100014
543 #define ELS_CMD_PRLO_ACC 0x02100014
544 #define ELS_CMD_PDISC 0x50000000
545 #define ELS_CMD_FDISC 0x51000000
546 #define ELS_CMD_ADISC 0x52000000
547 #define ELS_CMD_FARP 0x54000000
548 #define ELS_CMD_FARPR 0x55000000
549 #define ELS_CMD_RPS 0x56000000
550 #define ELS_CMD_RPL 0x57000000
551 #define ELS_CMD_FAN 0x60000000
552 #define ELS_CMD_RSCN 0x61040000
553 #define ELS_CMD_SCR 0x62000000
554 #define ELS_CMD_RNID 0x78000000
555 #define ELS_CMD_LIRR 0x7A000000
556 #else /* __LITTLE_ENDIAN_BITFIELD */
557 #define ELS_CMD_MASK 0xffff
558 #define ELS_RSP_MASK 0xff
559 #define ELS_CMD_LS_RJT 0x01
560 #define ELS_CMD_ACC 0x02
561 #define ELS_CMD_PLOGI 0x03
562 #define ELS_CMD_FLOGI 0x04
563 #define ELS_CMD_LOGO 0x05
564 #define ELS_CMD_ABTX 0x06
565 #define ELS_CMD_RCS 0x07
566 #define ELS_CMD_RES 0x08
567 #define ELS_CMD_RSS 0x09
568 #define ELS_CMD_RSI 0x0A
569 #define ELS_CMD_ESTS 0x0B
570 #define ELS_CMD_ESTC 0x0C
571 #define ELS_CMD_ADVC 0x0D
572 #define ELS_CMD_RTV 0x0E
573 #define ELS_CMD_RLS 0x0F
574 #define ELS_CMD_ECHO 0x10
575 #define ELS_CMD_TEST 0x11
576 #define ELS_CMD_RRQ 0x12
577 #define ELS_CMD_PRLI 0x14001020
578 #define ELS_CMD_PRLO 0x14001021
579 #define ELS_CMD_PRLO_ACC 0x14001002
580 #define ELS_CMD_PDISC 0x50
581 #define ELS_CMD_FDISC 0x51
582 #define ELS_CMD_ADISC 0x52
583 #define ELS_CMD_FARP 0x54
584 #define ELS_CMD_FARPR 0x55
585 #define ELS_CMD_RPS 0x56
586 #define ELS_CMD_RPL 0x57
587 #define ELS_CMD_FAN 0x60
588 #define ELS_CMD_RSCN 0x0461
589 #define ELS_CMD_SCR 0x62
590 #define ELS_CMD_RNID 0x78
591 #define ELS_CMD_LIRR 0x7A
592 #endif
593 
594 /*
595  * LS_RJT Payload Definition
596  */
597 
598 struct ls_rjt { /* Structure is in Big Endian format */
599  union {
600  uint32_t lsRjtError;
601  struct {
602  uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
603 
604  uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
605  /* LS_RJT reason codes */
606 #define LSRJT_INVALID_CMD 0x01
607 #define LSRJT_LOGICAL_ERR 0x03
608 #define LSRJT_LOGICAL_BSY 0x05
609 #define LSRJT_PROTOCOL_ERR 0x07
610 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
611 #define LSRJT_CMD_UNSUPPORTED 0x0B
612 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
613 
614  uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
615  /* LS_RJT reason explanation */
616 #define LSEXP_NOTHING_MORE 0x00
617 #define LSEXP_SPARM_OPTIONS 0x01
618 #define LSEXP_SPARM_ICTL 0x03
619 #define LSEXP_SPARM_RCTL 0x05
620 #define LSEXP_SPARM_RCV_SIZE 0x07
621 #define LSEXP_SPARM_CONCUR_SEQ 0x09
622 #define LSEXP_SPARM_CREDIT 0x0B
623 #define LSEXP_INVALID_PNAME 0x0D
624 #define LSEXP_INVALID_NNAME 0x0E
625 #define LSEXP_INVALID_CSP 0x0F
626 #define LSEXP_INVALID_ASSOC_HDR 0x11
627 #define LSEXP_ASSOC_HDR_REQ 0x13
628 #define LSEXP_INVALID_O_SID 0x15
629 #define LSEXP_INVALID_OX_RX 0x17
630 #define LSEXP_CMD_IN_PROGRESS 0x19
631 #define LSEXP_PORT_LOGIN_REQ 0x1E
632 #define LSEXP_INVALID_NPORT_ID 0x1F
633 #define LSEXP_INVALID_SEQ_ID 0x21
634 #define LSEXP_INVALID_XCHG 0x23
635 #define LSEXP_INACTIVE_XCHG 0x25
636 #define LSEXP_RQ_REQUIRED 0x27
637 #define LSEXP_OUT_OF_RESOURCE 0x29
638 #define LSEXP_CANT_GIVE_DATA 0x2A
639 #define LSEXP_REQ_UNSUPPORTED 0x2C
640  uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
641  } b;
642  } un;
643 };
644 
645 /*
646  * N_Port Login (FLOGO/PLOGO Request) Payload Definition
647  */
648 
649 typedef struct _LOGO { /* Structure is in Big Endian format */
650  union {
651  uint32_t nPortId32; /* Access nPortId as a word */
652  struct {
653  uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
654  uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
655  uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
656  uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
657  } b;
658  } un;
659  struct lpfc_name portName; /* N_port name field */
660 } LOGO;
661 
662 /*
663  * FCP Login (PRLI Request / ACC) Payload Definition
664  */
665 
666 #define PRLX_PAGE_LEN 0x10
667 #define TPRLO_PAGE_LEN 0x14
668 
669 typedef struct _PRLI { /* Structure is in Big Endian format */
670  uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
671 
672 #define PRLI_FCP_TYPE 0x08
673  uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
674 
675 #ifdef __BIG_ENDIAN_BITFIELD
676  uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
677  uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
678  uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
679 
680  /* ACC = imagePairEstablished */
681  uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
682  uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
683 #else /* __LITTLE_ENDIAN_BITFIELD */
684  uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
685  uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
686  uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
687  uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
688  uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
689  /* ACC = imagePairEstablished */
690 #endif
691 
692 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
693 #define PRLI_NO_RESOURCES 0x2
694 #define PRLI_INIT_INCOMPLETE 0x3
695 #define PRLI_NO_SUCH_PA 0x4
696 #define PRLI_PREDEF_CONFIG 0x5
697 #define PRLI_PARTIAL_SUCCESS 0x6
698 #define PRLI_INVALID_PAGE_CNT 0x7
699  uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
700 
701  uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
702 
703  uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
704 
705  uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
706  uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
707 
708 #ifdef __BIG_ENDIAN_BITFIELD
709  uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
710  uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
711  uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
712  uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
713  uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
714  uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
715  uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
716  uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
717  uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
718  uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
719  uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
720  uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
721  uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
722  uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
723  uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
724  uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
725 #else /* __LITTLE_ENDIAN_BITFIELD */
726  uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
727  uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
728  uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
729  uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
730  uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
731  uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
732  uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
733  uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
734  uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
735  uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
736  uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
737  uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
738  uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
739  uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
740  uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
741  uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
742 #endif
743 } PRLI;
744 
745 /*
746  * FCP Logout (PRLO Request / ACC) Payload Definition
747  */
748 
749 typedef struct _PRLO { /* Structure is in Big Endian format */
750  uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
751 
752 #define PRLO_FCP_TYPE 0x08
753  uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
754 
755 #ifdef __BIG_ENDIAN_BITFIELD
756  uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
757  uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
758  uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
759  uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
760 #else /* __LITTLE_ENDIAN_BITFIELD */
761  uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
762  uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
763  uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
764  uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
765 #endif
766 
767 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
768 #define PRLO_NO_SUCH_IMAGE 0x4
769 #define PRLO_INVALID_PAGE_CNT 0x7
770 
771  uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
772 
773  uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
774 
775  uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
776 
777  uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
778 } PRLO;
779 
780 typedef struct _ADISC { /* Structure is in Big Endian format */
781  uint32_t hardAL_PA;
782  struct lpfc_name portName;
783  struct lpfc_name nodeName;
784  uint32_t DID;
785 } ADISC;
786 
787 typedef struct _FARP { /* Structure is in Big Endian format */
788  uint32_t Mflags:8;
789  uint32_t Odid:24;
790 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
791  action */
792 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
793 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
794 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
795 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
796  supported */
797 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
798  supported */
799  uint32_t Rflags:8;
800  uint32_t Rdid:24;
801 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
802 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
803  struct lpfc_name OportName;
804  struct lpfc_name OnodeName;
805  struct lpfc_name RportName;
806  struct lpfc_name RnodeName;
807  uint8_t Oipaddr[16];
808  uint8_t Ripaddr[16];
809 } FARP;
810 
811 typedef struct _FAN { /* Structure is in Big Endian format */
812  uint32_t Fdid;
813  struct lpfc_name FportName;
814  struct lpfc_name FnodeName;
815 } FAN;
816 
817 typedef struct _SCR { /* Structure is in Big Endian format */
818  uint8_t resvd1;
819  uint8_t resvd2;
820  uint8_t resvd3;
821  uint8_t Function;
822 #define SCR_FUNC_FABRIC 0x01
823 #define SCR_FUNC_NPORT 0x02
824 #define SCR_FUNC_FULL 0x03
825 #define SCR_CLEAR 0xff
826 } SCR;
827 
828 typedef struct _RNID_TOP_DISC {
829  struct lpfc_name portName;
830  uint8_t resvd[8];
831  uint32_t unitType;
832 #define RNID_HBA 0x7
833 #define RNID_HOST 0xa
834 #define RNID_DRIVER 0xd
835  uint32_t physPort;
836  uint32_t attachedNodes;
837  uint16_t ipVersion;
838 #define RNID_IPV4 0x1
839 #define RNID_IPV6 0x2
840  uint16_t UDPport;
841  uint8_t ipAddr[16];
842  uint16_t resvd1;
843  uint16_t flags;
844 #define RNID_TD_SUPPORT 0x1
845 #define RNID_LP_VALID 0x2
846 } RNID_TOP_DISC;
847 
848 typedef struct _RNID { /* Structure is in Big Endian format */
849  uint8_t Format;
850 #define RNID_TOPOLOGY_DISC 0xdf
851  uint8_t CommonLen;
852  uint8_t resvd1;
853  uint8_t SpecificLen;
854  struct lpfc_name portName;
855  struct lpfc_name nodeName;
856  union {
857  RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
858  } un;
859 } RNID;
860 
861 typedef struct _RPS { /* Structure is in Big Endian format */
862  union {
863  uint32_t portNum;
864  struct lpfc_name portName;
865  } un;
866 } RPS;
867 
868 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
869  uint16_t rsvd1;
870  uint16_t portStatus;
871  uint32_t linkFailureCnt;
872  uint32_t lossSyncCnt;
873  uint32_t lossSignalCnt;
874  uint32_t primSeqErrCnt;
875  uint32_t invalidXmitWord;
876  uint32_t crcCnt;
877 } RPS_RSP;
878 
879 struct RLS { /* Structure is in Big Endian format */
880  uint32_t rls;
881 #define rls_rsvd_SHIFT 24
882 #define rls_rsvd_MASK 0x000000ff
883 #define rls_rsvd_WORD rls
884 #define rls_did_SHIFT 0
885 #define rls_did_MASK 0x00ffffff
886 #define rls_did_WORD rls
887 };
888 
889 struct RLS_RSP { /* Structure is in Big Endian format */
890  uint32_t linkFailureCnt;
891  uint32_t lossSyncCnt;
892  uint32_t lossSignalCnt;
893  uint32_t primSeqErrCnt;
894  uint32_t invalidXmitWord;
895  uint32_t crcCnt;
896 };
897 
898 struct RRQ { /* Structure is in Big Endian format */
899  uint32_t rrq;
900 #define rrq_rsvd_SHIFT 24
901 #define rrq_rsvd_MASK 0x000000ff
902 #define rrq_rsvd_WORD rrq
903 #define rrq_did_SHIFT 0
904 #define rrq_did_MASK 0x00ffffff
905 #define rrq_did_WORD rrq
906  uint32_t rrq_exchg;
907 #define rrq_oxid_SHIFT 16
908 #define rrq_oxid_MASK 0xffff
909 #define rrq_oxid_WORD rrq_exchg
910 #define rrq_rxid_SHIFT 0
911 #define rrq_rxid_MASK 0xffff
912 #define rrq_rxid_WORD rrq_exchg
913 };
914 
915 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
916 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
917 
918 struct RTV_RSP { /* Structure is in Big Endian format */
919  uint32_t ratov;
920  uint32_t edtov;
921  uint32_t qtov;
922 #define qtov_rsvd0_SHIFT 28
923 #define qtov_rsvd0_MASK 0x0000000f
924 #define qtov_rsvd0_WORD qtov /* reserved */
925 #define qtov_edtovres_SHIFT 27
926 #define qtov_edtovres_MASK 0x00000001
927 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
928 #define qtov__rsvd1_SHIFT 19
929 #define qtov_rsvd1_MASK 0x0000003f
930 #define qtov_rsvd1_WORD qtov /* reserved */
931 #define qtov_rttov_SHIFT 18
932 #define qtov_rttov_MASK 0x00000001
933 #define qtov_rttov_WORD qtov /* R_T_TOV value */
934 #define qtov_rsvd2_SHIFT 0
935 #define qtov_rsvd2_MASK 0x0003ffff
936 #define qtov_rsvd2_WORD qtov /* reserved */
937 };
938 
939 
940 typedef struct _RPL { /* Structure is in Big Endian format */
941  uint32_t maxsize;
942  uint32_t index;
943 } RPL;
944 
945 typedef struct _PORT_NUM_BLK {
946  uint32_t portNum;
947  uint32_t portID;
948  struct lpfc_name portName;
949 } PORT_NUM_BLK;
950 
951 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
952  uint32_t listLen;
953  uint32_t index;
954  PORT_NUM_BLK port_num_blk;
955 } RPL_RSP;
956 
957 /* This is used for RSCN command */
958 typedef struct _D_ID { /* Structure is in Big Endian format */
959  union {
960  uint32_t word;
961  struct {
962 #ifdef __BIG_ENDIAN_BITFIELD
963  uint8_t resv;
964  uint8_t domain;
965  uint8_t area;
966  uint8_t id;
967 #else /* __LITTLE_ENDIAN_BITFIELD */
968  uint8_t id;
969  uint8_t area;
970  uint8_t domain;
971  uint8_t resv;
972 #endif
973  } b;
974  } un;
975 } D_ID;
976 
977 #define RSCN_ADDRESS_FORMAT_PORT 0x0
978 #define RSCN_ADDRESS_FORMAT_AREA 0x1
979 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
980 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
981 #define RSCN_ADDRESS_FORMAT_MASK 0x3
982 
983 /*
984  * Structure to define all ELS Payload types
985  */
986 
987 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
988  uint8_t elsCode; /* FC Word 0, bit 24:31 */
989  uint8_t elsByte1;
990  uint8_t elsByte2;
991  uint8_t elsByte3;
992  union {
993  struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
994  struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
995  LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
996  PRLI prli; /* Payload for PRLI/ACC */
997  PRLO prlo; /* Payload for PRLO/ACC */
998  ADISC adisc; /* Payload for ADISC/ACC */
999  FARP farp; /* Payload for FARP/ACC */
1000  FAN fan; /* Payload for FAN */
1001  SCR scr; /* Payload for SCR/ACC */
1002  RNID rnid; /* Payload for RNID */
1003  uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1004  } un;
1005 } ELS_PKT;
1006 
1007 /*
1008  * FDMI
1009  * HBA MAnagement Operations Command Codes
1010  */
1011 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1012 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1013 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1014 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1015 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1016 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1017 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1018 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1019 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1020 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1021 
1022 /*
1023  * Management Service Subtypes
1024  */
1025 #define SLI_CT_FDMI_Subtypes 0x10
1026 
1027 /*
1028  * HBA Management Service Reject Code
1029  */
1030 #define REJECT_CODE 0x9 /* Unable to perform command request */
1031 
1032 /*
1033  * HBA Management Service Reject Reason Code
1034  * Please refer to the Reason Codes above
1035  */
1036 
1037 /*
1038  * HBA Attribute Types
1039  */
1040 #define NODE_NAME 0x1
1041 #define MANUFACTURER 0x2
1042 #define SERIAL_NUMBER 0x3
1043 #define MODEL 0x4
1044 #define MODEL_DESCRIPTION 0x5
1045 #define HARDWARE_VERSION 0x6
1046 #define DRIVER_VERSION 0x7
1047 #define OPTION_ROM_VERSION 0x8
1048 #define FIRMWARE_VERSION 0x9
1049 #define OS_NAME_VERSION 0xa
1050 #define MAX_CT_PAYLOAD_LEN 0xb
1051 
1052 /*
1053  * Port Attrubute Types
1054  */
1055 #define SUPPORTED_FC4_TYPES 0x1
1056 #define SUPPORTED_SPEED 0x2
1057 #define PORT_SPEED 0x3
1058 #define MAX_FRAME_SIZE 0x4
1059 #define OS_DEVICE_NAME 0x5
1060 #define HOST_NAME 0x6
1061 
1062 union AttributesDef {
1063  /* Structure is in Big Endian format */
1064  struct {
1065  uint32_t AttrType:16;
1066  uint32_t AttrLen:16;
1067  } bits;
1068  uint32_t word;
1069 };
1070 
1071 
1072 /*
1073  * HBA Attribute Entry (8 - 260 bytes)
1074  */
1075 typedef struct {
1076  union AttributesDef ad;
1077  union {
1078  uint32_t VendorSpecific;
1079  uint8_t Manufacturer[64];
1080  uint8_t SerialNumber[64];
1081  uint8_t Model[256];
1082  uint8_t ModelDescription[256];
1083  uint8_t HardwareVersion[256];
1084  uint8_t DriverVersion[256];
1085  uint8_t OptionROMVersion[256];
1086  uint8_t FirmwareVersion[256];
1087  struct lpfc_name NodeName;
1088  uint8_t SupportFC4Types[32];
1089  uint32_t SupportSpeed;
1090  uint32_t PortSpeed;
1091  uint32_t MaxFrameSize;
1092  uint8_t OsDeviceName[256];
1093  uint8_t OsNameVersion[256];
1094  uint32_t MaxCTPayloadLen;
1095  uint8_t HostName[256];
1096  } un;
1097 } ATTRIBUTE_ENTRY;
1098 
1099 /*
1100  * HBA Attribute Block
1101  */
1102 typedef struct {
1103  uint32_t EntryCnt; /* Number of HBA attribute entries */
1104  ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1105 } ATTRIBUTE_BLOCK;
1106 
1107 /*
1108  * Port Entry
1109  */
1110 typedef struct {
1111  struct lpfc_name PortName;
1112 } PORT_ENTRY;
1113 
1114 /*
1115  * HBA Identifier
1116  */
1117 typedef struct {
1118  struct lpfc_name PortName;
1119 } HBA_IDENTIFIER;
1120 
1121 /*
1122  * Registered Port List Format
1123  */
1124 typedef struct {
1125  uint32_t EntryCnt;
1126  PORT_ENTRY pe; /* Variable-length array */
1127 } REG_PORT_LIST;
1128 
1129 /*
1130  * Register HBA(RHBA)
1131  */
1132 typedef struct {
1133  HBA_IDENTIFIER hi;
1134  REG_PORT_LIST rpl; /* variable-length array */
1135 /* ATTRIBUTE_BLOCK ab; */
1136 } REG_HBA;
1137 
1138 /*
1139  * Register HBA Attributes (RHAT)
1140  */
1141 typedef struct {
1142  struct lpfc_name HBA_PortName;
1143  ATTRIBUTE_BLOCK ab;
1144 } REG_HBA_ATTRIBUTE;
1145 
1146 /*
1147  * Register Port Attributes (RPA)
1148  */
1149 typedef struct {
1150  struct lpfc_name PortName;
1151  ATTRIBUTE_BLOCK ab;
1152 } REG_PORT_ATTRIBUTE;
1153 
1154 /*
1155  * Get Registered HBA List (GRHL) Accept Payload Format
1156  */
1157 typedef struct {
1158  uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1159  struct lpfc_name HBA_PortName; /* Variable-length array */
1160 } GRHL_ACC_PAYLOAD;
1161 
1162 /*
1163  * Get Registered Port List (GRPL) Accept Payload Format
1164  */
1165 typedef struct {
1166  uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1167  PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1168 } GRPL_ACC_PAYLOAD;
1169 
1170 /*
1171  * Get Port Attributes (GPAT) Accept Payload Format
1172  */
1173 
1174 typedef struct {
1175  ATTRIBUTE_BLOCK pab;
1176 } GPAT_ACC_PAYLOAD;
1177 
1178 
1179 /*
1180  * Begin HBA configuration parameters.
1181  * The PCI configuration register BAR assignments are:
1182  * BAR0, offset 0x10 - SLIM base memory address
1183  * BAR1, offset 0x14 - SLIM base memory high address
1184  * BAR2, offset 0x18 - REGISTER base memory address
1185  * BAR3, offset 0x1c - REGISTER base memory high address
1186  * BAR4, offset 0x20 - BIU I/O registers
1187  * BAR5, offset 0x24 - REGISTER base io high address
1188  */
1189 
1190 /* Number of rings currently used and available. */
1191 #define MAX_SLI3_CONFIGURED_RINGS 3
1192 #define MAX_SLI3_RINGS 4
1193 
1194 /* IOCB / Mailbox is owned by FireFly */
1195 #define OWN_CHIP 1
1196 
1197 /* IOCB / Mailbox is owned by Host */
1198 #define OWN_HOST 0
1199 
1200 /* Number of 4-byte words in an IOCB. */
1201 #define IOCB_WORD_SZ 8
1202 
1203 /* network headers for Dfctl field */
1204 #define FC_NET_HDR 0x20
1205 
1206 /* Start FireFly Register definitions */
1207 #define PCI_VENDOR_ID_EMULEX 0x10df
1208 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1209 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1210 #define PCI_DEVICE_ID_BALIUS 0xe131
1211 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1212 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1213 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1214 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1215 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1216 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1217 #define PCI_DEVICE_ID_SAT_MID 0xf015
1218 #define PCI_DEVICE_ID_RFLY 0xf095
1219 #define PCI_DEVICE_ID_PFLY 0xf098
1220 #define PCI_DEVICE_ID_LP101 0xf0a1
1221 #define PCI_DEVICE_ID_TFLY 0xf0a5
1222 #define PCI_DEVICE_ID_BSMB 0xf0d1
1223 #define PCI_DEVICE_ID_BMID 0xf0d5
1224 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1225 #define PCI_DEVICE_ID_ZMID 0xf0e5
1226 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1227 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1228 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1229 #define PCI_DEVICE_ID_SAT 0xf100
1230 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1231 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1232 #define PCI_DEVICE_ID_FALCON 0xf180
1233 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1234 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1235 #define PCI_DEVICE_ID_CENTAUR 0xf900
1236 #define PCI_DEVICE_ID_PEGASUS 0xf980
1237 #define PCI_DEVICE_ID_THOR 0xfa00
1238 #define PCI_DEVICE_ID_VIPER 0xfb00
1239 #define PCI_DEVICE_ID_LP10000S 0xfc00
1240 #define PCI_DEVICE_ID_LP11000S 0xfc10
1241 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1242 #define PCI_DEVICE_ID_SAT_S 0xfc40
1243 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1244 #define PCI_DEVICE_ID_HELIOS 0xfd00
1245 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1246 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1247 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1248 #define PCI_DEVICE_ID_HORNET 0xfe05
1249 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1250 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1251 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1252 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1253 #define PCI_DEVICE_ID_TOMCAT 0x0714
1254 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1255 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1256 
1257 #define JEDEC_ID_ADDRESS 0x0080001c
1258 #define FIREFLY_JEDEC_ID 0x1ACC
1259 #define SUPERFLY_JEDEC_ID 0x0020
1260 #define DRAGONFLY_JEDEC_ID 0x0021
1261 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1262 #define CENTAUR_2G_JEDEC_ID 0x0026
1263 #define CENTAUR_1G_JEDEC_ID 0x0028
1264 #define PEGASUS_ORION_JEDEC_ID 0x0036
1265 #define PEGASUS_JEDEC_ID 0x0038
1266 #define THOR_JEDEC_ID 0x0012
1267 #define HELIOS_JEDEC_ID 0x0364
1268 #define ZEPHYR_JEDEC_ID 0x0577
1269 #define VIPER_JEDEC_ID 0x4838
1270 #define SATURN_JEDEC_ID 0x1004
1271 #define HORNET_JDEC_ID 0x2057706D
1272 
1273 #define JEDEC_ID_MASK 0x0FFFF000
1274 #define JEDEC_ID_SHIFT 12
1275 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1276 
1277 typedef struct { /* FireFly BIU registers */
1278  uint32_t hostAtt; /* See definitions for Host Attention
1279  register */
1280  uint32_t chipAtt; /* See definitions for Chip Attention
1281  register */
1282  uint32_t hostStatus; /* See definitions for Host Status register */
1283  uint32_t hostControl; /* See definitions for Host Control register */
1284  uint32_t buiConfig; /* See definitions for BIU configuration
1285  register */
1286 } FF_REGS;
1287 
1288 /* IO Register size in bytes */
1289 #define FF_REG_AREA_SIZE 256
1290 
1291 /* Host Attention Register */
1292 
1293 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1294 
1295 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1296 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1297 #define HA_R0ATT 0x00000008 /* Bit 3 */
1298 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1299 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1300 #define HA_R1ATT 0x00000080 /* Bit 7 */
1301 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1302 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1303 #define HA_R2ATT 0x00000800 /* Bit 11 */
1304 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1305 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1306 #define HA_R3ATT 0x00008000 /* Bit 15 */
1307 #define HA_LATT 0x20000000 /* Bit 29 */
1308 #define HA_MBATT 0x40000000 /* Bit 30 */
1309 #define HA_ERATT 0x80000000 /* Bit 31 */
1310 
1311 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1312 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1313 #define HA_RXATT 0x00000008 /* Bit 3 */
1314 #define HA_RXMASK 0x0000000f
1315 
1316 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1317 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1318 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1319 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1320 
1321 #define HA_R0_POS 3
1322 #define HA_R1_POS 7
1323 #define HA_R2_POS 11
1324 #define HA_R3_POS 15
1325 #define HA_LE_POS 29
1326 #define HA_MB_POS 30
1327 #define HA_ER_POS 31
1328 /* Chip Attention Register */
1329 
1330 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1331 
1332 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1333 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1334 #define CA_R0ATT 0x00000008 /* Bit 3 */
1335 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1336 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1337 #define CA_R1ATT 0x00000080 /* Bit 7 */
1338 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1339 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1340 #define CA_R2ATT 0x00000800 /* Bit 11 */
1341 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1342 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1343 #define CA_R3ATT 0x00008000 /* Bit 15 */
1344 #define CA_MBATT 0x40000000 /* Bit 30 */
1345 
1346 /* Host Status Register */
1347 
1348 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1349 
1350 #define HS_MBRDY 0x00400000 /* Bit 22 */
1351 #define HS_FFRDY 0x00800000 /* Bit 23 */
1352 #define HS_FFER8 0x01000000 /* Bit 24 */
1353 #define HS_FFER7 0x02000000 /* Bit 25 */
1354 #define HS_FFER6 0x04000000 /* Bit 26 */
1355 #define HS_FFER5 0x08000000 /* Bit 27 */
1356 #define HS_FFER4 0x10000000 /* Bit 28 */
1357 #define HS_FFER3 0x20000000 /* Bit 29 */
1358 #define HS_FFER2 0x40000000 /* Bit 30 */
1359 #define HS_FFER1 0x80000000 /* Bit 31 */
1360 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1361 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1362 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1363 /* Host Control Register */
1364 
1365 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1366 
1367 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1368 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1369 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1370 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1371 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1372 #define HC_INITHBI 0x02000000 /* Bit 25 */
1373 #define HC_INITMB 0x04000000 /* Bit 26 */
1374 #define HC_INITFF 0x08000000 /* Bit 27 */
1375 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1376 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1377 
1378 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1379 #define MSIX_DFLT_ID 0
1380 #define MSIX_RNG0_ID 0
1381 #define MSIX_RNG1_ID 1
1382 #define MSIX_RNG2_ID 2
1383 #define MSIX_RNG3_ID 3
1384 
1385 #define MSIX_LINK_ID 4
1386 #define MSIX_MBOX_ID 5
1387 
1388 #define MSIX_SPARE0_ID 6
1389 #define MSIX_SPARE1_ID 7
1390 
1391 /* Mailbox Commands */
1392 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1393 #define MBX_LOAD_SM 0x01
1394 #define MBX_READ_NV 0x02
1395 #define MBX_WRITE_NV 0x03
1396 #define MBX_RUN_BIU_DIAG 0x04
1397 #define MBX_INIT_LINK 0x05
1398 #define MBX_DOWN_LINK 0x06
1399 #define MBX_CONFIG_LINK 0x07
1400 #define MBX_CONFIG_RING 0x09
1401 #define MBX_RESET_RING 0x0A
1402 #define MBX_READ_CONFIG 0x0B
1403 #define MBX_READ_RCONFIG 0x0C
1404 #define MBX_READ_SPARM 0x0D
1405 #define MBX_READ_STATUS 0x0E
1406 #define MBX_READ_RPI 0x0F
1407 #define MBX_READ_XRI 0x10
1408 #define MBX_READ_REV 0x11
1409 #define MBX_READ_LNK_STAT 0x12
1410 #define MBX_REG_LOGIN 0x13
1411 #define MBX_UNREG_LOGIN 0x14
1412 #define MBX_CLEAR_LA 0x16
1413 #define MBX_DUMP_MEMORY 0x17
1414 #define MBX_DUMP_CONTEXT 0x18
1415 #define MBX_RUN_DIAGS 0x19
1416 #define MBX_RESTART 0x1A
1417 #define MBX_UPDATE_CFG 0x1B
1418 #define MBX_DOWN_LOAD 0x1C
1419 #define MBX_DEL_LD_ENTRY 0x1D
1420 #define MBX_RUN_PROGRAM 0x1E
1421 #define MBX_SET_MASK 0x20
1422 #define MBX_SET_VARIABLE 0x21
1423 #define MBX_UNREG_D_ID 0x23
1424 #define MBX_KILL_BOARD 0x24
1425 #define MBX_CONFIG_FARP 0x25
1426 #define MBX_BEACON 0x2A
1427 #define MBX_CONFIG_MSI 0x30
1428 #define MBX_HEARTBEAT 0x31
1429 #define MBX_WRITE_VPARMS 0x32
1430 #define MBX_ASYNCEVT_ENABLE 0x33
1431 #define MBX_READ_EVENT_LOG_STATUS 0x37
1432 #define MBX_READ_EVENT_LOG 0x38
1433 #define MBX_WRITE_EVENT_LOG 0x39
1434 
1435 #define MBX_PORT_CAPABILITIES 0x3B
1436 #define MBX_PORT_IOV_CONTROL 0x3C
1437 
1438 #define MBX_CONFIG_HBQ 0x7C
1439 #define MBX_LOAD_AREA 0x81
1440 #define MBX_RUN_BIU_DIAG64 0x84
1441 #define MBX_CONFIG_PORT 0x88
1442 #define MBX_READ_SPARM64 0x8D
1443 #define MBX_READ_RPI64 0x8F
1444 #define MBX_REG_LOGIN64 0x93
1445 #define MBX_READ_TOPOLOGY 0x95
1446 #define MBX_REG_VPI 0x96
1447 #define MBX_UNREG_VPI 0x97
1448 
1449 #define MBX_WRITE_WWN 0x98
1450 #define MBX_SET_DEBUG 0x99
1451 #define MBX_LOAD_EXP_ROM 0x9C
1452 #define MBX_SLI4_CONFIG 0x9B
1453 #define MBX_SLI4_REQ_FTRS 0x9D
1454 #define MBX_MAX_CMDS 0x9E
1455 #define MBX_RESUME_RPI 0x9E
1456 #define MBX_SLI2_CMD_MASK 0x80
1457 #define MBX_REG_VFI 0x9F
1458 #define MBX_REG_FCFI 0xA0
1459 #define MBX_UNREG_VFI 0xA1
1460 #define MBX_UNREG_FCFI 0xA2
1461 #define MBX_INIT_VFI 0xA3
1462 #define MBX_INIT_VPI 0xA4
1463 #define MBX_ACCESS_VDATA 0xA5
1464 
1465 #define MBX_AUTH_PORT 0xF8
1466 #define MBX_SECURITY_MGMT 0xF9
1467 
1468 /* IOCB Commands */
1469 
1470 #define CMD_RCV_SEQUENCE_CX 0x01
1471 #define CMD_XMIT_SEQUENCE_CR 0x02
1472 #define CMD_XMIT_SEQUENCE_CX 0x03
1473 #define CMD_XMIT_BCAST_CN 0x04
1474 #define CMD_XMIT_BCAST_CX 0x05
1475 #define CMD_QUE_RING_BUF_CN 0x06
1476 #define CMD_QUE_XRI_BUF_CX 0x07
1477 #define CMD_IOCB_CONTINUE_CN 0x08
1478 #define CMD_RET_XRI_BUF_CX 0x09
1479 #define CMD_ELS_REQUEST_CR 0x0A
1480 #define CMD_ELS_REQUEST_CX 0x0B
1481 #define CMD_RCV_ELS_REQ_CX 0x0D
1482 #define CMD_ABORT_XRI_CN 0x0E
1483 #define CMD_ABORT_XRI_CX 0x0F
1484 #define CMD_CLOSE_XRI_CN 0x10
1485 #define CMD_CLOSE_XRI_CX 0x11
1486 #define CMD_CREATE_XRI_CR 0x12
1487 #define CMD_CREATE_XRI_CX 0x13
1488 #define CMD_GET_RPI_CN 0x14
1489 #define CMD_XMIT_ELS_RSP_CX 0x15
1490 #define CMD_GET_RPI_CR 0x16
1491 #define CMD_XRI_ABORTED_CX 0x17
1492 #define CMD_FCP_IWRITE_CR 0x18
1493 #define CMD_FCP_IWRITE_CX 0x19
1494 #define CMD_FCP_IREAD_CR 0x1A
1495 #define CMD_FCP_IREAD_CX 0x1B
1496 #define CMD_FCP_ICMND_CR 0x1C
1497 #define CMD_FCP_ICMND_CX 0x1D
1498 #define CMD_FCP_TSEND_CX 0x1F
1499 #define CMD_FCP_TRECEIVE_CX 0x21
1500 #define CMD_FCP_TRSP_CX 0x23
1501 #define CMD_FCP_AUTO_TRSP_CX 0x29
1502 
1503 #define CMD_ADAPTER_MSG 0x20
1504 #define CMD_ADAPTER_DUMP 0x22
1505 
1506 /* SLI_2 IOCB Command Set */
1507 
1508 #define CMD_ASYNC_STATUS 0x7C
1509 #define CMD_RCV_SEQUENCE64_CX 0x81
1510 #define CMD_XMIT_SEQUENCE64_CR 0x82
1511 #define CMD_XMIT_SEQUENCE64_CX 0x83
1512 #define CMD_XMIT_BCAST64_CN 0x84
1513 #define CMD_XMIT_BCAST64_CX 0x85
1514 #define CMD_QUE_RING_BUF64_CN 0x86
1515 #define CMD_QUE_XRI_BUF64_CX 0x87
1516 #define CMD_IOCB_CONTINUE64_CN 0x88
1517 #define CMD_RET_XRI_BUF64_CX 0x89
1518 #define CMD_ELS_REQUEST64_CR 0x8A
1519 #define CMD_ELS_REQUEST64_CX 0x8B
1520 #define CMD_ABORT_MXRI64_CN 0x8C
1521 #define CMD_RCV_ELS_REQ64_CX 0x8D
1522 #define CMD_XMIT_ELS_RSP64_CX 0x95
1523 #define CMD_XMIT_BLS_RSP64_CX 0x97
1524 #define CMD_FCP_IWRITE64_CR 0x98
1525 #define CMD_FCP_IWRITE64_CX 0x99
1526 #define CMD_FCP_IREAD64_CR 0x9A
1527 #define CMD_FCP_IREAD64_CX 0x9B
1528 #define CMD_FCP_ICMND64_CR 0x9C
1529 #define CMD_FCP_ICMND64_CX 0x9D
1530 #define CMD_FCP_TSEND64_CX 0x9F
1531 #define CMD_FCP_TRECEIVE64_CX 0xA1
1532 #define CMD_FCP_TRSP64_CX 0xA3
1533 
1534 #define CMD_QUE_XRI64_CX 0xB3
1535 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1536 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1537 #define CMD_IOCB_RET_XRI64_CX 0xB9
1538 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1539 
1540 #define CMD_GEN_REQUEST64_CR 0xC2
1541 #define CMD_GEN_REQUEST64_CX 0xC3
1542 
1543 /* Unhandled SLI-3 Commands */
1544 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1545 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1546 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1547 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1548 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1549 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1550 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1551 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1552 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1553 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1554 #define CMD_IOCB_LOGENTRY_CN 0x94
1555 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1556 
1557 /* Data Security SLI Commands */
1558 #define DSSCMD_IWRITE64_CR 0xF8
1559 #define DSSCMD_IWRITE64_CX 0xF9
1560 #define DSSCMD_IREAD64_CR 0xFA
1561 #define DSSCMD_IREAD64_CX 0xFB
1562 
1563 #define CMD_MAX_IOCB_CMD 0xFB
1564 #define CMD_IOCB_MASK 0xff
1565 
1566 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1567  iocb */
1568 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1569 /*
1570  * Define Status
1571  */
1572 #define MBX_SUCCESS 0
1573 #define MBXERR_NUM_RINGS 1
1574 #define MBXERR_NUM_IOCBS 2
1575 #define MBXERR_IOCBS_EXCEEDED 3
1576 #define MBXERR_BAD_RING_NUMBER 4
1577 #define MBXERR_MASK_ENTRIES_RANGE 5
1578 #define MBXERR_MASKS_EXCEEDED 6
1579 #define MBXERR_BAD_PROFILE 7
1580 #define MBXERR_BAD_DEF_CLASS 8
1581 #define MBXERR_BAD_MAX_RESPONDER 9
1582 #define MBXERR_BAD_MAX_ORIGINATOR 10
1583 #define MBXERR_RPI_REGISTERED 11
1584 #define MBXERR_RPI_FULL 12
1585 #define MBXERR_NO_RESOURCES 13
1586 #define MBXERR_BAD_RCV_LENGTH 14
1587 #define MBXERR_DMA_ERROR 15
1588 #define MBXERR_ERROR 16
1589 #define MBXERR_LINK_DOWN 0x33
1590 #define MBXERR_SEC_NO_PERMISSION 0xF02
1591 #define MBX_NOT_FINISHED 255
1592 
1593 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1594 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1595 
1596 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1597 
1598 /*
1599  * Begin Structure Definitions for Mailbox Commands
1600  */
1601 
1602 typedef struct {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604  uint8_t tval;
1605  uint8_t tmask;
1606  uint8_t rval;
1607  uint8_t rmask;
1608 #else /* __LITTLE_ENDIAN_BITFIELD */
1609  uint8_t rmask;
1610  uint8_t rval;
1611  uint8_t tmask;
1612  uint8_t tval;
1613 #endif
1614 } RR_REG;
1615 
1616 struct ulp_bde {
1617  uint32_t bdeAddress;
1618 #ifdef __BIG_ENDIAN_BITFIELD
1619  uint32_t bdeReserved:4;
1620  uint32_t bdeAddrHigh:4;
1621  uint32_t bdeSize:24;
1622 #else /* __LITTLE_ENDIAN_BITFIELD */
1623  uint32_t bdeSize:24;
1624  uint32_t bdeAddrHigh:4;
1625  uint32_t bdeReserved:4;
1626 #endif
1627 };
1628 
1629 typedef struct ULP_BDL { /* SLI-2 */
1630 #ifdef __BIG_ENDIAN_BITFIELD
1631  uint32_t bdeFlags:8; /* BDL Flags */
1632  uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1633 #else /* __LITTLE_ENDIAN_BITFIELD */
1634  uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1635  uint32_t bdeFlags:8; /* BDL Flags */
1636 #endif
1637 
1638  uint32_t addrLow; /* Address 0:31 */
1639  uint32_t addrHigh; /* Address 32:63 */
1640  uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1641 } ULP_BDL;
1642 
1643 /*
1644  * BlockGuard Definitions
1645  */
1646 
1647 enum lpfc_protgrp_type {
1648  LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1649  LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1650  LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1651  LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1652 };
1653 
1654 /* PDE Descriptors */
1655 #define LPFC_PDE5_DESCRIPTOR 0x85
1656 #define LPFC_PDE6_DESCRIPTOR 0x86
1657 #define LPFC_PDE7_DESCRIPTOR 0x87
1658 
1659 /* BlockGuard Opcodes */
1660 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1661 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1662 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1663 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1664 #define BG_OP_IN_CRC_OUT_CRC 0x4
1665 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1666 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1667 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1668 
1669 struct lpfc_pde5 {
1670  uint32_t word0;
1671 #define pde5_type_SHIFT 24
1672 #define pde5_type_MASK 0x000000ff
1673 #define pde5_type_WORD word0
1674 #define pde5_rsvd0_SHIFT 0
1675 #define pde5_rsvd0_MASK 0x00ffffff
1676 #define pde5_rsvd0_WORD word0
1677  uint32_t reftag; /* Reference Tag Value */
1678  uint32_t reftagtr; /* Reference Tag Translation Value */
1679 };
1680 
1681 struct lpfc_pde6 {
1682  uint32_t word0;
1683 #define pde6_type_SHIFT 24
1684 #define pde6_type_MASK 0x000000ff
1685 #define pde6_type_WORD word0
1686 #define pde6_rsvd0_SHIFT 0
1687 #define pde6_rsvd0_MASK 0x00ffffff
1688 #define pde6_rsvd0_WORD word0
1689  uint32_t word1;
1690 #define pde6_rsvd1_SHIFT 26
1691 #define pde6_rsvd1_MASK 0x0000003f
1692 #define pde6_rsvd1_WORD word1
1693 #define pde6_na_SHIFT 25
1694 #define pde6_na_MASK 0x00000001
1695 #define pde6_na_WORD word1
1696 #define pde6_rsvd2_SHIFT 16
1697 #define pde6_rsvd2_MASK 0x000001FF
1698 #define pde6_rsvd2_WORD word1
1699 #define pde6_apptagtr_SHIFT 0
1700 #define pde6_apptagtr_MASK 0x0000ffff
1701 #define pde6_apptagtr_WORD word1
1702  uint32_t word2;
1703 #define pde6_optx_SHIFT 28
1704 #define pde6_optx_MASK 0x0000000f
1705 #define pde6_optx_WORD word2
1706 #define pde6_oprx_SHIFT 24
1707 #define pde6_oprx_MASK 0x0000000f
1708 #define pde6_oprx_WORD word2
1709 #define pde6_nr_SHIFT 23
1710 #define pde6_nr_MASK 0x00000001
1711 #define pde6_nr_WORD word2
1712 #define pde6_ce_SHIFT 22
1713 #define pde6_ce_MASK 0x00000001
1714 #define pde6_ce_WORD word2
1715 #define pde6_re_SHIFT 21
1716 #define pde6_re_MASK 0x00000001
1717 #define pde6_re_WORD word2
1718 #define pde6_ae_SHIFT 20
1719 #define pde6_ae_MASK 0x00000001
1720 #define pde6_ae_WORD word2
1721 #define pde6_ai_SHIFT 19
1722 #define pde6_ai_MASK 0x00000001
1723 #define pde6_ai_WORD word2
1724 #define pde6_bs_SHIFT 16
1725 #define pde6_bs_MASK 0x00000007
1726 #define pde6_bs_WORD word2
1727 #define pde6_apptagval_SHIFT 0
1728 #define pde6_apptagval_MASK 0x0000ffff
1729 #define pde6_apptagval_WORD word2
1730 };
1731 
1732 struct lpfc_pde7 {
1733  uint32_t word0;
1734 #define pde7_type_SHIFT 24
1735 #define pde7_type_MASK 0x000000ff
1736 #define pde7_type_WORD word0
1737 #define pde7_rsvd0_SHIFT 0
1738 #define pde7_rsvd0_MASK 0x00ffffff
1739 #define pde7_rsvd0_WORD word0
1740  uint32_t addrHigh;
1741  uint32_t addrLow;
1742 };
1743 
1744 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1745 
1746 typedef struct {
1747 #ifdef __BIG_ENDIAN_BITFIELD
1748  uint32_t rsvd2:25;
1749  uint32_t acknowledgment:1;
1750  uint32_t version:1;
1751  uint32_t erase_or_prog:1;
1752  uint32_t update_flash:1;
1753  uint32_t update_ram:1;
1754  uint32_t method:1;
1755  uint32_t load_cmplt:1;
1756 #else /* __LITTLE_ENDIAN_BITFIELD */
1757  uint32_t load_cmplt:1;
1758  uint32_t method:1;
1759  uint32_t update_ram:1;
1760  uint32_t update_flash:1;
1761  uint32_t erase_or_prog:1;
1762  uint32_t version:1;
1763  uint32_t acknowledgment:1;
1764  uint32_t rsvd2:25;
1765 #endif
1766 
1767  uint32_t dl_to_adr_low;
1768  uint32_t dl_to_adr_high;
1769  uint32_t dl_len;
1770  union {
1771  uint32_t dl_from_mbx_offset;
1772  struct ulp_bde dl_from_bde;
1773  struct ulp_bde64 dl_from_bde64;
1774  } un;
1775 
1776 } LOAD_SM_VAR;
1777 
1778 /* Structure for MB Command READ_NVPARM (02) */
1779 
1780 typedef struct {
1781  uint32_t rsvd1[3]; /* Read as all one's */
1782  uint32_t rsvd2; /* Read as all zero's */
1783  uint32_t portname[2]; /* N_PORT name */
1784  uint32_t nodename[2]; /* NODE name */
1785 
1786 #ifdef __BIG_ENDIAN_BITFIELD
1787  uint32_t pref_DID:24;
1788  uint32_t hardAL_PA:8;
1789 #else /* __LITTLE_ENDIAN_BITFIELD */
1790  uint32_t hardAL_PA:8;
1791  uint32_t pref_DID:24;
1792 #endif
1793 
1794  uint32_t rsvd3[21]; /* Read as all one's */
1795 } READ_NV_VAR;
1796 
1797 /* Structure for MB Command WRITE_NVPARMS (03) */
1798 
1799 typedef struct {
1800  uint32_t rsvd1[3]; /* Must be all one's */
1801  uint32_t rsvd2; /* Must be all zero's */
1802  uint32_t portname[2]; /* N_PORT name */
1803  uint32_t nodename[2]; /* NODE name */
1804 
1805 #ifdef __BIG_ENDIAN_BITFIELD
1806  uint32_t pref_DID:24;
1807  uint32_t hardAL_PA:8;
1808 #else /* __LITTLE_ENDIAN_BITFIELD */
1809  uint32_t hardAL_PA:8;
1810  uint32_t pref_DID:24;
1811 #endif
1812 
1813  uint32_t rsvd3[21]; /* Must be all one's */
1814 } WRITE_NV_VAR;
1815 
1816 /* Structure for MB Command RUN_BIU_DIAG (04) */
1817 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1818 
1819 typedef struct {
1820  uint32_t rsvd1;
1821  union {
1822  struct {
1823  struct ulp_bde xmit_bde;
1824  struct ulp_bde rcv_bde;
1825  } s1;
1826  struct {
1827  struct ulp_bde64 xmit_bde64;
1828  struct ulp_bde64 rcv_bde64;
1829  } s2;
1830  } un;
1831 } BIU_DIAG_VAR;
1832 
1833 /* Structure for MB command READ_EVENT_LOG (0x38) */
1834 struct READ_EVENT_LOG_VAR {
1835  uint32_t word1;
1836 #define lpfc_event_log_SHIFT 29
1837 #define lpfc_event_log_MASK 0x00000001
1838 #define lpfc_event_log_WORD word1
1839 #define USE_MAILBOX_RESPONSE 1
1840  uint32_t offset;
1841  struct ulp_bde64 rcv_bde64;
1842 };
1843 
1844 /* Structure for MB Command INIT_LINK (05) */
1845 
1846 typedef struct {
1847 #ifdef __BIG_ENDIAN_BITFIELD
1848  uint32_t rsvd1:24;
1849  uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1850 #else /* __LITTLE_ENDIAN_BITFIELD */
1851  uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1852  uint32_t rsvd1:24;
1853 #endif
1854 
1855 #ifdef __BIG_ENDIAN_BITFIELD
1856  uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1857  uint8_t rsvd2;
1858  uint16_t link_flags;
1859 #else /* __LITTLE_ENDIAN_BITFIELD */
1860  uint16_t link_flags;
1861  uint8_t rsvd2;
1862  uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1863 #endif
1864 
1865 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1866 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1867 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1868 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1869 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1870 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1871 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1872 
1873 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1874 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1875 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1876 
1877  uint32_t link_speed;
1878 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
1879 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
1880 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
1881 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
1882 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
1883 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
1884 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
1885 
1886 } INIT_LINK_VAR;
1887 
1888 /* Structure for MB Command DOWN_LINK (06) */
1889 
1890 typedef struct {
1891  uint32_t rsvd1;
1892 } DOWN_LINK_VAR;
1893 
1894 /* Structure for MB Command CONFIG_LINK (07) */
1895 
1896 typedef struct {
1897 #ifdef __BIG_ENDIAN_BITFIELD
1898  uint32_t cr:1;
1899  uint32_t ci:1;
1900  uint32_t cr_delay:6;
1901  uint32_t cr_count:8;
1902  uint32_t rsvd1:8;
1903  uint32_t MaxBBC:8;
1904 #else /* __LITTLE_ENDIAN_BITFIELD */
1905  uint32_t MaxBBC:8;
1906  uint32_t rsvd1:8;
1907  uint32_t cr_count:8;
1908  uint32_t cr_delay:6;
1909  uint32_t ci:1;
1910  uint32_t cr:1;
1911 #endif
1912 
1913  uint32_t myId;
1914  uint32_t rsvd2;
1915  uint32_t edtov;
1916  uint32_t arbtov;
1917  uint32_t ratov;
1918  uint32_t rttov;
1919  uint32_t altov;
1920  uint32_t crtov;
1921  uint32_t citov;
1922 #ifdef __BIG_ENDIAN_BITFIELD
1923  uint32_t rrq_enable:1;
1924  uint32_t rrq_immed:1;
1925  uint32_t rsvd4:29;
1926  uint32_t ack0_enable:1;
1927 #else /* __LITTLE_ENDIAN_BITFIELD */
1928  uint32_t ack0_enable:1;
1929  uint32_t rsvd4:29;
1930  uint32_t rrq_immed:1;
1931  uint32_t rrq_enable:1;
1932 #endif
1933 } CONFIG_LINK;
1934 
1935 /* Structure for MB Command PART_SLIM (08)
1936  * will be removed since SLI1 is no longer supported!
1937  */
1938 typedef struct {
1939 #ifdef __BIG_ENDIAN_BITFIELD
1940  uint16_t offCiocb;
1941  uint16_t numCiocb;
1942  uint16_t offRiocb;
1943  uint16_t numRiocb;
1944 #else /* __LITTLE_ENDIAN_BITFIELD */
1945  uint16_t numCiocb;
1946  uint16_t offCiocb;
1947  uint16_t numRiocb;
1948  uint16_t offRiocb;
1949 #endif
1950 } RING_DEF;
1951 
1952 typedef struct {
1953 #ifdef __BIG_ENDIAN_BITFIELD
1954  uint32_t unused1:24;
1955  uint32_t numRing:8;
1956 #else /* __LITTLE_ENDIAN_BITFIELD */
1957  uint32_t numRing:8;
1958  uint32_t unused1:24;
1959 #endif
1960 
1961  RING_DEF ringdef[4];
1962  uint32_t hbainit;
1963 } PART_SLIM_VAR;
1964 
1965 /* Structure for MB Command CONFIG_RING (09) */
1966 
1967 typedef struct {
1968 #ifdef __BIG_ENDIAN_BITFIELD
1969  uint32_t unused2:6;
1970  uint32_t recvSeq:1;
1971  uint32_t recvNotify:1;
1972  uint32_t numMask:8;
1973  uint32_t profile:8;
1974  uint32_t unused1:4;
1975  uint32_t ring:4;
1976 #else /* __LITTLE_ENDIAN_BITFIELD */
1977  uint32_t ring:4;
1978  uint32_t unused1:4;
1979  uint32_t profile:8;
1980  uint32_t numMask:8;
1981  uint32_t recvNotify:1;
1982  uint32_t recvSeq:1;
1983  uint32_t unused2:6;
1984 #endif
1985 
1986 #ifdef __BIG_ENDIAN_BITFIELD
1987  uint16_t maxRespXchg;
1988  uint16_t maxOrigXchg;
1989 #else /* __LITTLE_ENDIAN_BITFIELD */
1990  uint16_t maxOrigXchg;
1991  uint16_t maxRespXchg;
1992 #endif
1993 
1994  RR_REG rrRegs[6];
1995 } CONFIG_RING_VAR;
1996 
1997 /* Structure for MB Command RESET_RING (10) */
1998 
1999 typedef struct {
2000  uint32_t ring_no;
2001 } RESET_RING_VAR;
2002 
2003 /* Structure for MB Command READ_CONFIG (11) */
2004 
2005 typedef struct {
2006 #ifdef __BIG_ENDIAN_BITFIELD
2007  uint32_t cr:1;
2008  uint32_t ci:1;
2009  uint32_t cr_delay:6;
2010  uint32_t cr_count:8;
2011  uint32_t InitBBC:8;
2012  uint32_t MaxBBC:8;
2013 #else /* __LITTLE_ENDIAN_BITFIELD */
2014  uint32_t MaxBBC:8;
2015  uint32_t InitBBC:8;
2016  uint32_t cr_count:8;
2017  uint32_t cr_delay:6;
2018  uint32_t ci:1;
2019  uint32_t cr:1;
2020 #endif
2021 
2022 #ifdef __BIG_ENDIAN_BITFIELD
2023  uint32_t topology:8;
2024  uint32_t myDid:24;
2025 #else /* __LITTLE_ENDIAN_BITFIELD */
2026  uint32_t myDid:24;
2027  uint32_t topology:8;
2028 #endif
2029 
2030  /* Defines for topology (defined previously) */
2031 #ifdef __BIG_ENDIAN_BITFIELD
2032  uint32_t AR:1;
2033  uint32_t IR:1;
2034  uint32_t rsvd1:29;
2035  uint32_t ack0:1;
2036 #else /* __LITTLE_ENDIAN_BITFIELD */
2037  uint32_t ack0:1;
2038  uint32_t rsvd1:29;
2039  uint32_t IR:1;
2040  uint32_t AR:1;
2041 #endif
2042 
2043  uint32_t edtov;
2044  uint32_t arbtov;
2045  uint32_t ratov;
2046  uint32_t rttov;
2047  uint32_t altov;
2048  uint32_t lmt;
2049 #define LMT_RESERVED 0x000 /* Not used */
2050 #define LMT_1Gb 0x004
2051 #define LMT_2Gb 0x008
2052 #define LMT_4Gb 0x040
2053 #define LMT_8Gb 0x080
2054 #define LMT_10Gb 0x100
2055 #define LMT_16Gb 0x200
2056  uint32_t rsvd2;
2057  uint32_t rsvd3;
2058  uint32_t max_xri;
2059  uint32_t max_iocb;
2060  uint32_t max_rpi;
2061  uint32_t avail_xri;
2062  uint32_t avail_iocb;
2063  uint32_t avail_rpi;
2064  uint32_t max_vpi;
2065  uint32_t rsvd4;
2066  uint32_t rsvd5;
2067  uint32_t avail_vpi;
2068 } READ_CONFIG_VAR;
2069 
2070 /* Structure for MB Command READ_RCONFIG (12) */
2071 
2072 typedef struct {
2073 #ifdef __BIG_ENDIAN_BITFIELD
2074  uint32_t rsvd2:7;
2075  uint32_t recvNotify:1;
2076  uint32_t numMask:8;
2077  uint32_t profile:8;
2078  uint32_t rsvd1:4;
2079  uint32_t ring:4;
2080 #else /* __LITTLE_ENDIAN_BITFIELD */
2081  uint32_t ring:4;
2082  uint32_t rsvd1:4;
2083  uint32_t profile:8;
2084  uint32_t numMask:8;
2085  uint32_t recvNotify:1;
2086  uint32_t rsvd2:7;
2087 #endif
2088 
2089 #ifdef __BIG_ENDIAN_BITFIELD
2090  uint16_t maxResp;
2091  uint16_t maxOrig;
2092 #else /* __LITTLE_ENDIAN_BITFIELD */
2093  uint16_t maxOrig;
2094  uint16_t maxResp;
2095 #endif
2096 
2097  RR_REG rrRegs[6];
2098 
2099 #ifdef __BIG_ENDIAN_BITFIELD
2100  uint16_t cmdRingOffset;
2101  uint16_t cmdEntryCnt;
2102  uint16_t rspRingOffset;
2103  uint16_t rspEntryCnt;
2104  uint16_t nextCmdOffset;
2105  uint16_t rsvd3;
2106  uint16_t nextRspOffset;
2107  uint16_t rsvd4;
2108 #else /* __LITTLE_ENDIAN_BITFIELD */
2109  uint16_t cmdEntryCnt;
2110  uint16_t cmdRingOffset;
2111  uint16_t rspEntryCnt;
2112  uint16_t rspRingOffset;
2113  uint16_t rsvd3;
2114  uint16_t nextCmdOffset;
2115  uint16_t rsvd4;
2116  uint16_t nextRspOffset;
2117 #endif
2118 } READ_RCONF_VAR;
2119 
2120 /* Structure for MB Command READ_SPARM (13) */
2121 /* Structure for MB Command READ_SPARM64 (0x8D) */
2122 
2123 typedef struct {
2124  uint32_t rsvd1;
2125  uint32_t rsvd2;
2126  union {
2127  struct ulp_bde sp; /* This BDE points to struct serv_parm
2128  structure */
2129  struct ulp_bde64 sp64;
2130  } un;
2131 #ifdef __BIG_ENDIAN_BITFIELD
2132  uint16_t rsvd3;
2133  uint16_t vpi;
2134 #else /* __LITTLE_ENDIAN_BITFIELD */
2135  uint16_t vpi;
2136  uint16_t rsvd3;
2137 #endif
2138 } READ_SPARM_VAR;
2139 
2140 /* Structure for MB Command READ_STATUS (14) */
2141 
2142 typedef struct {
2143 #ifdef __BIG_ENDIAN_BITFIELD
2144  uint32_t rsvd1:31;
2145  uint32_t clrCounters:1;
2146  uint16_t activeXriCnt;
2147  uint16_t activeRpiCnt;
2148 #else /* __LITTLE_ENDIAN_BITFIELD */
2149  uint32_t clrCounters:1;
2150  uint32_t rsvd1:31;
2151  uint16_t activeRpiCnt;
2152  uint16_t activeXriCnt;
2153 #endif
2154 
2155  uint32_t xmitByteCnt;
2156  uint32_t rcvByteCnt;
2157  uint32_t xmitFrameCnt;
2158  uint32_t rcvFrameCnt;
2159  uint32_t xmitSeqCnt;
2160  uint32_t rcvSeqCnt;
2161  uint32_t totalOrigExchanges;
2162  uint32_t totalRespExchanges;
2163  uint32_t rcvPbsyCnt;
2164  uint32_t rcvFbsyCnt;
2165 } READ_STATUS_VAR;
2166 
2167 /* Structure for MB Command READ_RPI (15) */
2168 /* Structure for MB Command READ_RPI64 (0x8F) */
2169 
2170 typedef struct {
2171 #ifdef __BIG_ENDIAN_BITFIELD
2172  uint16_t nextRpi;
2173  uint16_t reqRpi;
2174  uint32_t rsvd2:8;
2175  uint32_t DID:24;
2176 #else /* __LITTLE_ENDIAN_BITFIELD */
2177  uint16_t reqRpi;
2178  uint16_t nextRpi;
2179  uint32_t DID:24;
2180  uint32_t rsvd2:8;
2181 #endif
2182 
2183  union {
2184  struct ulp_bde sp;
2185  struct ulp_bde64 sp64;
2186  } un;
2187 
2188 } READ_RPI_VAR;
2189 
2190 /* Structure for MB Command READ_XRI (16) */
2191 
2192 typedef struct {
2193 #ifdef __BIG_ENDIAN_BITFIELD
2194  uint16_t nextXri;
2195  uint16_t reqXri;
2196  uint16_t rsvd1;
2197  uint16_t rpi;
2198  uint32_t rsvd2:8;
2199  uint32_t DID:24;
2200  uint32_t rsvd3:8;
2201  uint32_t SID:24;
2202  uint32_t rsvd4;
2203  uint8_t seqId;
2204  uint8_t rsvd5;
2205  uint16_t seqCount;
2206  uint16_t oxId;
2207  uint16_t rxId;
2208  uint32_t rsvd6:30;
2209  uint32_t si:1;
2210  uint32_t exchOrig:1;
2211 #else /* __LITTLE_ENDIAN_BITFIELD */
2212  uint16_t reqXri;
2213  uint16_t nextXri;
2214  uint16_t rpi;
2215  uint16_t rsvd1;
2216  uint32_t DID:24;
2217  uint32_t rsvd2:8;
2218  uint32_t SID:24;
2219  uint32_t rsvd3:8;
2220  uint32_t rsvd4;
2221  uint16_t seqCount;
2222  uint8_t rsvd5;
2223  uint8_t seqId;
2224  uint16_t rxId;
2225  uint16_t oxId;
2226  uint32_t exchOrig:1;
2227  uint32_t si:1;
2228  uint32_t rsvd6:30;
2229 #endif
2230 } READ_XRI_VAR;
2231 
2232 /* Structure for MB Command READ_REV (17) */
2233 
2234 typedef struct {
2235 #ifdef __BIG_ENDIAN_BITFIELD
2236  uint32_t cv:1;
2237  uint32_t rr:1;
2238  uint32_t rsvd2:2;
2239  uint32_t v3req:1;
2240  uint32_t v3rsp:1;
2241  uint32_t rsvd1:25;
2242  uint32_t rv:1;
2243 #else /* __LITTLE_ENDIAN_BITFIELD */
2244  uint32_t rv:1;
2245  uint32_t rsvd1:25;
2246  uint32_t v3rsp:1;
2247  uint32_t v3req:1;
2248  uint32_t rsvd2:2;
2249  uint32_t rr:1;
2250  uint32_t cv:1;
2251 #endif
2252 
2253  uint32_t biuRev;
2254  uint32_t smRev;
2255  union {
2256  uint32_t smFwRev;
2257  struct {
2258 #ifdef __BIG_ENDIAN_BITFIELD
2259  uint8_t ProgType;
2260  uint8_t ProgId;
2261  uint16_t ProgVer:4;
2262  uint16_t ProgRev:4;
2263  uint16_t ProgFixLvl:2;
2264  uint16_t ProgDistType:2;
2265  uint16_t DistCnt:4;
2266 #else /* __LITTLE_ENDIAN_BITFIELD */
2267  uint16_t DistCnt:4;
2268  uint16_t ProgDistType:2;
2269  uint16_t ProgFixLvl:2;
2270  uint16_t ProgRev:4;
2271  uint16_t ProgVer:4;
2272  uint8_t ProgId;
2273  uint8_t ProgType;
2274 #endif
2275 
2276  } b;
2277  } un;
2278  uint32_t endecRev;
2279 #ifdef __BIG_ENDIAN_BITFIELD
2280  uint8_t feaLevelHigh;
2281  uint8_t feaLevelLow;
2282  uint8_t fcphHigh;
2283  uint8_t fcphLow;
2284 #else /* __LITTLE_ENDIAN_BITFIELD */
2285  uint8_t fcphLow;
2286  uint8_t fcphHigh;
2287  uint8_t feaLevelLow;
2288  uint8_t feaLevelHigh;
2289 #endif
2290 
2291  uint32_t postKernRev;
2292  uint32_t opFwRev;
2293  uint8_t opFwName[16];
2294  uint32_t sli1FwRev;
2295  uint8_t sli1FwName[16];
2296  uint32_t sli2FwRev;
2297  uint8_t sli2FwName[16];
2298  uint32_t sli3Feat;
2299  uint32_t RandomData[6];
2300 } READ_REV_VAR;
2301 
2302 /* Structure for MB Command READ_LINK_STAT (18) */
2303 
2304 typedef struct {
2305  uint32_t rsvd1;
2306  uint32_t linkFailureCnt;
2307  uint32_t lossSyncCnt;
2308 
2309  uint32_t lossSignalCnt;
2310  uint32_t primSeqErrCnt;
2311  uint32_t invalidXmitWord;
2312  uint32_t crcCnt;
2313  uint32_t primSeqTimeout;
2314  uint32_t elasticOverrun;
2315  uint32_t arbTimeout;
2316 } READ_LNK_VAR;
2317 
2318 /* Structure for MB Command REG_LOGIN (19) */
2319 /* Structure for MB Command REG_LOGIN64 (0x93) */
2320 
2321 typedef struct {
2322 #ifdef __BIG_ENDIAN_BITFIELD
2323  uint16_t rsvd1;
2324  uint16_t rpi;
2325  uint32_t rsvd2:8;
2326  uint32_t did:24;
2327 #else /* __LITTLE_ENDIAN_BITFIELD */
2328  uint16_t rpi;
2329  uint16_t rsvd1;
2330  uint32_t did:24;
2331  uint32_t rsvd2:8;
2332 #endif
2333 
2334  union {
2335  struct ulp_bde sp;
2336  struct ulp_bde64 sp64;
2337  } un;
2338 
2339 #ifdef __BIG_ENDIAN_BITFIELD
2340  uint16_t rsvd6;
2341  uint16_t vpi;
2342 #else /* __LITTLE_ENDIAN_BITFIELD */
2343  uint16_t vpi;
2344  uint16_t rsvd6;
2345 #endif
2346 
2347 } REG_LOGIN_VAR;
2348 
2349 /* Word 30 contents for REG_LOGIN */
2350 typedef union {
2351  struct {
2352 #ifdef __BIG_ENDIAN_BITFIELD
2353  uint16_t rsvd1:12;
2354  uint16_t wd30_class:4;
2355  uint16_t xri;
2356 #else /* __LITTLE_ENDIAN_BITFIELD */
2357  uint16_t xri;
2358  uint16_t wd30_class:4;
2359  uint16_t rsvd1:12;
2360 #endif
2361  } f;
2362  uint32_t word;
2363 } REG_WD30;
2364 
2365 /* Structure for MB Command UNREG_LOGIN (20) */
2366 
2367 typedef struct {
2368 #ifdef __BIG_ENDIAN_BITFIELD
2369  uint16_t rsvd1;
2370  uint16_t rpi;
2371  uint32_t rsvd2;
2372  uint32_t rsvd3;
2373  uint32_t rsvd4;
2374  uint32_t rsvd5;
2375  uint16_t rsvd6;
2376  uint16_t vpi;
2377 #else /* __LITTLE_ENDIAN_BITFIELD */
2378  uint16_t rpi;
2379  uint16_t rsvd1;
2380  uint32_t rsvd2;
2381  uint32_t rsvd3;
2382  uint32_t rsvd4;
2383  uint32_t rsvd5;
2384  uint16_t vpi;
2385  uint16_t rsvd6;
2386 #endif
2387 } UNREG_LOGIN_VAR;
2388 
2389 /* Structure for MB Command REG_VPI (0x96) */
2390 typedef struct {
2391 #ifdef __BIG_ENDIAN_BITFIELD
2392  uint32_t rsvd1;
2393  uint32_t rsvd2:7;
2394  uint32_t upd:1;
2395  uint32_t sid:24;
2396  uint32_t wwn[2];
2397  uint32_t rsvd5;
2398  uint16_t vfi;
2399  uint16_t vpi;
2400 #else /* __LITTLE_ENDIAN */
2401  uint32_t rsvd1;
2402  uint32_t sid:24;
2403  uint32_t upd:1;
2404  uint32_t rsvd2:7;
2405  uint32_t wwn[2];
2406  uint32_t rsvd5;
2407  uint16_t vpi;
2408  uint16_t vfi;
2409 #endif
2410 } REG_VPI_VAR;
2411 
2412 /* Structure for MB Command UNREG_VPI (0x97) */
2413 typedef struct {
2414  uint32_t rsvd1;
2415 #ifdef __BIG_ENDIAN_BITFIELD
2416  uint16_t rsvd2;
2417  uint16_t sli4_vpi;
2418 #else /* __LITTLE_ENDIAN */
2419  uint16_t sli4_vpi;
2420  uint16_t rsvd2;
2421 #endif
2422  uint32_t rsvd3;
2423  uint32_t rsvd4;
2424  uint32_t rsvd5;
2425 #ifdef __BIG_ENDIAN_BITFIELD
2426  uint16_t rsvd6;
2427  uint16_t vpi;
2428 #else /* __LITTLE_ENDIAN */
2429  uint16_t vpi;
2430  uint16_t rsvd6;
2431 #endif
2432 } UNREG_VPI_VAR;
2433 
2434 /* Structure for MB Command UNREG_D_ID (0x23) */
2435 
2436 typedef struct {
2437  uint32_t did;
2438  uint32_t rsvd2;
2439  uint32_t rsvd3;
2440  uint32_t rsvd4;
2441  uint32_t rsvd5;
2442 #ifdef __BIG_ENDIAN_BITFIELD
2443  uint16_t rsvd6;
2444  uint16_t vpi;
2445 #else
2446  uint16_t vpi;
2447  uint16_t rsvd6;
2448 #endif
2449 } UNREG_D_ID_VAR;
2450 
2451 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2452 struct lpfc_mbx_read_top {
2453  uint32_t eventTag; /* Event tag */
2454  uint32_t word2;
2455 #define lpfc_mbx_read_top_fa_SHIFT 12
2456 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2457 #define lpfc_mbx_read_top_fa_WORD word2
2458 #define lpfc_mbx_read_top_mm_SHIFT 11
2459 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2460 #define lpfc_mbx_read_top_mm_WORD word2
2461 #define lpfc_mbx_read_top_pb_SHIFT 9
2462 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2463 #define lpfc_mbx_read_top_pb_WORD word2
2464 #define lpfc_mbx_read_top_il_SHIFT 8
2465 #define lpfc_mbx_read_top_il_MASK 0x00000001
2466 #define lpfc_mbx_read_top_il_WORD word2
2467 #define lpfc_mbx_read_top_att_type_SHIFT 0
2468 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2469 #define lpfc_mbx_read_top_att_type_WORD word2
2470 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2471 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2472 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2473  uint32_t word3;
2474 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2475 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2476 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2477 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2478 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2479 #define lpfc_mbx_read_top_lip_alps_WORD word3
2480 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2481 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2482 #define lpfc_mbx_read_top_lip_type_WORD word3
2483 #define lpfc_mbx_read_top_topology_SHIFT 0
2484 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2485 #define lpfc_mbx_read_top_topology_WORD word3
2486 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2487 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2488 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2489  /* store the LILP AL_PA position map into */
2490  struct ulp_bde64 lilpBde64;
2491 #define LPFC_ALPA_MAP_SIZE 128
2492  uint32_t word7;
2493 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2494 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2495 #define lpfc_mbx_read_top_ld_lu_WORD word7
2496 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2497 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2498 #define lpfc_mbx_read_top_ld_tf_WORD word7
2499 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2500 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2501 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2502 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2503 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2504 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2505 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2506 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2507 #define lpfc_mbx_read_top_ld_tx_WORD word7
2508 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2509 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2510 #define lpfc_mbx_read_top_ld_rx_WORD word7
2511  uint32_t word8;
2512 #define lpfc_mbx_read_top_lu_SHIFT 31
2513 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2514 #define lpfc_mbx_read_top_lu_WORD word8
2515 #define lpfc_mbx_read_top_tf_SHIFT 30
2516 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2517 #define lpfc_mbx_read_top_tf_WORD word8
2518 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2519 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2520 #define lpfc_mbx_read_top_link_spd_WORD word8
2521 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2522 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2523 #define lpfc_mbx_read_top_nl_port_WORD word8
2524 #define lpfc_mbx_read_top_tx_SHIFT 2
2525 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2526 #define lpfc_mbx_read_top_tx_WORD word8
2527 #define lpfc_mbx_read_top_rx_SHIFT 0
2528 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2529 #define lpfc_mbx_read_top_rx_WORD word8
2530 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2531 #define LPFC_LINK_SPEED_1GHZ 0x04
2532 #define LPFC_LINK_SPEED_2GHZ 0x08
2533 #define LPFC_LINK_SPEED_4GHZ 0x10
2534 #define LPFC_LINK_SPEED_8GHZ 0x20
2535 #define LPFC_LINK_SPEED_10GHZ 0x40
2536 #define LPFC_LINK_SPEED_16GHZ 0x80
2537 };
2538 
2539 /* Structure for MB Command CLEAR_LA (22) */
2540 
2541 typedef struct {
2542  uint32_t eventTag; /* Event tag */
2543  uint32_t rsvd1;
2544 } CLEAR_LA_VAR;
2545 
2546 /* Structure for MB Command DUMP */
2547 
2548 typedef struct {
2549 #ifdef __BIG_ENDIAN_BITFIELD
2550  uint32_t rsvd:25;
2551  uint32_t ra:1;
2552  uint32_t co:1;
2553  uint32_t cv:1;
2554  uint32_t type:4;
2555  uint32_t entry_index:16;
2556  uint32_t region_id:16;
2557 #else /* __LITTLE_ENDIAN_BITFIELD */
2558  uint32_t type:4;
2559  uint32_t cv:1;
2560  uint32_t co:1;
2561  uint32_t ra:1;
2562  uint32_t rsvd:25;
2563  uint32_t region_id:16;
2564  uint32_t entry_index:16;
2565 #endif
2566 
2567  uint32_t sli4_length;
2568  uint32_t word_cnt;
2569  uint32_t resp_offset;
2570 } DUMP_VAR;
2571 
2572 #define DMP_MEM_REG 0x1
2573 #define DMP_NV_PARAMS 0x2
2574 #define DMP_LMSD 0x3 /* Link Module Serial Data */
2575 #define DMP_WELL_KNOWN 0x4
2576 
2577 #define DMP_REGION_VPD 0xe
2578 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2579 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2580 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2581 
2582 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2583 #define DMP_VPORT_REGION_SIZE 0x200
2584 #define DMP_MBOX_OFFSET_WORD 0x5
2585 
2586 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2587 #define DMP_RGN23_SIZE 0x400
2588 
2589 #define WAKE_UP_PARMS_REGION_ID 4
2590 #define WAKE_UP_PARMS_WORD_SIZE 15
2591 
2592 struct vport_rec {
2593  uint8_t wwpn[8];
2594  uint8_t wwnn[8];
2595 };
2596 
2597 #define VPORT_INFO_SIG 0x32324752
2598 #define VPORT_INFO_REV_MASK 0xff
2599 #define VPORT_INFO_REV 0x1
2600 #define MAX_STATIC_VPORT_COUNT 16
2601 struct static_vport_info {
2602  uint32_t signature;
2603  uint32_t rev;
2604  struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2605  uint32_t resvd[66];
2606 };
2607 
2608 /* Option rom version structure */
2609 struct prog_id {
2610 #ifdef __BIG_ENDIAN_BITFIELD
2611  uint8_t type;
2612  uint8_t id;
2613  uint32_t ver:4; /* Major Version */
2614  uint32_t rev:4; /* Revision */
2615  uint32_t lev:2; /* Level */
2616  uint32_t dist:2; /* Dist Type */
2617  uint32_t num:4; /* number after dist type */
2618 #else /* __LITTLE_ENDIAN_BITFIELD */
2619  uint32_t num:4; /* number after dist type */
2620  uint32_t dist:2; /* Dist Type */
2621  uint32_t lev:2; /* Level */
2622  uint32_t rev:4; /* Revision */
2623  uint32_t ver:4; /* Major Version */
2624  uint8_t id;
2625  uint8_t type;
2626 #endif
2627 };
2628 
2629 /* Structure for MB Command UPDATE_CFG (0x1B) */
2630 
2631 struct update_cfg_var {
2632 #ifdef __BIG_ENDIAN_BITFIELD
2633  uint32_t rsvd2:16;
2634  uint32_t type:8;
2635  uint32_t rsvd:1;
2636  uint32_t ra:1;
2637  uint32_t co:1;
2638  uint32_t cv:1;
2639  uint32_t req:4;
2640  uint32_t entry_length:16;
2641  uint32_t region_id:16;
2642 #else /* __LITTLE_ENDIAN_BITFIELD */
2643  uint32_t req:4;
2644  uint32_t cv:1;
2645  uint32_t co:1;
2646  uint32_t ra:1;
2647  uint32_t rsvd:1;
2648  uint32_t type:8;
2649  uint32_t rsvd2:16;
2650  uint32_t region_id:16;
2651  uint32_t entry_length:16;
2652 #endif
2653 
2654  uint32_t resp_info;
2655  uint32_t byte_cnt;
2656  uint32_t data_offset;
2657 };
2658 
2659 struct hbq_mask {
2660 #ifdef __BIG_ENDIAN_BITFIELD
2661  uint8_t tmatch;
2662  uint8_t tmask;
2663  uint8_t rctlmatch;
2664  uint8_t rctlmask;
2665 #else /* __LITTLE_ENDIAN */
2666  uint8_t rctlmask;
2667  uint8_t rctlmatch;
2668  uint8_t tmask;
2669  uint8_t tmatch;
2670 #endif
2671 };
2672 
2673 
2674 /* Structure for MB Command CONFIG_HBQ (7c) */
2675 
2676 struct config_hbq_var {
2677 #ifdef __BIG_ENDIAN_BITFIELD
2678  uint32_t rsvd1 :7;
2679  uint32_t recvNotify :1; /* Receive Notification */
2680  uint32_t numMask :8; /* # Mask Entries */
2681  uint32_t profile :8; /* Selection Profile */
2682  uint32_t rsvd2 :8;
2683 #else /* __LITTLE_ENDIAN */
2684  uint32_t rsvd2 :8;
2685  uint32_t profile :8; /* Selection Profile */
2686  uint32_t numMask :8; /* # Mask Entries */
2687  uint32_t recvNotify :1; /* Receive Notification */
2688  uint32_t rsvd1 :7;
2689 #endif
2690 
2691 #ifdef __BIG_ENDIAN_BITFIELD
2692  uint32_t hbqId :16;
2693  uint32_t rsvd3 :12;
2694  uint32_t ringMask :4;
2695 #else /* __LITTLE_ENDIAN */
2696  uint32_t ringMask :4;
2697  uint32_t rsvd3 :12;
2698  uint32_t hbqId :16;
2699 #endif
2700 
2701 #ifdef __BIG_ENDIAN_BITFIELD
2702  uint32_t entry_count :16;
2703  uint32_t rsvd4 :8;
2704  uint32_t headerLen :8;
2705 #else /* __LITTLE_ENDIAN */
2706  uint32_t headerLen :8;
2707  uint32_t rsvd4 :8;
2708  uint32_t entry_count :16;
2709 #endif
2710 
2711  uint32_t hbqaddrLow;
2712  uint32_t hbqaddrHigh;
2713 
2714 #ifdef __BIG_ENDIAN_BITFIELD
2715  uint32_t rsvd5 :31;
2716  uint32_t logEntry :1;
2717 #else /* __LITTLE_ENDIAN */
2718  uint32_t logEntry :1;
2719  uint32_t rsvd5 :31;
2720 #endif
2721 
2722  uint32_t rsvd6; /* w7 */
2723  uint32_t rsvd7; /* w8 */
2724  uint32_t rsvd8; /* w9 */
2725 
2726  struct hbq_mask hbqMasks[6];
2727 
2728 
2729  union {
2730  uint32_t allprofiles[12];
2731 
2732  struct {
2733  #ifdef __BIG_ENDIAN_BITFIELD
2734  uint32_t seqlenoff :16;
2735  uint32_t maxlen :16;
2736  #else /* __LITTLE_ENDIAN */
2737  uint32_t maxlen :16;
2738  uint32_t seqlenoff :16;
2739  #endif
2740  #ifdef __BIG_ENDIAN_BITFIELD
2741  uint32_t rsvd1 :28;
2742  uint32_t seqlenbcnt :4;
2743  #else /* __LITTLE_ENDIAN */
2744  uint32_t seqlenbcnt :4;
2745  uint32_t rsvd1 :28;
2746  #endif
2747  uint32_t rsvd[10];
2748  } profile2;
2749 
2750  struct {
2751  #ifdef __BIG_ENDIAN_BITFIELD
2752  uint32_t seqlenoff :16;
2753  uint32_t maxlen :16;
2754  #else /* __LITTLE_ENDIAN */
2755  uint32_t maxlen :16;
2756  uint32_t seqlenoff :16;
2757  #endif
2758  #ifdef __BIG_ENDIAN_BITFIELD
2759  uint32_t cmdcodeoff :28;
2760  uint32_t rsvd1 :12;
2761  uint32_t seqlenbcnt :4;
2762  #else /* __LITTLE_ENDIAN */
2763  uint32_t seqlenbcnt :4;
2764  uint32_t rsvd1 :12;
2765  uint32_t cmdcodeoff :28;
2766  #endif
2767  uint32_t cmdmatch[8];
2768 
2769  uint32_t rsvd[2];
2770  } profile3;
2771 
2772  struct {
2773  #ifdef __BIG_ENDIAN_BITFIELD
2774  uint32_t seqlenoff :16;
2775  uint32_t maxlen :16;
2776  #else /* __LITTLE_ENDIAN */
2777  uint32_t maxlen :16;
2778  uint32_t seqlenoff :16;
2779  #endif
2780  #ifdef __BIG_ENDIAN_BITFIELD
2781  uint32_t cmdcodeoff :28;
2782  uint32_t rsvd1 :12;
2783  uint32_t seqlenbcnt :4;
2784  #else /* __LITTLE_ENDIAN */
2785  uint32_t seqlenbcnt :4;
2786  uint32_t rsvd1 :12;
2787  uint32_t cmdcodeoff :28;
2788  #endif
2789  uint32_t cmdmatch[8];
2790 
2791  uint32_t rsvd[2];
2792  } profile5;
2793 
2794  } profiles;
2795 
2796 };
2797 
2798 
2799 
2800 /* Structure for MB Command CONFIG_PORT (0x88) */
2801 typedef struct {
2802 #ifdef __BIG_ENDIAN_BITFIELD
2803  uint32_t cBE : 1;
2804  uint32_t cET : 1;
2805  uint32_t cHpcb : 1;
2806  uint32_t cMA : 1;
2807  uint32_t sli_mode : 4;
2808  uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2809  * config block */
2810 #else /* __LITTLE_ENDIAN */
2811  uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2812  * config block */
2813  uint32_t sli_mode : 4;
2814  uint32_t cMA : 1;
2815  uint32_t cHpcb : 1;
2816  uint32_t cET : 1;
2817  uint32_t cBE : 1;
2818 #endif
2819 
2820  uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2821  uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2822  uint32_t hbainit[5];
2823 #ifdef __BIG_ENDIAN_BITFIELD
2824  uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2825  uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2826 #else /* __LITTLE_ENDIAN */
2827  uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2828  uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2829 #endif
2830 
2831 #ifdef __BIG_ENDIAN_BITFIELD
2832  uint32_t rsvd1 : 19; /* Reserved */
2833  uint32_t cdss : 1; /* Configure Data Security SLI */
2834  uint32_t casabt : 1; /* Configure async abts status notice */
2835  uint32_t rsvd2 : 2; /* Reserved */
2836  uint32_t cbg : 1; /* Configure BlockGuard */
2837  uint32_t cmv : 1; /* Configure Max VPIs */
2838  uint32_t ccrp : 1; /* Config Command Ring Polling */
2839  uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2840  uint32_t chbs : 1; /* Cofigure Host Backing store */
2841  uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2842  uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2843  uint32_t cmx : 1; /* Configure Max XRIs */
2844  uint32_t cmr : 1; /* Configure Max RPIs */
2845 #else /* __LITTLE_ENDIAN */
2846  uint32_t cmr : 1; /* Configure Max RPIs */
2847  uint32_t cmx : 1; /* Configure Max XRIs */
2848  uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2849  uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2850  uint32_t chbs : 1; /* Cofigure Host Backing store */
2851  uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2852  uint32_t ccrp : 1; /* Config Command Ring Polling */
2853  uint32_t cmv : 1; /* Configure Max VPIs */
2854  uint32_t cbg : 1; /* Configure BlockGuard */
2855  uint32_t rsvd2 : 2; /* Reserved */
2856  uint32_t casabt : 1; /* Configure async abts status notice */
2857  uint32_t cdss : 1; /* Configure Data Security SLI */
2858  uint32_t rsvd1 : 19; /* Reserved */
2859 #endif
2860 #ifdef __BIG_ENDIAN_BITFIELD
2861  uint32_t rsvd3 : 19; /* Reserved */
2862  uint32_t gdss : 1; /* Configure Data Security SLI */
2863  uint32_t gasabt : 1; /* Grant async abts status notice */
2864  uint32_t rsvd4 : 2; /* Reserved */
2865  uint32_t gbg : 1; /* Grant BlockGuard */
2866  uint32_t gmv : 1; /* Grant Max VPIs */
2867  uint32_t gcrp : 1; /* Grant Command Ring Polling */
2868  uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2869  uint32_t ghbs : 1; /* Grant Host Backing Store */
2870  uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2871  uint32_t gerbm : 1; /* Grant ERBM Request */
2872  uint32_t gmx : 1; /* Grant Max XRIs */
2873  uint32_t gmr : 1; /* Grant Max RPIs */
2874 #else /* __LITTLE_ENDIAN */
2875  uint32_t gmr : 1; /* Grant Max RPIs */
2876  uint32_t gmx : 1; /* Grant Max XRIs */
2877  uint32_t gerbm : 1; /* Grant ERBM Request */
2878  uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2879  uint32_t ghbs : 1; /* Grant Host Backing Store */
2880  uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2881  uint32_t gcrp : 1; /* Grant Command Ring Polling */
2882  uint32_t gmv : 1; /* Grant Max VPIs */
2883  uint32_t gbg : 1; /* Grant BlockGuard */
2884  uint32_t rsvd4 : 2; /* Reserved */
2885  uint32_t gasabt : 1; /* Grant async abts status notice */
2886  uint32_t gdss : 1; /* Configure Data Security SLI */
2887  uint32_t rsvd3 : 19; /* Reserved */
2888 #endif
2889 
2890 #ifdef __BIG_ENDIAN_BITFIELD
2891  uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2892  uint32_t max_xri : 16; /* Max XRIs Port should configure */
2893 #else /* __LITTLE_ENDIAN */
2894  uint32_t max_xri : 16; /* Max XRIs Port should configure */
2895  uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2896 #endif
2897 
2898 #ifdef __BIG_ENDIAN_BITFIELD
2899  uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2900  uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2901 #else /* __LITTLE_ENDIAN */
2902  uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
2903  uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2904 #endif
2905 
2906  uint32_t rsvd6; /* Reserved */
2907 
2908 #ifdef __BIG_ENDIAN_BITFIELD
2909  uint32_t fips_rev : 3; /* FIPS Spec Revision */
2910  uint32_t fips_level : 4; /* FIPS Level */
2911  uint32_t sec_err : 9; /* security crypto error */
2912  uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2913 #else /* __LITTLE_ENDIAN */
2914  uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2915  uint32_t sec_err : 9; /* security crypto error */
2916  uint32_t fips_level : 4; /* FIPS Level */
2917  uint32_t fips_rev : 3; /* FIPS Spec Revision */
2918 #endif
2919 
2920 } CONFIG_PORT_VAR;
2921 
2922 /* Structure for MB Command CONFIG_MSI (0x30) */
2923 struct config_msi_var {
2924 #ifdef __BIG_ENDIAN_BITFIELD
2925  uint32_t dfltMsgNum:8; /* Default message number */
2926  uint32_t rsvd1:11; /* Reserved */
2927  uint32_t NID:5; /* Number of secondary attention IDs */
2928  uint32_t rsvd2:5; /* Reserved */
2929  uint32_t dfltPresent:1; /* Default message number present */
2930  uint32_t addFlag:1; /* Add association flag */
2931  uint32_t reportFlag:1; /* Report association flag */
2932 #else /* __LITTLE_ENDIAN_BITFIELD */
2933  uint32_t reportFlag:1; /* Report association flag */
2934  uint32_t addFlag:1; /* Add association flag */
2935  uint32_t dfltPresent:1; /* Default message number present */
2936  uint32_t rsvd2:5; /* Reserved */
2937  uint32_t NID:5; /* Number of secondary attention IDs */
2938  uint32_t rsvd1:11; /* Reserved */
2939  uint32_t dfltMsgNum:8; /* Default message number */
2940 #endif
2941  uint32_t attentionConditions[2];
2942  uint8_t attentionId[16];
2943  uint8_t messageNumberByHA[64];
2944  uint8_t messageNumberByID[16];
2945  uint32_t autoClearHA[2];
2946 #ifdef __BIG_ENDIAN_BITFIELD
2947  uint32_t rsvd3:16;
2948  uint32_t autoClearID:16;
2949 #else /* __LITTLE_ENDIAN_BITFIELD */
2950  uint32_t autoClearID:16;
2951  uint32_t rsvd3:16;
2952 #endif
2953  uint32_t rsvd4;
2954 };
2955 
2956 /* SLI-2 Port Control Block */
2957 
2958 /* SLIM POINTER */
2959 #define SLIMOFF 0x30 /* WORD */
2960 
2961 typedef struct _SLI2_RDSC {
2962  uint32_t cmdEntries;
2963  uint32_t cmdAddrLow;
2964  uint32_t cmdAddrHigh;
2965 
2966  uint32_t rspEntries;
2967  uint32_t rspAddrLow;
2968  uint32_t rspAddrHigh;
2969 } SLI2_RDSC;
2970 
2971 typedef struct _PCB {
2972 #ifdef __BIG_ENDIAN_BITFIELD
2973  uint32_t type:8;
2974 #define TYPE_NATIVE_SLI2 0x01
2975  uint32_t feature:8;
2976 #define FEATURE_INITIAL_SLI2 0x01
2977  uint32_t rsvd:12;
2978  uint32_t maxRing:4;
2979 #else /* __LITTLE_ENDIAN_BITFIELD */
2980  uint32_t maxRing:4;
2981  uint32_t rsvd:12;
2982  uint32_t feature:8;
2983 #define FEATURE_INITIAL_SLI2 0x01
2984  uint32_t type:8;
2985 #define TYPE_NATIVE_SLI2 0x01
2986 #endif
2987 
2988  uint32_t mailBoxSize;
2989  uint32_t mbAddrLow;
2990  uint32_t mbAddrHigh;
2991 
2992  uint32_t hgpAddrLow;
2993  uint32_t hgpAddrHigh;
2994 
2995  uint32_t pgpAddrLow;
2996  uint32_t pgpAddrHigh;
2997  SLI2_RDSC rdsc[MAX_SLI3_RINGS];
2998 } PCB_t;
2999 
3000 /* NEW_FEATURE */
3001 typedef struct {
3002 #ifdef __BIG_ENDIAN_BITFIELD
3003  uint32_t rsvd0:27;
3004  uint32_t discardFarp:1;
3005  uint32_t IPEnable:1;
3006  uint32_t nodeName:1;
3007  uint32_t portName:1;
3008  uint32_t filterEnable:1;
3009 #else /* __LITTLE_ENDIAN_BITFIELD */
3010  uint32_t filterEnable:1;
3011  uint32_t portName:1;
3012  uint32_t nodeName:1;
3013  uint32_t IPEnable:1;
3014  uint32_t discardFarp:1;
3015  uint32_t rsvd:27;
3016 #endif
3017 
3018  uint8_t portname[8]; /* Used to be struct lpfc_name */
3019  uint8_t nodename[8];
3020  uint32_t rsvd1;
3021  uint32_t rsvd2;
3022  uint32_t rsvd3;
3023  uint32_t IPAddress;
3024 } CONFIG_FARP_VAR;
3025 
3026 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3027 
3028 typedef struct {
3029 #ifdef __BIG_ENDIAN_BITFIELD
3030  uint32_t rsvd:30;
3031  uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3032 #else /* __LITTLE_ENDIAN */
3033  uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3034  uint32_t rsvd:30;
3035 #endif
3036 } ASYNCEVT_ENABLE_VAR;
3037 
3038 /* Union of all Mailbox Command types */
3039 #define MAILBOX_CMD_WSIZE 32
3040 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3041 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3042 #define MAILBOX_EXT_WSIZE 512
3043 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3044 #define MAILBOX_HBA_EXT_OFFSET 0x100
3045 /* max mbox xmit size is a page size for sysfs IO operations */
3046 #define MAILBOX_SYSFS_MAX 4096
3047 
3048 typedef union {
3049  uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3050  * feature/max ring number
3051  */
3052  LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3053  READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3054  WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3055  BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3056  INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3057  DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3058  CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3059  PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3060  CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3061  RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3062  READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3063  READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3064  READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3065  READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3066  READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3067  READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3068  READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3069  READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3070  REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3071  UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3072  CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3073  DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3074  UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3075  CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3076  * NEW_FEATURE
3077  */
3078  struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3079  struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3080  CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3081  struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3082  REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3083  UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3084  ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3085  struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3086  * (READ_EVENT_LOG)
3087  */
3088  struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3089 } MAILVARIANTS;
3090 
3091 /*
3092  * SLI-2 specific structures
3093  */
3094 
3095 struct lpfc_hgp {
3096  __le32 cmdPutInx;
3097  __le32 rspGetInx;
3098 };
3099 
3100 struct lpfc_pgp {
3101  __le32 cmdGetInx;
3102  __le32 rspPutInx;
3103 };
3104 
3105 struct sli2_desc {
3106  uint32_t unused1[16];
3107  struct lpfc_hgp host[MAX_SLI3_RINGS];
3108  struct lpfc_pgp port[MAX_SLI3_RINGS];
3109 };
3110 
3111 struct sli3_desc {
3112  struct lpfc_hgp host[MAX_SLI3_RINGS];
3113  uint32_t reserved[8];
3114  uint32_t hbq_put[16];
3115 };
3116 
3117 struct sli3_pgp {
3118  struct lpfc_pgp port[MAX_SLI3_RINGS];
3119  uint32_t hbq_get[16];
3120 };
3121 
3122 union sli_var {
3123  struct sli2_desc s2;
3124  struct sli3_desc s3;
3125  struct sli3_pgp s3_pgp;
3126 };
3127 
3128 typedef struct {
3129 #ifdef __BIG_ENDIAN_BITFIELD
3130  uint16_t mbxStatus;
3131  uint8_t mbxCommand;
3132  uint8_t mbxReserved:6;
3133  uint8_t mbxHc:1;
3134  uint8_t mbxOwner:1; /* Low order bit first word */
3135 #else /* __LITTLE_ENDIAN_BITFIELD */
3136  uint8_t mbxOwner:1; /* Low order bit first word */
3137  uint8_t mbxHc:1;
3138  uint8_t mbxReserved:6;
3139  uint8_t mbxCommand;
3140  uint16_t mbxStatus;
3141 #endif
3142 
3143  MAILVARIANTS un;
3144  union sli_var us;
3145 } MAILBOX_t;
3146 
3147 /*
3148  * Begin Structure Definitions for IOCB Commands
3149  */
3150 
3151 typedef struct {
3152 #ifdef __BIG_ENDIAN_BITFIELD
3153  uint8_t statAction;
3154  uint8_t statRsn;
3155  uint8_t statBaExp;
3156  uint8_t statLocalError;
3157 #else /* __LITTLE_ENDIAN_BITFIELD */
3158  uint8_t statLocalError;
3159  uint8_t statBaExp;
3160  uint8_t statRsn;
3161  uint8_t statAction;
3162 #endif
3163  /* statRsn P/F_RJT reason codes */
3164 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3165 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3166 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3167 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3168 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3169 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3170 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3171 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3172 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3173 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3174 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3175 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3176 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3177 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3178 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3179 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3180 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3181 #define RJT_PROT_ERR 0x12 /* Protocol error */
3182 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3183 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3184 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3185 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3186 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3187 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3188 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3189 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3190 
3191 #define IOERR_SUCCESS 0x00 /* statLocalError */
3192 #define IOERR_MISSING_CONTINUE 0x01
3193 #define IOERR_SEQUENCE_TIMEOUT 0x02
3194 #define IOERR_INTERNAL_ERROR 0x03
3195 #define IOERR_INVALID_RPI 0x04
3196 #define IOERR_NO_XRI 0x05
3197 #define IOERR_ILLEGAL_COMMAND 0x06
3198 #define IOERR_XCHG_DROPPED 0x07
3199 #define IOERR_ILLEGAL_FIELD 0x08
3200 #define IOERR_BAD_CONTINUE 0x09
3201 #define IOERR_TOO_MANY_BUFFERS 0x0A
3202 #define IOERR_RCV_BUFFER_WAITING 0x0B
3203 #define IOERR_NO_CONNECTION 0x0C
3204 #define IOERR_TX_DMA_FAILED 0x0D
3205 #define IOERR_RX_DMA_FAILED 0x0E
3206 #define IOERR_ILLEGAL_FRAME 0x0F
3207 #define IOERR_EXTRA_DATA 0x10
3208 #define IOERR_NO_RESOURCES 0x11
3209 #define IOERR_RESERVED 0x12
3210 #define IOERR_ILLEGAL_LENGTH 0x13
3211 #define IOERR_UNSUPPORTED_FEATURE 0x14
3212 #define IOERR_ABORT_IN_PROGRESS 0x15
3213 #define IOERR_ABORT_REQUESTED 0x16
3214 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3215 #define IOERR_LOOP_OPEN_FAILURE 0x18
3216 #define IOERR_RING_RESET 0x19
3217 #define IOERR_LINK_DOWN 0x1A
3218 #define IOERR_CORRUPTED_DATA 0x1B
3219 #define IOERR_CORRUPTED_RPI 0x1C
3220 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3221 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3222 #define IOERR_DUP_FRAME 0x1F
3223 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3224 #define IOERR_BAD_HOST_ADDRESS 0x21
3225 #define IOERR_RCV_HDRBUF_WAITING 0x22
3226 #define IOERR_MISSING_HDR_BUFFER 0x23
3227 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3228 #define IOERR_ABORTMULT_REQUESTED 0x25
3229 #define IOERR_BUFFER_SHORTAGE 0x28
3230 #define IOERR_DEFAULT 0x29
3231 #define IOERR_CNT 0x2A
3232 #define IOERR_SLER_FAILURE 0x46
3233 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3234 #define IOERR_SLER_REC_RJT_ERR 0x48
3235 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3236 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3237 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3238 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3239 #define IOERR_SLER_ABTS_ERR 0x4E
3240 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3241 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3242 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3243 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3244 #define IOERR_DRVR_MASK 0x100
3245 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3246 #define IOERR_SLI_BRESET 0x102
3247 #define IOERR_SLI_ABORTED 0x103
3248 #define IOERR_PARAM_MASK 0x1ff
3249 } PARM_ERR;
3250 
3251 typedef union {
3252  struct {
3253 #ifdef __BIG_ENDIAN_BITFIELD
3254  uint8_t Rctl; /* R_CTL field */
3255  uint8_t Type; /* TYPE field */
3256  uint8_t Dfctl; /* DF_CTL field */
3257  uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3258 #else /* __LITTLE_ENDIAN_BITFIELD */
3259  uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3260  uint8_t Dfctl; /* DF_CTL field */
3261  uint8_t Type; /* TYPE field */
3262  uint8_t Rctl; /* R_CTL field */
3263 #endif
3264 
3265 #define BC 0x02 /* Broadcast Received - Fctl */
3266 #define SI 0x04 /* Sequence Initiative */
3267 #define LA 0x08 /* Ignore Link Attention state */
3268 #define LS 0x80 /* Last Sequence */
3269  } hcsw;
3270  uint32_t reserved;
3271 } WORD5;
3272 
3273 /* IOCB Command template for a generic response */
3274 typedef struct {
3275  uint32_t reserved[4];
3276  PARM_ERR perr;
3277 } GENERIC_RSP;
3278 
3279 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3280 typedef struct {
3281  struct ulp_bde xrsqbde[2];
3282  uint32_t xrsqRo; /* Starting Relative Offset */
3283  WORD5 w5; /* Header control/status word */
3284 } XR_SEQ_FIELDS;
3285 
3286 /* IOCB Command template for ELS_REQUEST */
3287 typedef struct {
3288  struct ulp_bde elsReq;
3289  struct ulp_bde elsRsp;
3290 
3291 #ifdef __BIG_ENDIAN_BITFIELD
3292  uint32_t word4Rsvd:7;
3293  uint32_t fl:1;
3294  uint32_t myID:24;
3295  uint32_t word5Rsvd:8;
3296  uint32_t remoteID:24;
3297 #else /* __LITTLE_ENDIAN_BITFIELD */
3298  uint32_t myID:24;
3299  uint32_t fl:1;
3300  uint32_t word4Rsvd:7;
3301  uint32_t remoteID:24;
3302  uint32_t word5Rsvd:8;
3303 #endif
3304 } ELS_REQUEST;
3305 
3306 /* IOCB Command template for RCV_ELS_REQ */
3307 typedef struct {
3308  struct ulp_bde elsReq[2];
3309  uint32_t parmRo;
3310 
3311 #ifdef __BIG_ENDIAN_BITFIELD
3312  uint32_t word5Rsvd:8;
3313  uint32_t remoteID:24;
3314 #else /* __LITTLE_ENDIAN_BITFIELD */
3315  uint32_t remoteID:24;
3316  uint32_t word5Rsvd:8;
3317 #endif
3318 } RCV_ELS_REQ;
3319 
3320 /* IOCB Command template for ABORT / CLOSE_XRI */
3321 typedef struct {
3322  uint32_t rsvd[3];
3323  uint32_t abortType;
3324 #define ABORT_TYPE_ABTX 0x00000000
3325 #define ABORT_TYPE_ABTS 0x00000001
3326  uint32_t parm;
3327 #ifdef __BIG_ENDIAN_BITFIELD
3328  uint16_t abortContextTag; /* ulpContext from command to abort/close */
3329  uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3330 #else /* __LITTLE_ENDIAN_BITFIELD */
3331  uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3332  uint16_t abortContextTag; /* ulpContext from command to abort/close */
3333 #endif
3334 } AC_XRI;
3335 
3336 /* IOCB Command template for ABORT_MXRI64 */
3337 typedef struct {
3338  uint32_t rsvd[3];
3339  uint32_t abortType;
3340  uint32_t parm;
3341  uint32_t iotag32;
3342 } A_MXRI64;
3343 
3344 /* IOCB Command template for GET_RPI */
3345 typedef struct {
3346  uint32_t rsvd[4];
3347  uint32_t parmRo;
3348 #ifdef __BIG_ENDIAN_BITFIELD
3349  uint32_t word5Rsvd:8;
3350  uint32_t remoteID:24;
3351 #else /* __LITTLE_ENDIAN_BITFIELD */
3352  uint32_t remoteID:24;
3353  uint32_t word5Rsvd:8;
3354 #endif
3355 } GET_RPI;
3356 
3357 /* IOCB Command template for all FCP Initiator commands */
3358 typedef struct {
3359  struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3360  struct ulp_bde fcpi_rsp; /* Rcv buffer */
3361  uint32_t fcpi_parm;
3362  uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3363 } FCPI_FIELDS;
3364 
3365 /* IOCB Command template for all FCP Target commands */
3366 typedef struct {
3367  struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3368  uint32_t fcpt_Offset;
3369  uint32_t fcpt_Length; /* transfer ready for IWRITE */
3370 } FCPT_FIELDS;
3371 
3372 /* SLI-2 IOCB structure definitions */
3373 
3374 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3375 typedef struct {
3376  ULP_BDL bdl;
3377  uint32_t xrsqRo; /* Starting Relative Offset */
3378  WORD5 w5; /* Header control/status word */
3379 } XMT_SEQ_FIELDS64;
3380 
3381 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3382 #define xmit_els_remoteID xrsqRo
3383 
3384 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3385 typedef struct {
3386  struct ulp_bde64 rcvBde;
3387  uint32_t rsvd1;
3388  uint32_t xrsqRo; /* Starting Relative Offset */
3389  WORD5 w5; /* Header control/status word */
3390 } RCV_SEQ_FIELDS64;
3391 
3392 /* IOCB Command template for ELS_REQUEST64 */
3393 typedef struct {
3394  ULP_BDL bdl;
3395 #ifdef __BIG_ENDIAN_BITFIELD
3396  uint32_t word4Rsvd:7;
3397  uint32_t fl:1;
3398  uint32_t myID:24;
3399  uint32_t word5Rsvd:8;
3400  uint32_t remoteID:24;
3401 #else /* __LITTLE_ENDIAN_BITFIELD */
3402  uint32_t myID:24;
3403  uint32_t fl:1;
3404  uint32_t word4Rsvd:7;
3405  uint32_t remoteID:24;
3406  uint32_t word5Rsvd:8;
3407 #endif
3408 } ELS_REQUEST64;
3409 
3410 /* IOCB Command template for GEN_REQUEST64 */
3411 typedef struct {
3412  ULP_BDL bdl;
3413  uint32_t xrsqRo; /* Starting Relative Offset */
3414  WORD5 w5; /* Header control/status word */
3415 } GEN_REQUEST64;
3416 
3417 /* IOCB Command template for RCV_ELS_REQ64 */
3418 typedef struct {
3419  struct ulp_bde64 elsReq;
3420  uint32_t rcvd1;
3421  uint32_t parmRo;
3422 
3423 #ifdef __BIG_ENDIAN_BITFIELD
3424  uint32_t word5Rsvd:8;
3425  uint32_t remoteID:24;
3426 #else /* __LITTLE_ENDIAN_BITFIELD */
3427  uint32_t remoteID:24;
3428  uint32_t word5Rsvd:8;
3429 #endif
3430 } RCV_ELS_REQ64;
3431 
3432 /* IOCB Command template for RCV_SEQ64 */
3433 struct rcv_seq64 {
3434  struct ulp_bde64 elsReq;
3435  uint32_t hbq_1;
3436  uint32_t parmRo;
3437 #ifdef __BIG_ENDIAN_BITFIELD
3438  uint32_t rctl:8;
3439  uint32_t type:8;
3440  uint32_t dfctl:8;
3441  uint32_t ls:1;
3442  uint32_t fs:1;
3443  uint32_t rsvd2:3;
3444  uint32_t si:1;
3445  uint32_t bc:1;
3446  uint32_t rsvd3:1;
3447 #else /* __LITTLE_ENDIAN_BITFIELD */
3448  uint32_t rsvd3:1;
3449  uint32_t bc:1;
3450  uint32_t si:1;
3451  uint32_t rsvd2:3;
3452  uint32_t fs:1;
3453  uint32_t ls:1;
3454  uint32_t dfctl:8;
3455  uint32_t type:8;
3456  uint32_t rctl:8;
3457 #endif
3458 };
3459 
3460 /* IOCB Command template for all 64 bit FCP Initiator commands */
3461 typedef struct {
3462  ULP_BDL bdl;
3463  uint32_t fcpi_parm;
3464  uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3465 } FCPI_FIELDS64;
3466 
3467 /* IOCB Command template for all 64 bit FCP Target commands */
3468 typedef struct {
3469  ULP_BDL bdl;
3470  uint32_t fcpt_Offset;
3471  uint32_t fcpt_Length; /* transfer ready for IWRITE */
3472 } FCPT_FIELDS64;
3473 
3474 /* IOCB Command template for Async Status iocb commands */
3475 typedef struct {
3476  uint32_t rsvd[4];
3477  uint32_t param;
3478 #ifdef __BIG_ENDIAN_BITFIELD
3479  uint16_t evt_code; /* High order bits word 5 */
3480  uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3481 #else /* __LITTLE_ENDIAN_BITFIELD */
3482  uint16_t sub_ctxt_tag; /* High order bits word 5 */
3483  uint16_t evt_code; /* Low order bits word 5 */
3484 #endif
3485 } ASYNCSTAT_FIELDS;
3486 #define ASYNC_TEMP_WARN 0x100
3487 #define ASYNC_TEMP_SAFE 0x101
3488 #define ASYNC_STATUS_CN 0x102
3489 
3490 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3491  or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3492 
3493 struct rcv_sli3 {
3494 #ifdef __BIG_ENDIAN_BITFIELD
3495  uint16_t ox_id;
3496  uint16_t seq_cnt;
3497 
3498  uint16_t vpi;
3499  uint16_t word9Rsvd;
3500 #else /* __LITTLE_ENDIAN */
3501  uint16_t seq_cnt;
3502  uint16_t ox_id;
3503 
3504  uint16_t word9Rsvd;
3505  uint16_t vpi;
3506 #endif
3507  uint32_t word10Rsvd;
3508  uint32_t acc_len; /* accumulated length */
3509  struct ulp_bde64 bde2;
3510 };
3511 
3512 /* Structure used for a single HBQ entry */
3513 struct lpfc_hbq_entry {
3514  struct ulp_bde64 bde;
3515  uint32_t buffer_tag;
3516 };
3517 
3518 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3519 typedef struct {
3520  struct lpfc_hbq_entry buff;
3521  uint32_t rsvd;
3522  uint32_t rsvd1;
3523 } QUE_XRI64_CX_FIELDS;
3524 
3525 struct que_xri64cx_ext_fields {
3526  uint32_t iotag64_low;
3527  uint32_t iotag64_high;
3528  uint32_t ebde_count;
3529  uint32_t rsvd;
3530  struct lpfc_hbq_entry buff[5];
3531 };
3532 
3533 struct sli3_bg_fields {
3534  uint32_t filler[6]; /* word 8-13 in IOCB */
3535  uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3536 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3537 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3538 #define BGS_BIDIR_BG_PROF_SHIFT 24
3539 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3540 #define BGS_BIDIR_ERR_COND_SHIFT 16
3541 #define BGS_BG_PROFILE_MASK 0x0000ff00
3542 #define BGS_BG_PROFILE_SHIFT 8
3543 #define BGS_INVALID_PROF_MASK 0x00000020
3544 #define BGS_INVALID_PROF_SHIFT 5
3545 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3546 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3547 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3548 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3549 #define BGS_REFTAG_ERR_MASK 0x00000004
3550 #define BGS_REFTAG_ERR_SHIFT 2
3551 #define BGS_APPTAG_ERR_MASK 0x00000002
3552 #define BGS_APPTAG_ERR_SHIFT 1
3553 #define BGS_GUARD_ERR_MASK 0x00000001
3554 #define BGS_GUARD_ERR_SHIFT 0
3555  uint32_t bgstat; /* word 15 - BlockGuard Status */
3556 };
3557 
3558 static inline uint32_t
3559 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3560 {
3561  return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3562  BGS_BIDIR_BG_PROF_SHIFT;
3563 }
3564 
3565 static inline uint32_t
3566 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3567 {
3568  return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3569  BGS_BIDIR_ERR_COND_SHIFT;
3570 }
3571 
3572 static inline uint32_t
3573 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3574 {
3575  return (bgstat & BGS_BG_PROFILE_MASK) >>
3576  BGS_BG_PROFILE_SHIFT;
3577 }
3578 
3579 static inline uint32_t
3580 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3581 {
3582  return (bgstat & BGS_INVALID_PROF_MASK) >>
3583  BGS_INVALID_PROF_SHIFT;
3584 }
3585 
3586 static inline uint32_t
3587 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3588 {
3589  return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3590  BGS_UNINIT_DIF_BLOCK_SHIFT;
3591 }
3592 
3593 static inline uint32_t
3594 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3595 {
3596  return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3597  BGS_HI_WATER_MARK_PRESENT_SHIFT;
3598 }
3599 
3600 static inline uint32_t
3601 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3602 {
3603  return (bgstat & BGS_REFTAG_ERR_MASK) >>
3604  BGS_REFTAG_ERR_SHIFT;
3605 }
3606 
3607 static inline uint32_t
3608 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3609 {
3610  return (bgstat & BGS_APPTAG_ERR_MASK) >>
3611  BGS_APPTAG_ERR_SHIFT;
3612 }
3613 
3614 static inline uint32_t
3615 lpfc_bgs_get_guard_err(uint32_t bgstat)
3616 {
3617  return (bgstat & BGS_GUARD_ERR_MASK) >>
3618  BGS_GUARD_ERR_SHIFT;
3619 }
3620 
3621 #define LPFC_EXT_DATA_BDE_COUNT 3
3622 struct fcp_irw_ext {
3623  uint32_t io_tag64_low;
3624  uint32_t io_tag64_high;
3625 #ifdef __BIG_ENDIAN_BITFIELD
3626  uint8_t reserved1;
3627  uint8_t reserved2;
3628  uint8_t reserved3;
3629  uint8_t ebde_count;
3630 #else /* __LITTLE_ENDIAN */
3631  uint8_t ebde_count;
3632  uint8_t reserved3;
3633  uint8_t reserved2;
3634  uint8_t reserved1;
3635 #endif
3636  uint32_t reserved4;
3637  struct ulp_bde64 rbde; /* response bde */
3638  struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3639  uint8_t icd[32]; /* immediate command data (32 bytes) */
3640 };
3641 
3642 typedef struct _IOCB { /* IOCB structure */
3643  union {
3644  GENERIC_RSP grsp; /* Generic response */
3645  XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3646  struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3647  RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3648  AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3649  A_MXRI64 amxri; /* abort multiple xri command overlay */
3650  GET_RPI getrpi; /* GET_RPI template */
3651  FCPI_FIELDS fcpi; /* FCP Initiator template */
3652  FCPT_FIELDS fcpt; /* FCP target template */
3653 
3654  /* SLI-2 structures */
3655 
3656  struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3657  * bde_64s */
3658  ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3659  GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3660  RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3661  XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3662  FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3663  FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3664  ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3665  QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3666  struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3667  struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3668  uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3669  } un;
3670  union {
3671  struct {
3672 #ifdef __BIG_ENDIAN_BITFIELD
3673  uint16_t ulpContext; /* High order bits word 6 */
3674  uint16_t ulpIoTag; /* Low order bits word 6 */
3675 #else /* __LITTLE_ENDIAN_BITFIELD */
3676  uint16_t ulpIoTag; /* Low order bits word 6 */
3677  uint16_t ulpContext; /* High order bits word 6 */
3678 #endif
3679  } t1;
3680  struct {
3681 #ifdef __BIG_ENDIAN_BITFIELD
3682  uint16_t ulpContext; /* High order bits word 6 */
3683  uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3684  uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3685 #else /* __LITTLE_ENDIAN_BITFIELD */
3686  uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3687  uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3688  uint16_t ulpContext; /* High order bits word 6 */
3689 #endif
3690  } t2;
3691  } un1;
3692 #define ulpContext un1.t1.ulpContext
3693 #define ulpIoTag un1.t1.ulpIoTag
3694 #define ulpIoTag0 un1.t2.ulpIoTag0
3695 
3696 #ifdef __BIG_ENDIAN_BITFIELD
3697  uint32_t ulpTimeout:8;
3698  uint32_t ulpXS:1;
3699  uint32_t ulpFCP2Rcvy:1;
3700  uint32_t ulpPU:2;
3701  uint32_t ulpIr:1;
3702  uint32_t ulpClass:3;
3703  uint32_t ulpCommand:8;
3704  uint32_t ulpStatus:4;
3705  uint32_t ulpBdeCount:2;
3706  uint32_t ulpLe:1;
3707  uint32_t ulpOwner:1; /* Low order bit word 7 */
3708 #else /* __LITTLE_ENDIAN_BITFIELD */
3709  uint32_t ulpOwner:1; /* Low order bit word 7 */
3710  uint32_t ulpLe:1;
3711  uint32_t ulpBdeCount:2;
3712  uint32_t ulpStatus:4;
3713  uint32_t ulpCommand:8;
3714  uint32_t ulpClass:3;
3715  uint32_t ulpIr:1;
3716  uint32_t ulpPU:2;
3717  uint32_t ulpFCP2Rcvy:1;
3718  uint32_t ulpXS:1;
3719  uint32_t ulpTimeout:8;
3720 #endif
3721 
3722  union {
3723  struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3724 
3725  /* words 8-31 used for que_xri_cx iocb */
3726  struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3727  struct fcp_irw_ext fcp_ext;
3728  uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3729 
3730  /* words 8-15 for BlockGuard */
3731  struct sli3_bg_fields sli3_bg;
3732  } unsli3;
3733 
3734 #define ulpCt_h ulpXS
3735 #define ulpCt_l ulpFCP2Rcvy
3736 
3737 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3738 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3739 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3740 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3741 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3742 #define PARM_NPIV_DID 3
3743 #define CLASS1 0 /* Class 1 */
3744 #define CLASS2 1 /* Class 2 */
3745 #define CLASS3 2 /* Class 3 */
3746 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3747 
3748 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3749 #define IOSTAT_FCP_RSP_ERROR 0x1
3750 #define IOSTAT_REMOTE_STOP 0x2
3751 #define IOSTAT_LOCAL_REJECT 0x3
3752 #define IOSTAT_NPORT_RJT 0x4
3753 #define IOSTAT_FABRIC_RJT 0x5
3754 #define IOSTAT_NPORT_BSY 0x6
3755 #define IOSTAT_FABRIC_BSY 0x7
3756 #define IOSTAT_INTERMED_RSP 0x8
3757 #define IOSTAT_LS_RJT 0x9
3758 #define IOSTAT_BA_RJT 0xA
3759 #define IOSTAT_RSVD1 0xB
3760 #define IOSTAT_RSVD2 0xC
3761 #define IOSTAT_RSVD3 0xD
3762 #define IOSTAT_RSVD4 0xE
3763 #define IOSTAT_NEED_BUFFER 0xF
3764 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3765 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3766 #define IOSTAT_CNT 0x11
3767 
3768 } IOCB_t;
3769 
3770 
3771 #define SLI1_SLIM_SIZE (4 * 1024)
3772 
3773 /* Up to 498 IOCBs will fit into 16k
3774  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3775  */
3776 #define SLI2_SLIM_SIZE (64 * 1024)
3777 
3778 /* Maximum IOCBs that will fit in SLI2 slim */
3779 #define MAX_SLI2_IOCB 498
3780 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3781  (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3782  sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3783 
3784 /* HBQ entries are 4 words each = 4k */
3785 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3786  lpfc_sli_hbq_count())
3787 
3788 struct lpfc_sli2_slim {
3789  MAILBOX_t mbx;
3790  uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3791  PCB_t pcb;
3792  IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3793 };
3794 
3795 /*
3796  * This function checks PCI device to allow special handling for LC HBAs.
3797  *
3798  * Parameters:
3799  * device : struct pci_dev 's device field
3800  *
3801  * return 1 => TRUE
3802  * 0 => FALSE
3803  */
3804 static inline int
3805 lpfc_is_LC_HBA(unsigned short device)
3806 {
3807  if ((device == PCI_DEVICE_ID_TFLY) ||
3808  (device == PCI_DEVICE_ID_PFLY) ||
3809  (device == PCI_DEVICE_ID_LP101) ||
3810  (device == PCI_DEVICE_ID_BMID) ||
3811  (device == PCI_DEVICE_ID_BSMB) ||
3812  (device == PCI_DEVICE_ID_ZMID) ||
3813  (device == PCI_DEVICE_ID_ZSMB) ||
3814  (device == PCI_DEVICE_ID_SAT_MID) ||
3815  (device == PCI_DEVICE_ID_SAT_SMB) ||
3816  (device == PCI_DEVICE_ID_RFLY))
3817  return 1;
3818  else
3819  return 0;
3820 }
3821 
3822 /*
3823  * Determine if an IOCB failed because of a link event or firmware reset.
3824  */
3825 
3826 static inline int
3827 lpfc_error_lost_link(IOCB_t *iocbp)
3828 {
3829  return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3830  (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3831  iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3832  iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3833 }
3834 
3835 #define MENLO_TRANSPORT_TYPE 0xfe
3836 #define MENLO_CONTEXT 0
3837 #define MENLO_PU 3
3838 #define MENLO_TIMEOUT 30
3839 #define SETVAR_MLOMNT 0x103107
3840 #define SETVAR_MLORST 0x103007
3841 
3842 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
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