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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/page.h>Go to the source code of this file.
Macros | |
| #define | MMU_REG_BASE (0xffff0000) |
| #define | ITLB_BASE (0xfe000000) |
| #define | DTLB_BASE (0xfe000800) |
| #define | NR_TLB_ENTRIES CONFIG_TLB_ENTRIES |
| #define | MATM |
| #define | MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */ |
| #define | MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */ |
| #define | MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */ |
| #define | MDEVA |
| #define | MDEVP |
| #define | MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */ |
| #define | MSVA |
| #define | MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */ |
| #define | MIDXI |
| #define | MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */ |
| #define | MATM_offset (MATM - MMU_REG_BASE) |
| #define | MPSZ_offset (MPSZ - MMU_REG_BASE) |
| #define | MASID_offset (MASID - MMU_REG_BASE) |
| #define | MESTS_offset (MESTS - MMU_REG_BASE) |
| #define | MDEVA_offset (MDEVA - MMU_REG_BASE) |
| #define | MDEVP_offset (MDEVP - MMU_REG_BASE) |
| #define | MPTB_offset (MPTB - MMU_REG_BASE) |
| #define | MSVA_offset (MSVA - MMU_REG_BASE) |
| #define | MTOP_offset (MTOP - MMU_REG_BASE) |
| #define | MIDXI_offset (MIDXI - MMU_REG_BASE) |
| #define | MIDXD_offset (MIDXD - MMU_REG_BASE) |
| #define | MESTS_IT (1 << 0) /* Instruction TLB miss */ |
| #define | MESTS_IA (1 << 1) /* Instruction Access Exception */ |
| #define | MESTS_DT (1 << 4) /* Operand TLB miss */ |
| #define | MESTS_DA (1 << 5) /* Operand Access Exception */ |
| #define | MESTS_DRW (1 << 6) /* Operand Write Exception Flag */ |
| #define | M32R_PSW_BIT_SM (7) /* Stack Mode */ |
| #define | M32R_PSW_BIT_IE (6) /* Interrupt Enable */ |
| #define | M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */ |
| #define | M32R_PSW_BIT_C (0) /* Condition */ |
| #define | M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */ |
| #define | M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */ |
| #define | M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */ |
| #define | M32R_PSW_BIT_BC (0+8) /* Backup Condition */ |
| #define | M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */ |
| #define | M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */ |
| #define | M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */ |
| #define | M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */ |
| #define | M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */ |
| #define | M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */ |
| #define | M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */ |
| #define | M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */ |
| #define | NONCACHE_OFFSET __PAGE_OFFSET |
| #define | M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET |
| #define | M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET |
| #define | M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET |
| #define | M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET |
| #define | M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET |
| #define | M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET |
| #define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET |
| #define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET |
| #define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET |
| #define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET |
| #define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET |
| #define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET |
| #define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */ |
| #define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */ |
| #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */ |
| #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */ |
| #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */ |
| #define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */ |
| #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */ |
| #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */ |
| #define MASID_offset (MASID - MMU_REG_BASE) |
| #define MATM |
| #define MATM_offset (MATM - MMU_REG_BASE) |
| #define MDEVA |
| #define MDEVA_offset (MDEVA - MMU_REG_BASE) |
| #define MDEVP |
| #define MDEVP_offset (MDEVP - MMU_REG_BASE) |
| #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */ |
| #define MESTS_offset (MESTS - MMU_REG_BASE) |
| #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */ |
| #define MIDXD_offset (MIDXD - MMU_REG_BASE) |
| #define MIDXI |
| #define MIDXI_offset (MIDXI - MMU_REG_BASE) |
| #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */ |
| #define MPSZ_offset (MPSZ - MMU_REG_BASE) |
| #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */ |
| #define MPTB_offset (MPTB - MMU_REG_BASE) |
| #define MSVA |
| #define MSVA_offset (MSVA - MMU_REG_BASE) |
| #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */ |
| #define MTOP_offset (MTOP - MMU_REG_BASE) |
| #define NONCACHE_OFFSET __PAGE_OFFSET |
1.8.2