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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m5206)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK MCF_CLK |
| #define | MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ |
| #define | MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ |
| #define | MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ |
| #define | MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ |
| #define | MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ |
| #define | MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ |
| #define | MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ |
| #define | MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ |
| #define | MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ |
| #define | MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ |
| #define | MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ |
| #define | MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ |
| #define | MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ |
| #define | MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ |
| #define | MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ |
| #define | MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ |
| #define | MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ |
| #define | MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ |
| #define | MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ |
| #define | MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ |
| #define | MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ |
| #define | MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ |
| #define | MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ |
| #define | MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ |
| #define | MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ |
| #define | MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ |
| #define | MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ |
| #define | MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ |
| #define | MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ |
| #define | MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ |
| #define | MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ |
| #define | MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ |
| #define | MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ |
| #define | MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ |
| #define | MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ |
| #define | MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ |
| #define | MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ |
| #define | MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ |
| #define | MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ |
| #define | MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ |
| #define | MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ |
| #define | MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ |
| #define | MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ |
| #define | MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ |
| #define | MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ |
| #define | MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ |
| #define | MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ |
| #define | MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ |
| #define | MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ |
| #define | MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ |
| #define | MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ |
| #define | MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ |
| #define | MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ |
| #define | MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ |
| #define | MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ |
| #define | MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ |
| #define | MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ |
| #define | MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ |
| #define | MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ |
| #define | MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ |
| #define | MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ |
| #define | MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ |
| #define | MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
| #define | MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
| #define | MCF_IRQ_UART0 73 /* UART0 */ |
| #define | MCF_IRQ_UART1 74 /* UART1 */ |
| #define | MCFGPIO_PIN_MAX 8 |
| #define | MCFGPIO_IRQ_VECBASE -1 |
| #define | MCFGPIO_IRQ_MAX -1 |
| #define | MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ |
| #define | MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ |
| #define | MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ |
| #define | MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ |
| #define | MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 16 of file m5206sim.h.
| #define CPU_NAME "COLDFIRE(m5206)" |
Definition at line 15 of file m5206sim.h.
| #define MCF_BUSCLK MCF_CLK |
Definition at line 17 of file m5206sim.h.
| #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ |
Definition at line 114 of file m5206sim.h.
| #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ |
Definition at line 113 of file m5206sim.h.
| #define MCF_IRQ_UART0 73 /* UART0 */ |
Definition at line 115 of file m5206sim.h.
| #define MCF_IRQ_UART1 74 /* UART1 */ |
Definition at line 116 of file m5206sim.h.
| #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ |
Definition at line 99 of file m5206sim.h.
| #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ |
Definition at line 100 of file m5206sim.h.
| #define MCFGPIO_IRQ_MAX -1 |
Definition at line 123 of file m5206sim.h.
| #define MCFGPIO_IRQ_VECBASE -1 |
Definition at line 122 of file m5206sim.h.
| #define MCFGPIO_PIN_MAX 8 |
Definition at line 121 of file m5206sim.h.
| #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ |
Definition at line 61 of file m5206sim.h.
| #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ |
Definition at line 64 of file m5206sim.h.
| #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ |
Definition at line 67 of file m5206sim.h.
| #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ |
Definition at line 70 of file m5206sim.h.
| #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ |
Definition at line 73 of file m5206sim.h.
| #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ |
Definition at line 76 of file m5206sim.h.
| #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ |
Definition at line 79 of file m5206sim.h.
| #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ |
Definition at line 82 of file m5206sim.h.
| #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ |
Definition at line 63 of file m5206sim.h.
| #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ |
Definition at line 66 of file m5206sim.h.
| #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ |
Definition at line 69 of file m5206sim.h.
| #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ |
Definition at line 72 of file m5206sim.h.
| #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ |
Definition at line 75 of file m5206sim.h.
| #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ |
Definition at line 78 of file m5206sim.h.
| #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ |
Definition at line 81 of file m5206sim.h.
| #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ |
Definition at line 84 of file m5206sim.h.
| #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ |
Definition at line 62 of file m5206sim.h.
| #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ |
Definition at line 65 of file m5206sim.h.
| #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ |
Definition at line 68 of file m5206sim.h.
| #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ |
Definition at line 71 of file m5206sim.h.
| #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ |
Definition at line 74 of file m5206sim.h.
| #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ |
Definition at line 77 of file m5206sim.h.
| #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ |
Definition at line 80 of file m5206sim.h.
| #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ |
Definition at line 83 of file m5206sim.h.
| #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ |
Definition at line 54 of file m5206sim.h.
| #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ |
Definition at line 57 of file m5206sim.h.
| #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ |
Definition at line 56 of file m5206sim.h.
| #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ |
Definition at line 59 of file m5206sim.h.
| #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ |
Definition at line 52 of file m5206sim.h.
| #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ |
Definition at line 53 of file m5206sim.h.
| #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ |
Definition at line 85 of file m5206sim.h.
| #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ |
Definition at line 55 of file m5206sim.h.
| #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ |
Definition at line 58 of file m5206sim.h.
| #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ |
Definition at line 25 of file m5206sim.h.
| #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ |
Definition at line 34 of file m5206sim.h.
| #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ |
Definition at line 35 of file m5206sim.h.
| #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ |
Definition at line 36 of file m5206sim.h.
| #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ |
Definition at line 37 of file m5206sim.h.
| #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ |
Definition at line 26 of file m5206sim.h.
| #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ |
Definition at line 27 of file m5206sim.h.
| #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ |
Definition at line 28 of file m5206sim.h.
| #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ |
Definition at line 29 of file m5206sim.h.
| #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ |
Definition at line 30 of file m5206sim.h.
| #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ |
Definition at line 31 of file m5206sim.h.
| #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ |
Definition at line 32 of file m5206sim.h.
| #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ |
Definition at line 33 of file m5206sim.h.
| #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ |
Definition at line 43 of file m5206sim.h.
| #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ |
Definition at line 44 of file m5206sim.h.
| #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ |
Definition at line 97 of file m5206sim.h.
| #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ |
Definition at line 96 of file m5206sim.h.
| #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ |
Definition at line 90 of file m5206sim.h.
| #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ |
Definition at line 46 of file m5206sim.h.
| #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ |
Definition at line 24 of file m5206sim.h.
| #define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ |
Definition at line 138 of file m5206sim.h.
| #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ |
Definition at line 49 of file m5206sim.h.
| #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ |
Definition at line 50 of file m5206sim.h.
| #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ |
Definition at line 47 of file m5206sim.h.
| #define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ |
Definition at line 139 of file m5206sim.h.
| #define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ |
Definition at line 140 of file m5206sim.h.
| #define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ |
Definition at line 141 of file m5206sim.h.
| #define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ |
Definition at line 142 of file m5206sim.h.
| #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ |
Definition at line 93 of file m5206sim.h.
| #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ |
Definition at line 94 of file m5206sim.h.
| #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ |
Definition at line 106 of file m5206sim.h.
| #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ |
Definition at line 107 of file m5206sim.h.
1.8.2