#include <linux/module.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/ioctl.h>
#include <linux/synclink.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/dma.h>
#include <linux/bitops.h>
#include <asm/types.h>
#include <linux/termios.h>
#include <linux/workqueue.h>
#include <linux/hdlc.h>
#include <linux/dma-mapping.h>
#include <asm/uaccess.h>

Data Structures
struct	_DMABUFFERENTRY

struct	_input_signal_events

struct	tx_holding_buffer

struct	mgsl_struct

Macros
#define	BREAKPOINT() { }

#define	MAX_ISA_DEVICES 10

#define	MAX_PCI_DEVICES 10

#define	MAX_TOTAL_DEVICES 20

#define	SYNCLINK_GENERIC_HDLC 0

#define	GET_USER(error, value, addr) error = get_user(value,addr)

#define	COPY_FROM_USER(error, dest, src, size) error = copy_from_user(dest,src,size) ? -EFAULT : 0

#define	PUT_USER(error, value, addr) error = put_user(value,addr)

#define	COPY_TO_USER(error, dest, src, size) error = copy_to_user(dest,src,size) ? -EFAULT : 0

#define	RCLRVALUE 0xffff

#define	SHARED_MEM_ADDRESS_SIZE 0x40000

#define	BUFFERLISTSIZE 4096

#define	DMABUFFERSIZE 4096

#define	MAXRXFRAMES 7

#define	BH_RECEIVE 1

#define	BH_TRANSMIT 2

#define	BH_STATUS 4

#define	IO_PIN_SHUTDOWN_LIMIT 100

#define	MAX_TX_HOLDING_BUFFERS 5

#define	MGSL_MAGIC 0x5401

#define	SERIAL_XMIT_SIZE 4096

#define	DCPIN 2 /* Bit 1 of I/O address */

#define	SDPIN 4 /* Bit 2 of I/O address */

#define	DCAR 0 /* DMA command/address register */

#define	CCAR SDPIN /* channel command/address register */

#define	DATAREG DCPIN + SDPIN /* serial data register */

#define	MSBONLY 0x41

#define	LSBONLY 0x40

#define	CMR 0x02 /* Channel mode Register */

#define	CCSR 0x04 /* Channel Command/status Register */

#define	CCR 0x06 /* Channel Control Register */

#define	PSR 0x08 /* Port status Register */

#define	PCR 0x0a /* Port Control Register */

#define	TMDR 0x0c /* Test mode Data Register */

#define	TMCR 0x0e /* Test mode Control Register */

#define	CMCR 0x10 /* Clock mode Control Register */

#define	HCR 0x12 /* Hardware Configuration Register */

#define	IVR 0x14 /* Interrupt Vector Register */

#define	IOCR 0x16 /* Input/Output Control Register */

#define	ICR 0x18 /* Interrupt Control Register */

#define	DCCR 0x1a /* Daisy Chain Control Register */

#define	MISR 0x1c /* Misc Interrupt status Register */

#define	SICR 0x1e /* status Interrupt Control Register */

#define	RDR 0x20 /* Receive Data Register */

#define	RMR 0x22 /* Receive mode Register */

#define	RCSR 0x24 /* Receive Command/status Register */

#define	RICR 0x26 /* Receive Interrupt Control Register */

#define	RSR 0x28 /* Receive Sync Register */

#define	RCLR 0x2a /* Receive count Limit Register */

#define	RCCR 0x2c /* Receive Character count Register */

#define	TC0R 0x2e /* Time Constant 0 Register */

#define	TDR 0x30 /* Transmit Data Register */

#define	TMR 0x32 /* Transmit mode Register */

#define	TCSR 0x34 /* Transmit Command/status Register */

#define	TICR 0x36 /* Transmit Interrupt Control Register */

#define	TSR 0x38 /* Transmit Sync Register */

#define	TCLR 0x3a /* Transmit count Limit Register */

#define	TCCR 0x3c /* Transmit Character count Register */

#define	TC1R 0x3e /* Time Constant 1 Register */

#define	DCR 0x06 /* DMA Control Register (shared) */

#define	DACR 0x08 /* DMA Array count Register (shared) */

#define	BDCR 0x12 /* Burst/Dwell Control Register (shared) */

#define	DIVR 0x14 /* DMA Interrupt Vector Register (shared) */

#define	DICR 0x18 /* DMA Interrupt Control Register (shared) */

#define	CDIR 0x1a /* Clear DMA Interrupt Register (shared) */

#define	SDIR 0x1c /* Set DMA Interrupt Register (shared) */

#define	TDMR 0x02 /* Transmit DMA mode Register */

#define	TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */

#define	TBCR 0x2a /* Transmit Byte count Register */

#define	TARL 0x2c /* Transmit Address Register (low) */

#define	TARU 0x2e /* Transmit Address Register (high) */

#define	NTBCR 0x3a /* Next Transmit Byte count Register */

#define	NTARL 0x3c /* Next Transmit Address Register (low) */

#define	NTARU 0x3e /* Next Transmit Address Register (high) */

#define	RDMR 0x82 /* Receive DMA mode Register (non-shared) */

#define	RDIAR 0x9e /* Receive DMA Interrupt Arm Register */

#define	RBCR 0xaa /* Receive Byte count Register */

#define	RARL 0xac /* Receive Address Register (low) */

#define	RARU 0xae /* Receive Address Register (high) */

#define	NRBCR 0xba /* Next Receive Byte count Register */

#define	NRARL 0xbc /* Next Receive Address Register (low) */

#define	NRARU 0xbe /* Next Receive Address Register (high) */

#define	MODEMSTATUS_DTR 0x80

#define	MODEMSTATUS_DSR 0x40

#define	MODEMSTATUS_RTS 0x20

#define	MODEMSTATUS_CTS 0x10

#define	MODEMSTATUS_RI 0x04

#define	MODEMSTATUS_DCD 0x01

#define	RTCmd_Null 0x0000

#define	RTCmd_ResetHighestIus 0x1000

#define	RTCmd_TriggerChannelLoadDma 0x2000

#define	RTCmd_TriggerRxDma 0x2800

#define	RTCmd_TriggerTxDma 0x3000

#define	RTCmd_TriggerRxAndTxDma 0x3800

#define	RTCmd_PurgeRxFifo 0x4800

#define	RTCmd_PurgeTxFifo 0x5000

#define	RTCmd_PurgeRxAndTxFifo 0x5800

#define	RTCmd_LoadRcc 0x6800

#define	RTCmd_LoadTcc 0x7000

#define	RTCmd_LoadRccAndTcc 0x7800

#define	RTCmd_LoadTC0 0x8800

#define	RTCmd_LoadTC1 0x9000

#define	RTCmd_LoadTC0AndTC1 0x9800

#define	RTCmd_SerialDataLSBFirst 0xa000

#define	RTCmd_SerialDataMSBFirst 0xa800

#define	RTCmd_SelectBigEndian 0xb000

#define	RTCmd_SelectLittleEndian 0xb800

#define	DmaCmd_Null 0x0000

#define	DmaCmd_ResetTxChannel 0x1000

#define	DmaCmd_ResetRxChannel 0x1200

#define	DmaCmd_StartTxChannel 0x2000

#define	DmaCmd_StartRxChannel 0x2200

#define	DmaCmd_ContinueTxChannel 0x3000

#define	DmaCmd_ContinueRxChannel 0x3200

#define	DmaCmd_PauseTxChannel 0x4000

#define	DmaCmd_PauseRxChannel 0x4200

#define	DmaCmd_AbortTxChannel 0x5000

#define	DmaCmd_AbortRxChannel 0x5200

#define	DmaCmd_InitTxChannel 0x7000

#define	DmaCmd_InitRxChannel 0x7200

#define	DmaCmd_ResetHighestDmaIus 0x8000

#define	DmaCmd_ResetAllChannels 0x9000

#define	DmaCmd_StartAllChannels 0xa000

#define	DmaCmd_ContinueAllChannels 0xb000

#define	DmaCmd_PauseAllChannels 0xc000

#define	DmaCmd_AbortAllChannels 0xd000

#define	DmaCmd_InitAllChannels 0xf000

#define	TCmd_Null 0x0000

#define	TCmd_ClearTxCRC 0x2000

#define	TCmd_SelectTicrTtsaData 0x4000

#define	TCmd_SelectTicrTxFifostatus 0x5000

#define	TCmd_SelectTicrIntLevel 0x6000

#define	TCmd_SelectTicrdma_level 0x7000

#define	TCmd_SendFrame 0x8000

#define	TCmd_SendAbort 0x9000

#define	TCmd_EnableDleInsertion 0xc000

#define	TCmd_DisableDleInsertion 0xd000

#define	TCmd_ClearEofEom 0xe000

#define	TCmd_SetEofEom 0xf000

#define	RCmd_Null 0x0000

#define	RCmd_ClearRxCRC 0x2000

#define	RCmd_EnterHuntmode 0x3000

#define	RCmd_SelectRicrRtsaData 0x4000

#define	RCmd_SelectRicrRxFifostatus 0x5000

#define	RCmd_SelectRicrIntLevel 0x6000

#define	RCmd_SelectRicrdma_level 0x7000

#define	RECEIVE_STATUS BIT5

#define	RECEIVE_DATA BIT4

#define	TRANSMIT_STATUS BIT3

#define	TRANSMIT_DATA BIT2

#define	IO_PIN BIT1

#define	MISC BIT0

#define	RXSTATUS_SHORT_FRAME BIT8

#define	RXSTATUS_CODE_VIOLATION BIT8

#define	RXSTATUS_EXITED_HUNT BIT7

#define	RXSTATUS_IDLE_RECEIVED BIT6

#define	RXSTATUS_BREAK_RECEIVED BIT5

#define	RXSTATUS_ABORT_RECEIVED BIT5

#define	RXSTATUS_RXBOUND BIT4

#define	RXSTATUS_CRC_ERROR BIT3

#define	RXSTATUS_FRAMING_ERROR BIT3

#define	RXSTATUS_ABORT BIT2

#define	RXSTATUS_PARITY_ERROR BIT2

#define	RXSTATUS_OVERRUN BIT1

#define	RXSTATUS_DATA_AVAILABLE BIT0

#define	RXSTATUS_ALL 0x01f6

#define	usc_UnlatchRxstatusBits(a, b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )

#define	IDLEMODE_FLAGS 0x0000

#define	IDLEMODE_ALT_ONE_ZERO 0x0100

#define	IDLEMODE_ZERO 0x0200

#define	IDLEMODE_ONE 0x0300

#define	IDLEMODE_ALT_MARK_SPACE 0x0500

#define	IDLEMODE_SPACE 0x0600

#define	IDLEMODE_MARK 0x0700

#define	IDLEMODE_MASK 0x0700

#define	IUSC_SL1660 0x4d44

#define	IUSC_PRE_SL1660 0x4553

#define	TCSR_PRESERVE 0x0F00

#define	TCSR_UNDERWAIT BIT11

#define	TXSTATUS_PREAMBLE_SENT BIT7

#define	TXSTATUS_IDLE_SENT BIT6

#define	TXSTATUS_ABORT_SENT BIT5

#define	TXSTATUS_EOF_SENT BIT4

#define	TXSTATUS_EOM_SENT BIT4

#define	TXSTATUS_CRC_SENT BIT3

#define	TXSTATUS_ALL_SENT BIT2

#define	TXSTATUS_UNDERRUN BIT1

#define	TXSTATUS_FIFO_EMPTY BIT0

#define	TXSTATUS_ALL 0x00fa

#define	usc_UnlatchTxstatusBits(a, b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )

#define	MISCSTATUS_RXC_LATCHED BIT15

#define	MISCSTATUS_RXC BIT14

#define	MISCSTATUS_TXC_LATCHED BIT13

#define	MISCSTATUS_TXC BIT12

#define	MISCSTATUS_RI_LATCHED BIT11

#define	MISCSTATUS_RI BIT10

#define	MISCSTATUS_DSR_LATCHED BIT9

#define	MISCSTATUS_DSR BIT8

#define	MISCSTATUS_DCD_LATCHED BIT7

#define	MISCSTATUS_DCD BIT6

#define	MISCSTATUS_CTS_LATCHED BIT5

#define	MISCSTATUS_CTS BIT4

#define	MISCSTATUS_RCC_UNDERRUN BIT3

#define	MISCSTATUS_DPLL_NO_SYNC BIT2

#define	MISCSTATUS_BRG1_ZERO BIT1

#define	MISCSTATUS_BRG0_ZERO BIT0

#define	usc_UnlatchIostatusBits(a, b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))

#define	usc_UnlatchMiscstatusBits(a, b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))

#define	SICR_RXC_ACTIVE BIT15

#define	SICR_RXC_INACTIVE BIT14

#define	SICR_RXC (BIT15+BIT14)

#define	SICR_TXC_ACTIVE BIT13

#define	SICR_TXC_INACTIVE BIT12

#define	SICR_TXC (BIT13+BIT12)

#define	SICR_RI_ACTIVE BIT11

#define	SICR_RI_INACTIVE BIT10

#define	SICR_RI (BIT11+BIT10)

#define	SICR_DSR_ACTIVE BIT9

#define	SICR_DSR_INACTIVE BIT8

#define	SICR_DSR (BIT9+BIT8)

#define	SICR_DCD_ACTIVE BIT7

#define	SICR_DCD_INACTIVE BIT6

#define	SICR_DCD (BIT7+BIT6)

#define	SICR_CTS_ACTIVE BIT5

#define	SICR_CTS_INACTIVE BIT4

#define	SICR_CTS (BIT5+BIT4)

#define	SICR_RCC_UNDERFLOW BIT3

#define	SICR_DPLL_NO_SYNC BIT2

#define	SICR_BRG1_ZERO BIT1

#define	SICR_BRG0_ZERO BIT0

#define	usc_EnableInterrupts(a, b) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )

#define	usc_DisableInterrupts(a, b) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )

#define	usc_EnableMasterIrqBit(a) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )

#define	usc_DisableMasterIrqBit(a) usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )

#define	usc_ClearIrqPendingBits(a, b) usc_OutReg( (a), DCCR, 0x40 + (b) )

#define	TXSTATUS_PREAMBLE_SENT BIT7

#define	TXSTATUS_IDLE_SENT BIT6

#define	TXSTATUS_ABORT_SENT BIT5

#define	TXSTATUS_EOF BIT4

#define	TXSTATUS_CRC_SENT BIT3

#define	TXSTATUS_ALL_SENT BIT2

#define	TXSTATUS_UNDERRUN BIT1

#define	TXSTATUS_FIFO_EMPTY BIT0

#define	DICR_MASTER BIT15

#define	DICR_TRANSMIT BIT0

#define	DICR_RECEIVE BIT1

#define	usc_EnableDmaInterrupts(a, b) usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) \| (b)) )

#define	usc_DisableDmaInterrupts(a, b) usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )

#define	usc_EnableStatusIrqs(a, b) usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) \| (b)) )

#define	usc_DisablestatusIrqs(a, b) usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )

#define	DISABLE_UNCONDITIONAL 0

#define	DISABLE_END_OF_FRAME 1

#define	ENABLE_UNCONDITIONAL 2

#define	ENABLE_AUTO_CTS 3

#define	ENABLE_AUTO_DCD 3

#define	usc_EnableTransmitter(a, b) usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) \| (b)) )

#define	usc_EnableReceiver(a, b) usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) \| (b)) )

#define	usc_TCmd(a, b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))

#define	usc_RCmd(a, b) usc_OutReg((a), RCSR, (b))

#define	usc_SetTransmitSyncChars(a, s0, s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)\|(u16)s1))

#define	BUS_DESCRIPTOR(WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad)

#define	WAKEUP_CHARS 256

#define	TESTFRAMESIZE 40

#define	PCI_LOAD_INTERVAL 64

Typedefs
typedef struct _DMABUFFERENTRY	DMABUFFERENTRY

typedef struct _DMABUFFERENTRY *	DMAPBUFFERENTRY

typedef void(*	isr_dispatch_func )(struct mgsl_struct *)

Functions
void	usc_DisableMasterIrqBit (struct mgsl_struct *info)

void	usc_EnableMasterIrqBit (struct mgsl_struct *info)

void	usc_EnableInterrupts (struct mgsl_struct *info, u16 IrqMask)

void	usc_DisableInterrupts (struct mgsl_struct *info, u16 IrqMask)

void	usc_ClearIrqPendingBits (struct mgsl_struct *info, u16 IrqMask)

void	usc_RCmd (struct mgsl_struct *info, u16 Cmd)

void	usc_TCmd (struct mgsl_struct *info, u16 Cmd)

	module_param (break_on_load, bool, 0)

	module_param (ttymajor, int, 0)

	module_param_array (io, int, NULL, 0)

	module_param_array (irq, int, NULL, 0)

	module_param_array (dma, int, NULL, 0)

	module_param (debug_level, int, 0)

	module_param_array (maxframe, int, NULL, 0)

	module_param_array (txdmabufs, int, NULL, 0)

	module_param_array (txholdbufs, int, NULL, 0)

	MODULE_DEVICE_TABLE (pci, synclink_pci_tbl)

	MODULE_LICENSE ("GPL")

	module_init (synclink_init)

	module_exit (synclink_exit)

Macro Definition Documentation

#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */

Definition at line 380 of file synclink.c.

#define BH_RECEIVE 1

Definition at line 150 of file synclink.c.

#define BH_STATUS 4

Definition at line 152 of file synclink.c.

#define BH_TRANSMIT 2

Definition at line 151 of file synclink.c.

#define BREAKPOINT ( ) { }

Definition at line 57 of file synclink.c.

#define BUFFERLISTSIZE 4096

Definition at line 131 of file synclink.c.

#define BUS_DESCRIPTOR	(	WrHold,
		WrDly,
		RdDly,
		Nwdd,
		Nwad,
		Nxda,
		Nrdd,
		Nrad
	)

Value:

(0x00400020 + \
((WrHold) << 30) + \
((WrDly)  << 28) + \
((RdDly)  << 26) + \
((Nwdd)   << 20) + \
((Nwad)   << 15) + \
((Nxda)   << 13) + \
((Nrdd)   << 11) + \
((Nrad)   <<  6) )

Definition at line 728 of file synclink.c.

#define CCAR SDPIN /* channel command/address register */

Definition at line 331 of file synclink.c.

#define CCR 0x06 /* Channel Control Register */

Definition at line 343 of file synclink.c.

#define CCSR 0x04 /* Channel Command/status Register */

Definition at line 342 of file synclink.c.

#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */

Definition at line 383 of file synclink.c.

#define CMCR 0x10 /* Clock mode Control Register */

Definition at line 348 of file synclink.c.

#define CMR 0x02 /* Channel mode Register */

Definition at line 341 of file synclink.c.

#define COPY_FROM_USER	(	error,
		dest,
		src,
		size
	)	error = copy_from_user(dest,src,size) ? -EFAULT : 0

Definition at line 106 of file synclink.c.

#define COPY_TO_USER	(	error,
		dest,
		src,
		size
	)	error = copy_to_user(dest,src,size) ? -EFAULT : 0

Definition at line 108 of file synclink.c.

#define DACR 0x08 /* DMA Array count Register (shared) */

Definition at line 379 of file synclink.c.

#define DATAREG DCPIN + SDPIN /* serial data register */

Definition at line 332 of file synclink.c.

#define DCAR 0 /* DMA command/address register */

Definition at line 330 of file synclink.c.

#define DCCR 0x1a /* Daisy Chain Control Register */

Definition at line 353 of file synclink.c.

#define DCPIN 2 /* Bit 1 of I/O address */

Definition at line 327 of file synclink.c.

#define DCR 0x06 /* DMA Control Register (shared) */

Definition at line 378 of file synclink.c.

#define DICR 0x18 /* DMA Interrupt Control Register (shared) */

Definition at line 382 of file synclink.c.

#define DICR_MASTER BIT15

Definition at line 636 of file synclink.c.

#define DICR_RECEIVE BIT1

Definition at line 638 of file synclink.c.

#define DICR_TRANSMIT BIT0

Definition at line 637 of file synclink.c.

#define DISABLE_END_OF_FRAME 1

Definition at line 657 of file synclink.c.

#define DISABLE_UNCONDITIONAL 0

Definition at line 656 of file synclink.c.

#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */

Definition at line 381 of file synclink.c.

#define DMABUFFERSIZE 4096

Definition at line 132 of file synclink.c.

#define DmaCmd_AbortAllChannels 0xd000

Definition at line 464 of file synclink.c.

#define DmaCmd_AbortRxChannel 0x5200

Definition at line 456 of file synclink.c.

#define DmaCmd_AbortTxChannel 0x5000

Definition at line 455 of file synclink.c.

#define DmaCmd_ContinueAllChannels 0xb000

Definition at line 462 of file synclink.c.

#define DmaCmd_ContinueRxChannel 0x3200

Definition at line 452 of file synclink.c.

#define DmaCmd_ContinueTxChannel 0x3000

Definition at line 451 of file synclink.c.

#define DmaCmd_InitAllChannels 0xf000

Definition at line 465 of file synclink.c.

#define DmaCmd_InitRxChannel 0x7200

Definition at line 458 of file synclink.c.

#define DmaCmd_InitTxChannel 0x7000

Definition at line 457 of file synclink.c.

#define DmaCmd_Null 0x0000

Definition at line 446 of file synclink.c.

#define DmaCmd_PauseAllChannels 0xc000

Definition at line 463 of file synclink.c.

#define DmaCmd_PauseRxChannel 0x4200

Definition at line 454 of file synclink.c.

#define DmaCmd_PauseTxChannel 0x4000

Definition at line 453 of file synclink.c.

#define DmaCmd_ResetAllChannels 0x9000

Definition at line 460 of file synclink.c.

#define DmaCmd_ResetHighestDmaIus 0x8000

Definition at line 459 of file synclink.c.

#define DmaCmd_ResetRxChannel 0x1200

Definition at line 448 of file synclink.c.

#define DmaCmd_ResetTxChannel 0x1000

Definition at line 447 of file synclink.c.

#define DmaCmd_StartAllChannels 0xa000

Definition at line 461 of file synclink.c.

#define DmaCmd_StartRxChannel 0x2200

Definition at line 450 of file synclink.c.

#define DmaCmd_StartTxChannel 0x2000

Definition at line 449 of file synclink.c.

#define ENABLE_AUTO_CTS 3

Definition at line 659 of file synclink.c.

#define ENABLE_AUTO_DCD 3

Definition at line 660 of file synclink.c.

#define ENABLE_UNCONDITIONAL 2

Definition at line 658 of file synclink.c.

#define GET_USER	(	error,
		value,
		addr
	)	error = get_user(value,addr)

Definition at line 105 of file synclink.c.

#define HCR 0x12 /* Hardware Configuration Register */

Definition at line 349 of file synclink.c.

#define ICR 0x18 /* Interrupt Control Register */

Definition at line 352 of file synclink.c.

#define IDLEMODE_ALT_MARK_SPACE 0x0500

Definition at line 528 of file synclink.c.

#define IDLEMODE_ALT_ONE_ZERO 0x0100

Definition at line 525 of file synclink.c.

#define IDLEMODE_FLAGS 0x0000

Definition at line 524 of file synclink.c.

#define IDLEMODE_MARK 0x0700

Definition at line 530 of file synclink.c.

#define IDLEMODE_MASK 0x0700

Definition at line 531 of file synclink.c.

#define IDLEMODE_ONE 0x0300

Definition at line 527 of file synclink.c.

#define IDLEMODE_SPACE 0x0600

Definition at line 529 of file synclink.c.

#define IDLEMODE_ZERO 0x0200

Definition at line 526 of file synclink.c.

#define IO_PIN BIT1

Definition at line 496 of file synclink.c.

#define IO_PIN_SHUTDOWN_LIMIT 100

Definition at line 154 of file synclink.c.

#define IOCR 0x16 /* Input/Output Control Register */

Definition at line 351 of file synclink.c.

#define IUSC_PRE_SL1660 0x4553

Definition at line 537 of file synclink.c.

#define IUSC_SL1660 0x4d44

Definition at line 536 of file synclink.c.

#define IVR 0x14 /* Interrupt Vector Register */

Definition at line 350 of file synclink.c.

#define LSBONLY 0x40

Definition at line 334 of file synclink.c.

#define MAX_ISA_DEVICES 10

Definition at line 60 of file synclink.c.

#define MAX_PCI_DEVICES 10

Definition at line 61 of file synclink.c.

#define MAX_TOTAL_DEVICES 20

Definition at line 62 of file synclink.c.

#define MAX_TX_HOLDING_BUFFERS 5

Definition at line 168 of file synclink.c.

#define MAXRXFRAMES 7

Definition at line 133 of file synclink.c.

#define MGSL_MAGIC 0x5401

Definition at line 312 of file synclink.c.

#define MISC BIT0

Definition at line 497 of file synclink.c.

#define MISCSTATUS_BRG0_ZERO BIT0

Definition at line 574 of file synclink.c.

#define MISCSTATUS_BRG1_ZERO BIT1

Definition at line 573 of file synclink.c.

#define MISCSTATUS_CTS BIT4

Definition at line 570 of file synclink.c.

#define MISCSTATUS_CTS_LATCHED BIT5

Definition at line 569 of file synclink.c.

#define MISCSTATUS_DCD BIT6

Definition at line 568 of file synclink.c.

#define MISCSTATUS_DCD_LATCHED BIT7

Definition at line 567 of file synclink.c.

#define MISCSTATUS_DPLL_NO_SYNC BIT2

Definition at line 572 of file synclink.c.

#define MISCSTATUS_DSR BIT8

Definition at line 566 of file synclink.c.

#define MISCSTATUS_DSR_LATCHED BIT9

Definition at line 565 of file synclink.c.

#define MISCSTATUS_RCC_UNDERRUN BIT3

Definition at line 571 of file synclink.c.

#define MISCSTATUS_RI BIT10

Definition at line 564 of file synclink.c.

#define MISCSTATUS_RI_LATCHED BIT11

Definition at line 563 of file synclink.c.

#define MISCSTATUS_RXC BIT14

Definition at line 560 of file synclink.c.

#define MISCSTATUS_RXC_LATCHED BIT15

Definition at line 559 of file synclink.c.

#define MISCSTATUS_TXC BIT12

Definition at line 562 of file synclink.c.

#define MISCSTATUS_TXC_LATCHED BIT13

Definition at line 561 of file synclink.c.

#define MISR 0x1c /* Misc Interrupt status Register */

Definition at line 354 of file synclink.c.

#define MODEMSTATUS_CTS 0x10

Definition at line 412 of file synclink.c.

#define MODEMSTATUS_DCD 0x01

Definition at line 414 of file synclink.c.

#define MODEMSTATUS_DSR 0x40

Definition at line 410 of file synclink.c.

#define MODEMSTATUS_DTR 0x80

Definition at line 409 of file synclink.c.

#define MODEMSTATUS_RI 0x04

Definition at line 413 of file synclink.c.

#define MODEMSTATUS_RTS 0x20

Definition at line 411 of file synclink.c.

#define MSBONLY 0x41

Definition at line 333 of file synclink.c.

#define NRARL 0xbc /* Next Receive Address Register (low) */

Definition at line 401 of file synclink.c.

#define NRARU 0xbe /* Next Receive Address Register (high) */

Definition at line 402 of file synclink.c.

#define NRBCR 0xba /* Next Receive Byte count Register */

Definition at line 400 of file synclink.c.

#define NTARL 0x3c /* Next Transmit Address Register (low) */

Definition at line 392 of file synclink.c.

#define NTARU 0x3e /* Next Transmit Address Register (high) */

Definition at line 393 of file synclink.c.

#define NTBCR 0x3a /* Next Transmit Byte count Register */

Definition at line 391 of file synclink.c.

#define PCI_LOAD_INTERVAL 64

#define PCR 0x0a /* Port Control Register */

Definition at line 345 of file synclink.c.

#define PSR 0x08 /* Port status Register */

Definition at line 344 of file synclink.c.

#define PUT_USER	(	error,
		value,
		addr
	)	error = put_user(value,addr)

Definition at line 107 of file synclink.c.

#define RARL 0xac /* Receive Address Register (low) */

Definition at line 398 of file synclink.c.

#define RARU 0xae /* Receive Address Register (high) */

Definition at line 399 of file synclink.c.

#define RBCR 0xaa /* Receive Byte count Register */

Definition at line 397 of file synclink.c.

#define RCCR 0x2c /* Receive Character count Register */

Definition at line 362 of file synclink.c.

#define RCLR 0x2a /* Receive count Limit Register */

Definition at line 361 of file synclink.c.

#define RCLRVALUE 0xffff

Definition at line 112 of file synclink.c.

#define RCmd_ClearRxCRC 0x2000

Definition at line 481 of file synclink.c.

#define RCmd_EnterHuntmode 0x3000

Definition at line 482 of file synclink.c.

#define RCmd_Null 0x0000

Definition at line 480 of file synclink.c.

#define RCmd_SelectRicrdma_level 0x7000

Definition at line 486 of file synclink.c.

#define RCmd_SelectRicrIntLevel 0x6000

Definition at line 485 of file synclink.c.

#define RCmd_SelectRicrRtsaData 0x4000

Definition at line 483 of file synclink.c.

#define RCmd_SelectRicrRxFifostatus 0x5000

Definition at line 484 of file synclink.c.

#define RCSR 0x24 /* Receive Command/status Register */

Definition at line 358 of file synclink.c.

#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */

Definition at line 396 of file synclink.c.

#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */

Definition at line 395 of file synclink.c.

#define RDR 0x20 /* Receive Data Register */

Definition at line 356 of file synclink.c.

#define RECEIVE_DATA BIT4

Definition at line 493 of file synclink.c.

#define RECEIVE_STATUS BIT5

Definition at line 492 of file synclink.c.

#define RICR 0x26 /* Receive Interrupt Control Register */

Definition at line 359 of file synclink.c.

#define RMR 0x22 /* Receive mode Register */

Definition at line 357 of file synclink.c.

#define RSR 0x28 /* Receive Sync Register */

Definition at line 360 of file synclink.c.

#define RTCmd_LoadRcc 0x6800

Definition at line 430 of file synclink.c.

#define RTCmd_LoadRccAndTcc 0x7800

Definition at line 432 of file synclink.c.

#define RTCmd_LoadTC0 0x8800

Definition at line 433 of file synclink.c.

#define RTCmd_LoadTC0AndTC1 0x9800

Definition at line 435 of file synclink.c.

#define RTCmd_LoadTC1 0x9000

Definition at line 434 of file synclink.c.

#define RTCmd_LoadTcc 0x7000

Definition at line 431 of file synclink.c.

#define RTCmd_Null 0x0000

Definition at line 421 of file synclink.c.

#define RTCmd_PurgeRxAndTxFifo 0x5800

Definition at line 429 of file synclink.c.

#define RTCmd_PurgeRxFifo 0x4800

Definition at line 427 of file synclink.c.

#define RTCmd_PurgeTxFifo 0x5000

Definition at line 428 of file synclink.c.

#define RTCmd_ResetHighestIus 0x1000

Definition at line 422 of file synclink.c.

#define RTCmd_SelectBigEndian 0xb000

Definition at line 438 of file synclink.c.

#define RTCmd_SelectLittleEndian 0xb800

Definition at line 439 of file synclink.c.

#define RTCmd_SerialDataLSBFirst 0xa000

Definition at line 436 of file synclink.c.

#define RTCmd_SerialDataMSBFirst 0xa800

Definition at line 437 of file synclink.c.

#define RTCmd_TriggerChannelLoadDma 0x2000

Definition at line 423 of file synclink.c.

#define RTCmd_TriggerRxAndTxDma 0x3800

Definition at line 426 of file synclink.c.

#define RTCmd_TriggerRxDma 0x2800

Definition at line 424 of file synclink.c.

#define RTCmd_TriggerTxDma 0x3000

Definition at line 425 of file synclink.c.

#define RXSTATUS_ABORT BIT2

Definition at line 513 of file synclink.c.

#define RXSTATUS_ABORT_RECEIVED BIT5

Definition at line 509 of file synclink.c.

#define RXSTATUS_ALL 0x01f6

Definition at line 517 of file synclink.c.

#define RXSTATUS_BREAK_RECEIVED BIT5

Definition at line 508 of file synclink.c.

#define RXSTATUS_CODE_VIOLATION BIT8

Definition at line 505 of file synclink.c.

#define RXSTATUS_CRC_ERROR BIT3

Definition at line 511 of file synclink.c.

#define RXSTATUS_DATA_AVAILABLE BIT0

Definition at line 516 of file synclink.c.

#define RXSTATUS_EXITED_HUNT BIT7

Definition at line 506 of file synclink.c.

#define RXSTATUS_FRAMING_ERROR BIT3

Definition at line 512 of file synclink.c.

#define RXSTATUS_IDLE_RECEIVED BIT6

Definition at line 507 of file synclink.c.

#define RXSTATUS_OVERRUN BIT1

Definition at line 515 of file synclink.c.

#define RXSTATUS_PARITY_ERROR BIT2

Definition at line 514 of file synclink.c.

#define RXSTATUS_RXBOUND BIT4

Definition at line 510 of file synclink.c.

#define RXSTATUS_SHORT_FRAME BIT8

Definition at line 504 of file synclink.c.

#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */

Definition at line 384 of file synclink.c.

#define SDPIN 4 /* Bit 2 of I/O address */

Definition at line 328 of file synclink.c.

#define SERIAL_XMIT_SIZE 4096

Definition at line 318 of file synclink.c.

#define SHARED_MEM_ADDRESS_SIZE 0x40000

Definition at line 130 of file synclink.c.

#define SICR 0x1e /* status Interrupt Control Register */

Definition at line 355 of file synclink.c.

#define SICR_BRG0_ZERO BIT0

Definition at line 600 of file synclink.c.

#define SICR_BRG1_ZERO BIT1

Definition at line 599 of file synclink.c.

#define SICR_CTS (BIT5+BIT4)

Definition at line 596 of file synclink.c.

#define SICR_CTS_ACTIVE BIT5

Definition at line 594 of file synclink.c.

#define SICR_CTS_INACTIVE BIT4

Definition at line 595 of file synclink.c.

#define SICR_DCD (BIT7+BIT6)

Definition at line 593 of file synclink.c.

#define SICR_DCD_ACTIVE BIT7

Definition at line 591 of file synclink.c.

#define SICR_DCD_INACTIVE BIT6

Definition at line 592 of file synclink.c.

#define SICR_DPLL_NO_SYNC BIT2

Definition at line 598 of file synclink.c.

#define SICR_DSR (BIT9+BIT8)

Definition at line 590 of file synclink.c.

#define SICR_DSR_ACTIVE BIT9

Definition at line 588 of file synclink.c.

#define SICR_DSR_INACTIVE BIT8

Definition at line 589 of file synclink.c.

#define SICR_RCC_UNDERFLOW BIT3

Definition at line 597 of file synclink.c.

#define SICR_RI (BIT11+BIT10)

Definition at line 587 of file synclink.c.

#define SICR_RI_ACTIVE BIT11

Definition at line 585 of file synclink.c.

#define SICR_RI_INACTIVE BIT10

Definition at line 586 of file synclink.c.

#define SICR_RXC (BIT15+BIT14)

Definition at line 581 of file synclink.c.

#define SICR_RXC_ACTIVE BIT15

Definition at line 579 of file synclink.c.

#define SICR_RXC_INACTIVE BIT14

Definition at line 580 of file synclink.c.

#define SICR_TXC (BIT13+BIT12)

Definition at line 584 of file synclink.c.

#define SICR_TXC_ACTIVE BIT13

Definition at line 582 of file synclink.c.

#define SICR_TXC_INACTIVE BIT12

Definition at line 583 of file synclink.c.

#define SYNCLINK_GENERIC_HDLC 0

Definition at line 102 of file synclink.c.

#define TARL 0x2c /* Transmit Address Register (low) */

Definition at line 389 of file synclink.c.

#define TARU 0x2e /* Transmit Address Register (high) */

Definition at line 390 of file synclink.c.

#define TBCR 0x2a /* Transmit Byte count Register */

Definition at line 388 of file synclink.c.

#define TC0R 0x2e /* Time Constant 0 Register */

Definition at line 363 of file synclink.c.

#define TC1R 0x3e /* Time Constant 1 Register */

Definition at line 371 of file synclink.c.

#define TCCR 0x3c /* Transmit Character count Register */

Definition at line 370 of file synclink.c.

#define TCLR 0x3a /* Transmit count Limit Register */

Definition at line 369 of file synclink.c.

#define TCmd_ClearEofEom 0xe000

Definition at line 477 of file synclink.c.

#define TCmd_ClearTxCRC 0x2000

Definition at line 468 of file synclink.c.

#define TCmd_DisableDleInsertion 0xd000

Definition at line 476 of file synclink.c.

#define TCmd_EnableDleInsertion 0xc000

Definition at line 475 of file synclink.c.

#define TCmd_Null 0x0000

Definition at line 467 of file synclink.c.

#define TCmd_SelectTicrdma_level 0x7000

Definition at line 472 of file synclink.c.

#define TCmd_SelectTicrIntLevel 0x6000

Definition at line 471 of file synclink.c.

#define TCmd_SelectTicrTtsaData 0x4000

Definition at line 469 of file synclink.c.

#define TCmd_SelectTicrTxFifostatus 0x5000

Definition at line 470 of file synclink.c.

#define TCmd_SendAbort 0x9000

Definition at line 474 of file synclink.c.

#define TCmd_SendFrame 0x8000

Definition at line 473 of file synclink.c.

#define TCmd_SetEofEom 0xf000

Definition at line 478 of file synclink.c.

#define TCSR 0x34 /* Transmit Command/status Register */

Definition at line 366 of file synclink.c.

#define TCSR_PRESERVE 0x0F00

Definition at line 543 of file synclink.c.

#define TCSR_UNDERWAIT BIT11

Definition at line 545 of file synclink.c.

#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */

Definition at line 387 of file synclink.c.

#define TDMR 0x02 /* Transmit DMA mode Register */

Definition at line 386 of file synclink.c.

#define TDR 0x30 /* Transmit Data Register */

Definition at line 364 of file synclink.c.

#define TESTFRAMESIZE 40

#define TICR 0x36 /* Transmit Interrupt Control Register */

Definition at line 367 of file synclink.c.

#define TMCR 0x0e /* Test mode Control Register */

Definition at line 347 of file synclink.c.

#define TMDR 0x0c /* Test mode Data Register */

Definition at line 346 of file synclink.c.

#define TMR 0x32 /* Transmit mode Register */

Definition at line 365 of file synclink.c.

#define TRANSMIT_DATA BIT2

Definition at line 495 of file synclink.c.

#define TRANSMIT_STATUS BIT3

Definition at line 494 of file synclink.c.

#define TSR 0x38 /* Transmit Sync Register */

Definition at line 368 of file synclink.c.

#define TXSTATUS_ABORT_SENT BIT5

Definition at line 629 of file synclink.c.

#define TXSTATUS_ABORT_SENT BIT5

Definition at line 629 of file synclink.c.

#define TXSTATUS_ALL 0x00fa

Definition at line 555 of file synclink.c.

#define TXSTATUS_ALL_SENT BIT2

Definition at line 632 of file synclink.c.

#define TXSTATUS_ALL_SENT BIT2

Definition at line 632 of file synclink.c.

#define TXSTATUS_CRC_SENT BIT3

Definition at line 631 of file synclink.c.

#define TXSTATUS_CRC_SENT BIT3

Definition at line 631 of file synclink.c.

#define TXSTATUS_EOF BIT4

Definition at line 630 of file synclink.c.

#define TXSTATUS_EOF_SENT BIT4

Definition at line 549 of file synclink.c.

#define TXSTATUS_EOM_SENT BIT4

Definition at line 550 of file synclink.c.

#define TXSTATUS_FIFO_EMPTY BIT0

Definition at line 634 of file synclink.c.

#define TXSTATUS_FIFO_EMPTY BIT0

Definition at line 634 of file synclink.c.

#define TXSTATUS_IDLE_SENT BIT6

Definition at line 628 of file synclink.c.

#define TXSTATUS_IDLE_SENT BIT6

Definition at line 628 of file synclink.c.

#define TXSTATUS_PREAMBLE_SENT BIT7

Definition at line 627 of file synclink.c.

#define TXSTATUS_PREAMBLE_SENT BIT7

Definition at line 627 of file synclink.c.

#define TXSTATUS_UNDERRUN BIT1

Definition at line 633 of file synclink.c.

#define TXSTATUS_UNDERRUN BIT1

Definition at line 633 of file synclink.c.

#define usc_ClearIrqPendingBits	(	a,
		b
	)	usc_OutReg( (a), DCCR, 0x40 + (b) )

Definition at line 620 of file synclink.c.

#define usc_DisableDmaInterrupts	(	a,
		b
	)	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )

Definition at line 643 of file synclink.c.

#define usc_DisableInterrupts	(	a,
		b
	)	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )

Definition at line 611 of file synclink.c.

#define usc_DisableMasterIrqBit ( a ) usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )

Definition at line 617 of file synclink.c.

#define usc_DisablestatusIrqs	(	a,
		b
	)	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )

Definition at line 649 of file synclink.c.

#define usc_EnableDmaInterrupts	(	a,
		b
	)	usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) \| (b)) )

Definition at line 640 of file synclink.c.

#define usc_EnableInterrupts	(	a,
		b
	)	usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )

Definition at line 608 of file synclink.c.

#define usc_EnableMasterIrqBit ( a ) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )

Definition at line 614 of file synclink.c.

#define usc_EnableReceiver	(	a,
		b
	)	usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) \| (b)) )

Definition at line 663 of file synclink.c.

#define usc_EnableStatusIrqs	(	a,
		b
	)	usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) \| (b)) )

Definition at line 646 of file synclink.c.

#define usc_EnableTransmitter	(	a,
		b
	)	usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) \| (b)) )

Definition at line 661 of file synclink.c.

#define usc_RCmd	(	a,
		b
	)	usc_OutReg((a), RCSR, (b))

Definition at line 677 of file synclink.c.

#define usc_SetTransmitSyncChars	(	a,
		s0,
		s1
	)	usc_OutReg((a), TSR, (u16)(((u16)s0<<8)\|(u16)s1))

Definition at line 679 of file synclink.c.

#define usc_TCmd	(	a,
		b
	)	usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))

Definition at line 676 of file synclink.c.

#define usc_UnlatchIostatusBits	(	a,
		b
	)	usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))

Definition at line 576 of file synclink.c.

#define usc_UnlatchMiscstatusBits	(	a,
		b
	)	usc_OutReg((a),MISR,(u16)((b) & 0x000f))

Definition at line 577 of file synclink.c.

#define usc_UnlatchRxstatusBits	(	a,
		b
	)	usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )

Definition at line 518 of file synclink.c.

#define usc_UnlatchTxstatusBits	(	a,
		b
	)	usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )

Definition at line 556 of file synclink.c.

#define WAKEUP_CHARS 256

Definition at line 907 of file synclink.c.

Typedef Documentation

typedef struct _DMABUFFERENTRY DMABUFFERENTRY

typedef struct _DMABUFFERENTRY * DMAPBUFFERENTRY

typedef void(* isr_dispatch_func)(struct mgsl_struct *)

Definition at line 807 of file synclink.c.

Function Documentation

MODULE_DEVICE_TABLE	(	pci	,
		synclink_pci_tbl
	)

module_exit ( synclink_exit )

module_init ( synclink_init )

MODULE_LICENSE ( "GPL" )

module_param	(	break_on_load	,
		bool	,
		0
	)

module_param	(	ttymajor	,
		int	,
		0
	)

module_param	(	debug_level	,
		int	,
		0
	)

module_param_array	(	io	,
		int	,
		NULL	,
		0
	)

module_param_array	(	irq	,
		int	,
		NULL	,
		0
	)

module_param_array	(	dma	,
		int	,
		NULL	,
		0
	)

module_param_array	(	maxframe	,
		int	,
		NULL	,
		0
	)

module_param_array	(	txdmabufs	,
		int	,
		NULL	,
		0
	)

module_param_array	(	txholdbufs	,
		int	,
		NULL	,
		0
	)

void usc_ClearIrqPendingBits	(	struct mgsl_struct *	info,
		u16	IrqMask
	)

void usc_DisableInterrupts	(	struct mgsl_struct *	info,
		u16	IrqMask
	)

void usc_DisableMasterIrqBit ( struct mgsl_struct * info )

void usc_EnableInterrupts	(	struct mgsl_struct *	info,
		u16	IrqMask
	)

void usc_EnableMasterIrqBit ( struct mgsl_struct * info )

void usc_RCmd	(	struct mgsl_struct *	info,
		u16	Cmd
	)

void usc_TCmd	(	struct mgsl_struct *	info,
		u16	Cmd
	)

Data Structures

Macros

Typedefs

Functions

Macro Definition Documentation

Typedef Documentation

Function Documentation