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mISDNinfineon.c File Reference
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/mISDNhw.h>
#include <linux/slab.h>
#include "ipac.h"

Go to the source code of this file.

Data Structures

struct  inf_cinfo
 
struct  _ioaddr
 
struct  _iohandle
 
struct  inf_hw
 

Macros

#define INFINEON_REV   "1.0"
 
#define PCI_SUBVENDOR_HST_SAPHIR3   0x52
 
#define PCI_SUBVENDOR_SEDLBAUER_PCI   0x53
 
#define PCI_SUB_ID_SEDLBAUER   0x01
 
#define DIVA_HSCX_PORT   0x00
 
#define DIVA_HSCX_ALE   0x04
 
#define DIVA_ISAC_PORT   0x08
 
#define DIVA_ISAC_ALE   0x0C
 
#define DIVA_PCI_CTRL   0x10
 
#define DIVA_IRQ_BIT   0x01
 
#define DIVA_RESET_BIT   0x08
 
#define DIVA_EEPROM_CLK   0x40
 
#define DIVA_LED_A   0x10
 
#define DIVA_LED_B   0x20
 
#define DIVA_IRQ_CLR   0x80
 
#define PITA_ICR_REG   0x00
 
#define PITA_INT0_STATUS   0x02
 
#define PITA_MISC_REG   0x1c
 
#define PITA_PARA_SOFTRESET   0x01000000
 
#define PITA_SER_SOFTRESET   0x02000000
 
#define PITA_PARA_MPX_MODE   0x04000000
 
#define PITA_INT0_ENABLE   0x00020000
 
#define TIGER_RESET_ADDR   0x00
 
#define TIGER_EXTERN_RESET   0x01
 
#define TIGER_AUX_CTRL   0x02
 
#define TIGER_AUX_DATA   0x03
 
#define TIGER_AUX_IRQMASK   0x05
 
#define TIGER_AUX_STATUS   0x07
 
#define TIGER_IOMASK   0xdd /* 1 and 5 are inputs */
 
#define TIGER_IRQ_BIT   0x02
 
#define TIGER_IPAC_ALE   0xC0
 
#define TIGER_IPAC_PORT   0xC8
 
#define ELSA_IRQ_ADDR   0x4c
 
#define ELSA_IRQ_MASK   0x04
 
#define QS1000_IRQ_OFF   0x01
 
#define QS3000_IRQ_OFF   0x03
 
#define QS1000_IRQ_ON   0x41
 
#define QS3000_IRQ_ON   0x43
 
#define NICCY_ISAC_PORT   0x00
 
#define NICCY_HSCX_PORT   0x01
 
#define NICCY_ISAC_ALE   0x02
 
#define NICCY_HSCX_ALE   0x03
 
#define NICCY_IRQ_CTRL_REG   0x38
 
#define NICCY_IRQ_ENABLE   0x001f00
 
#define NICCY_IRQ_DISABLE   0xff0000
 
#define NICCY_IRQ_BIT   0x800000
 
#define SCT_PLX_IRQ_ADDR   0x4c
 
#define SCT_PLX_RESET_ADDR   0x50
 
#define SCT_PLX_IRQ_ENABLE   0x41
 
#define SCT_PLX_RESET_BIT   0x04
 
#define GAZEL_IPAC_DATA_PORT   0x04
 
#define GAZEL_CNTRL   0x50
 
#define GAZEL_RESET   0x04
 
#define GAZEL_RESET_9050   0x40000000
 
#define GAZEL_INCSR   0x4C
 
#define GAZEL_ISAC_EN   0x08
 
#define GAZEL_INT_ISAC   0x20
 
#define GAZEL_HSCX_EN   0x01
 
#define GAZEL_INT_HSCX   0x04
 
#define GAZEL_PCI_EN   0x40
 
#define GAZEL_IPAC_EN   0x03
 

Enumerations

enum  inf_types {
  INF_NONE, INF_DIVA20, INF_DIVA20U, INF_DIVA201,
  INF_DIVA202, INF_SPEEDWIN, INF_SAPHIR3, INF_QS1000,
  INF_QS3000, INF_NICCY, INF_SCT_1, INF_SCT_2,
  INF_SCT_3, INF_SCT_4, INF_GAZEL_R685, INF_GAZEL_R753
}
 
enum  addr_mode { AM_NONE = 0, AM_IO, AM_MEMIO, AM_IND_IO }
 

Functions

 MODULE_DEVICE_TABLE (pci, infineon_ids)
 
 MODULE_AUTHOR ("Karsten Keil")
 
 MODULE_LICENSE ("GPL v2")
 
 MODULE_VERSION (INFINEON_REV)
 
 module_param_call (debug, set_debug, param_get_uint,&debug, S_IRUGO|S_IWUSR)
 
 MODULE_PARM_DESC (debug,"infineon debug mask")
 
 module_param (irqloops, uint, S_IRUGO|S_IWUSR)
 
 MODULE_PARM_DESC (irqloops,"infineon maximal irqloops (default 4)")
 
 module_init (infineon_init)
 
 module_exit (infineon_cleanup)
 

Macro Definition Documentation

#define DIVA_EEPROM_CLK   0x40

Definition at line 163 of file mISDNinfineon.c.

#define DIVA_HSCX_ALE   0x04

Definition at line 155 of file mISDNinfineon.c.

#define DIVA_HSCX_PORT   0x00

Definition at line 154 of file mISDNinfineon.c.

#define DIVA_IRQ_BIT   0x01

Definition at line 161 of file mISDNinfineon.c.

#define DIVA_IRQ_CLR   0x80

Definition at line 166 of file mISDNinfineon.c.

#define DIVA_ISAC_ALE   0x0C

Definition at line 157 of file mISDNinfineon.c.

#define DIVA_ISAC_PORT   0x08

Definition at line 156 of file mISDNinfineon.c.

#define DIVA_LED_A   0x10

Definition at line 164 of file mISDNinfineon.c.

#define DIVA_LED_B   0x20

Definition at line 165 of file mISDNinfineon.c.

#define DIVA_PCI_CTRL   0x10

Definition at line 158 of file mISDNinfineon.c.

#define DIVA_RESET_BIT   0x08

Definition at line 162 of file mISDNinfineon.c.

#define ELSA_IRQ_ADDR   0x4c

Definition at line 195 of file mISDNinfineon.c.

#define ELSA_IRQ_MASK   0x04

Definition at line 196 of file mISDNinfineon.c.

#define GAZEL_CNTRL   0x50

Definition at line 223 of file mISDNinfineon.c.

#define GAZEL_HSCX_EN   0x01

Definition at line 229 of file mISDNinfineon.c.

#define GAZEL_INCSR   0x4C

Definition at line 226 of file mISDNinfineon.c.

#define GAZEL_INT_HSCX   0x04

Definition at line 230 of file mISDNinfineon.c.

#define GAZEL_INT_ISAC   0x20

Definition at line 228 of file mISDNinfineon.c.

#define GAZEL_IPAC_DATA_PORT   0x04

Definition at line 221 of file mISDNinfineon.c.

#define GAZEL_IPAC_EN   0x03

Definition at line 232 of file mISDNinfineon.c.

#define GAZEL_ISAC_EN   0x08

Definition at line 227 of file mISDNinfineon.c.

#define GAZEL_PCI_EN   0x40

Definition at line 231 of file mISDNinfineon.c.

#define GAZEL_RESET   0x04

Definition at line 224 of file mISDNinfineon.c.

#define GAZEL_RESET_9050   0x40000000

Definition at line 225 of file mISDNinfineon.c.

#define INFINEON_REV   "1.0"

Definition at line 49 of file mISDNinfineon.c.

#define NICCY_HSCX_ALE   0x03

Definition at line 206 of file mISDNinfineon.c.

#define NICCY_HSCX_PORT   0x01

Definition at line 204 of file mISDNinfineon.c.

#define NICCY_IRQ_BIT   0x800000

Definition at line 211 of file mISDNinfineon.c.

#define NICCY_IRQ_CTRL_REG   0x38

Definition at line 208 of file mISDNinfineon.c.

#define NICCY_IRQ_DISABLE   0xff0000

Definition at line 210 of file mISDNinfineon.c.

#define NICCY_IRQ_ENABLE   0x001f00

Definition at line 209 of file mISDNinfineon.c.

#define NICCY_ISAC_ALE   0x02

Definition at line 205 of file mISDNinfineon.c.

#define NICCY_ISAC_PORT   0x00

Definition at line 203 of file mISDNinfineon.c.

#define PCI_SUB_ID_SEDLBAUER   0x01

Definition at line 126 of file mISDNinfineon.c.

#define PCI_SUBVENDOR_HST_SAPHIR3   0x52

Definition at line 124 of file mISDNinfineon.c.

#define PCI_SUBVENDOR_SEDLBAUER_PCI   0x53

Definition at line 125 of file mISDNinfineon.c.

#define PITA_ICR_REG   0x00

Definition at line 170 of file mISDNinfineon.c.

#define PITA_INT0_ENABLE   0x00020000

Definition at line 177 of file mISDNinfineon.c.

#define PITA_INT0_STATUS   0x02

Definition at line 171 of file mISDNinfineon.c.

#define PITA_MISC_REG   0x1c

Definition at line 173 of file mISDNinfineon.c.

#define PITA_PARA_MPX_MODE   0x04000000

Definition at line 176 of file mISDNinfineon.c.

#define PITA_PARA_SOFTRESET   0x01000000

Definition at line 174 of file mISDNinfineon.c.

#define PITA_SER_SOFTRESET   0x02000000

Definition at line 175 of file mISDNinfineon.c.

#define QS1000_IRQ_OFF   0x01

Definition at line 197 of file mISDNinfineon.c.

#define QS1000_IRQ_ON   0x41

Definition at line 199 of file mISDNinfineon.c.

#define QS3000_IRQ_OFF   0x03

Definition at line 198 of file mISDNinfineon.c.

#define QS3000_IRQ_ON   0x43

Definition at line 200 of file mISDNinfineon.c.

#define SCT_PLX_IRQ_ADDR   0x4c

Definition at line 215 of file mISDNinfineon.c.

#define SCT_PLX_IRQ_ENABLE   0x41

Definition at line 217 of file mISDNinfineon.c.

#define SCT_PLX_RESET_ADDR   0x50

Definition at line 216 of file mISDNinfineon.c.

#define SCT_PLX_RESET_BIT   0x04

Definition at line 218 of file mISDNinfineon.c.

#define TIGER_AUX_CTRL   0x02

Definition at line 182 of file mISDNinfineon.c.

#define TIGER_AUX_DATA   0x03

Definition at line 183 of file mISDNinfineon.c.

#define TIGER_AUX_IRQMASK   0x05

Definition at line 184 of file mISDNinfineon.c.

#define TIGER_AUX_STATUS   0x07

Definition at line 185 of file mISDNinfineon.c.

#define TIGER_EXTERN_RESET   0x01

Definition at line 181 of file mISDNinfineon.c.

#define TIGER_IOMASK   0xdd /* 1 and 5 are inputs */

Definition at line 188 of file mISDNinfineon.c.

#define TIGER_IPAC_ALE   0xC0

Definition at line 191 of file mISDNinfineon.c.

#define TIGER_IPAC_PORT   0xC8

Definition at line 192 of file mISDNinfineon.c.

#define TIGER_IRQ_BIT   0x02

Definition at line 189 of file mISDNinfineon.c.

#define TIGER_RESET_ADDR   0x00

Definition at line 180 of file mISDNinfineon.c.

Enumeration Type Documentation

enum addr_mode
Enumerator:
AM_NONE 
AM_IO 
AM_MEMIO 
AM_IND_IO 

Definition at line 74 of file mISDNinfineon.c.

enum inf_types
Enumerator:
INF_NONE 
INF_DIVA20 
INF_DIVA20U 
INF_DIVA201 
INF_DIVA202 
INF_SPEEDWIN 
INF_SAPHIR3 
INF_QS1000 
INF_QS3000 
INF_NICCY 
INF_SCT_1 
INF_SCT_2 
INF_SCT_3 
INF_SCT_4 
INF_GAZEL_R685 
INF_GAZEL_R753 

Definition at line 55 of file mISDNinfineon.c.

Function Documentation

MODULE_AUTHOR ( "Karsten Keil"  )
MODULE_DEVICE_TABLE ( pci  ,
infineon_ids   
)
module_exit ( infineon_cleanup  )
module_init ( infineon_init  )
MODULE_LICENSE ( "GPL v2 )
module_param ( irqloops  ,
uint  ,
S_IRUGO S_IWUSR 
)
module_param_call ( debug  ,
set_debug  ,
param_get_uint  ,
debug,
S_IRUGO S_IWUSR 
)
MODULE_PARM_DESC ( debug  ,
"infineon debug mask  
)
MODULE_PARM_DESC ( irqloops  ,
"infineon maximal irqloops (default 4)"   
)
MODULE_VERSION ( INFINEON_REV  )