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| int | iop_listen (uint, uint, void(*handler)(struct iop_msg *), const char *) |
| |
| int | iop_send_message (uint, uint, void *, uint, __u8 *, void(*)(struct iop_msg *)) |
| |
| void | iop_complete_message (struct iop_msg *) |
| |
| void | iop_upload_code (uint, __u8 *, uint, __u16) |
| |
| void | iop_download_code (uint, __u8 *, uint, __u16) |
| |
| __u8 * | iop_compare_code (uint, __u8 *, uint, __u16) |
| |
| void | iop_register_interrupts (void) |
| |
| #define IOP_ADDR_ALIVE 0x031F |
| #define IOP_ADDR_MAX_RECV_CHAN 0x0300 |
| #define IOP_ADDR_MAX_SEND_CHAN 0x0200 |
| #define IOP_ADDR_PATCH_CTRL 0x021F |
| #define IOP_ADDR_RECV_MSG 0x0320 |
| #define IOP_ADDR_RECV_STATE 0x0301 |
| #define IOP_ADDR_SEND_MSG 0x0220 |
| #define IOP_ADDR_SEND_STATE 0x0201 |
| #define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */ |
| #define IOP_BYPASS 0x01 /* bypass-mode hardware access */ |
| #define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */ |
| #define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */ |
| #define IOP_INT0 0x10 /* intr priority from IOP to host */ |
| #define IOP_INT1 0x20 /* intr priority from IOP to host */ |
| #define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */ |
| #define IOP_MSG_IDLE 0 /* idle */ |
| #define IOP_MSG_NEW 1 /* new message sent */ |
| #define IOP_MSG_RCVD 2 /* message received; processing */ |
| #define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */ |
| #define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */ |
| #define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */ |
| #define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */ |
| #define IOP_RUN 0x04 /* set to 0 to reset IOP chip */ |
| #define ISM_IOP_BASE_IIFX (0x50F12000) |
| #define ISM_IOP_BASE_QUADRA (0x50F1E000) |
| #define SCC_IOP_BASE_IIFX (0x50F04000) |
| #define SCC_IOP_BASE_QUADRA (0x50F0C000) |
1.8.2