iop_sw_mpu_defs.h File Reference

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Data Structures
struct	reg_iop_sw_mpu_rw_sw_cfg_owner
struct	reg_iop_sw_mpu_rw_mc_ctrl
struct	reg_iop_sw_mpu_rw_mc_data
struct	reg_iop_sw_mpu_r_mc_stat
struct	reg_iop_sw_mpu_rw_bus_clr_mask
struct	reg_iop_sw_mpu_rw_bus_set_mask
struct	reg_iop_sw_mpu_rw_bus_oe_clr_mask
struct	reg_iop_sw_mpu_rw_bus_oe_set_mask
struct	reg_iop_sw_mpu_rw_gio_clr_mask
struct	reg_iop_sw_mpu_rw_gio_set_mask
struct	reg_iop_sw_mpu_rw_gio_oe_clr_mask
struct	reg_iop_sw_mpu_rw_gio_oe_set_mask
struct	reg_iop_sw_mpu_rw_cpu_intr
struct	reg_iop_sw_mpu_r_cpu_intr
struct	reg_iop_sw_mpu_rw_intr_grp0_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp0
struct	reg_iop_sw_mpu_r_intr_grp0
struct	reg_iop_sw_mpu_r_masked_intr_grp0
struct	reg_iop_sw_mpu_rw_intr_grp1_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp1
struct	reg_iop_sw_mpu_r_intr_grp1
struct	reg_iop_sw_mpu_r_masked_intr_grp1
struct	reg_iop_sw_mpu_rw_intr_grp2_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp2
struct	reg_iop_sw_mpu_r_intr_grp2
struct	reg_iop_sw_mpu_r_masked_intr_grp2
struct	reg_iop_sw_mpu_rw_intr_grp3_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp3
struct	reg_iop_sw_mpu_r_intr_grp3
struct	reg_iop_sw_mpu_r_masked_intr_grp3

Macros
#define	REG_RD(scope, inst, reg)
#define	REG_WR(scope, inst, reg, val)
#define	REG_RD_VECT(scope, inst, reg, index)
#define	REG_WR_VECT(scope, inst, reg, index, val)
#define	REG_RD_INT(scope, inst, reg)   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_WR_INT(scope, inst, reg, val)   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#define	REG_RD_INT_VECT(scope, inst, reg, index)
#define	REG_WR_INT_VECT(scope, inst, reg, index, val)
#define	REG_TYPE_CONV(type, orgtype, val)   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#define	reg_page_size   8192
#define	REG_ADDR(scope, inst, reg)   ( (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_ADDR_VECT(scope, inst, reg, index)
#define	REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0
#define	REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0
#define	REG_RD_ADDR_iop_sw_mpu_r_spu_trace   4
#define	REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace   8
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl   12
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl   12
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_data   16
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_data   16
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_addr   20
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_addr   20
#define	REG_RD_ADDR_iop_sw_mpu_rs_mc_data   24
#define	REG_RD_ADDR_iop_sw_mpu_r_mc_data   28
#define	REG_RD_ADDR_iop_sw_mpu_r_mc_stat   32
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask   36
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask   36
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask   40
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask   40
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask   44
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask   44
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask   48
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask   48
#define	REG_RD_ADDR_iop_sw_mpu_r_bus_in   52
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask   56
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask   56
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask   60
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask   60
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   64
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   64
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   68
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   68
#define	REG_RD_ADDR_iop_sw_mpu_r_gio_in   72
#define	REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr   76
#define	REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr   76
#define	REG_RD_ADDR_iop_sw_mpu_r_cpu_intr   80
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask   84
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask   84
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0   88
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0   88
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp0   92
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0   96
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask   100
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask   100
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1   104
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1   104
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp1   108
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1   112
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask   116
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask   116
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2   120
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2   120
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp2   124
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2   128
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask   132
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask   132
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3   136
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3   136
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp3   140
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3   144

Typedefs
typedef unsigned int	reg_iop_sw_mpu_r_spu_trace
typedef unsigned int	reg_iop_sw_mpu_r_spu_fsm_trace
typedef unsigned int	reg_iop_sw_mpu_rw_mc_addr
typedef unsigned int	reg_iop_sw_mpu_rs_mc_data
typedef unsigned int	reg_iop_sw_mpu_r_mc_data
typedef unsigned int	reg_iop_sw_mpu_r_bus_in
typedef unsigned int	reg_iop_sw_mpu_r_gio_in

Enumerations
enum	{   regk_iop_sw_mpu_copy = 0x00000000, regk_iop_sw_mpu_cpu = 0x00000000, regk_iop_sw_mpu_mpu = 0x00000001, regk_iop_sw_mpu_no = 0x00000000,   regk_iop_sw_mpu_nop = 0x00000000, regk_iop_sw_mpu_rd = 0x00000002, regk_iop_sw_mpu_reg_copy = 0x00000001, regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,   regk_iop_sw_mpu_set = 0x00000001, regk_iop_sw_mpu_spu = 0x00000002, regk_iop_sw_mpu_wr = 0x00000003, regk_iop_sw_mpu_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(		scope,
			inst,
			reg
	)		( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 72 of file iop_sw_mpu_defs.h.

#define REG_ADDR_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )

Definition at line 77 of file iop_sw_mpu_defs.h.

#define reg_page_size   8192

Definition at line 68 of file iop_sw_mpu_defs.h.

#define REG_RD	(		scope,
			inst,
			reg
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 15 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_bus_in   52

Definition at line 187 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr   80

Definition at line 294 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_gio_in   72

Definition at line 219 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0   92

Definition at line 353 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1   108

Definition at line 434 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2   124

Definition at line 515 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3   140

Definition at line 596 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0   96

Definition at line 375 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1   112

Definition at line 456 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2   128

Definition at line 537 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3   144

Definition at line 618 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_mc_data   28

Definition at line 129 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat   32

Definition at line 141 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace   8

Definition at line 98 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace   4

Definition at line 94 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data   24

Definition at line 125 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0   88

Definition at line 330 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1   104

Definition at line 411 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2   120

Definition at line 492 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3   136

Definition at line 573 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask   36

Definition at line 150 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask   44

Definition at line 171 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask   48

Definition at line 182 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask   40

Definition at line 160 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr   76

Definition at line 256 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask   56

Definition at line 193 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   64

Definition at line 207 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   68

Definition at line 214 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask   60

Definition at line 200 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask   84

Definition at line 316 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask   100

Definition at line 397 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask   116

Definition at line 478 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask   132

Definition at line 559 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr   20

Definition at line 120 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl   12

Definition at line 108 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data   16

Definition at line 115 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0

Definition at line 89 of file iop_sw_mpu_defs.h.

#define REG_RD_INT	(		scope,
			inst,
			reg
	)		REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 41 of file iop_sw_mpu_defs.h.

#define REG_RD_INT_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 51 of file iop_sw_mpu_defs.h.

#define REG_RD_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 27 of file iop_sw_mpu_defs.h.

#define REG_TYPE_CONV	(		type,
			orgtype,
			val
	)		( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 63 of file iop_sw_mpu_defs.h.

#define REG_WR	(		scope,
			inst,
			reg,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 21 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0   88

Definition at line 331 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1   104

Definition at line 412 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2   120

Definition at line 493 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3   136

Definition at line 574 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask   36

Definition at line 151 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask   44

Definition at line 172 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask   48

Definition at line 183 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask   40

Definition at line 161 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr   76

Definition at line 257 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask   56

Definition at line 194 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   64

Definition at line 208 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   68

Definition at line 215 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask   60

Definition at line 201 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask   84

Definition at line 317 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask   100

Definition at line 398 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask   116

Definition at line 479 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask   132

Definition at line 560 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr   20

Definition at line 121 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl   12

Definition at line 109 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data   16

Definition at line 116 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0

Definition at line 90 of file iop_sw_mpu_defs.h.

#define REG_WR_INT	(		scope,
			inst,
			reg,
			val
	)		REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 46 of file iop_sw_mpu_defs.h.

#define REG_WR_INT_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 57 of file iop_sw_mpu_defs.h.

#define REG_WR_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 34 of file iop_sw_mpu_defs.h.

Typedef Documentation

typedef unsigned int reg_iop_sw_mpu_r_bus_in

Definition at line 186 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_gio_in

Definition at line 218 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_mc_data

Definition at line 128 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace

Definition at line 97 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_spu_trace

Definition at line 93 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_rs_mc_data

Definition at line 124 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_rw_mc_addr

Definition at line 119 of file iop_sw_mpu_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_mpu_copy
regk_iop_sw_mpu_cpu
regk_iop_sw_mpu_mpu
regk_iop_sw_mpu_no
regk_iop_sw_mpu_nop
regk_iop_sw_mpu_rd
regk_iop_sw_mpu_reg_copy
regk_iop_sw_mpu_rw_bus_clr_mask_default
regk_iop_sw_mpu_rw_bus_oe_clr_mask_default
regk_iop_sw_mpu_rw_bus_oe_set_mask_default
regk_iop_sw_mpu_rw_bus_set_mask_default
regk_iop_sw_mpu_rw_gio_clr_mask_default
regk_iop_sw_mpu_rw_gio_oe_clr_mask_default
regk_iop_sw_mpu_rw_gio_oe_set_mask_default
regk_iop_sw_mpu_rw_gio_set_mask_default
regk_iop_sw_mpu_rw_intr_grp0_mask_default
regk_iop_sw_mpu_rw_intr_grp1_mask_default
regk_iop_sw_mpu_rw_intr_grp2_mask_default
regk_iop_sw_mpu_rw_intr_grp3_mask_default
regk_iop_sw_mpu_rw_sw_cfg_owner_default
regk_iop_sw_mpu_set
regk_iop_sw_mpu_spu
regk_iop_sw_mpu_wr
regk_iop_sw_mpu_yes

Definition at line 622 of file iop_sw_mpu_defs.h.