iop_sw_spu_defs.h File Reference

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Data Structures
struct	reg_iop_sw_spu_rw_mc_ctrl
struct	reg_iop_sw_spu_rw_mc_data
struct	reg_iop_sw_spu_r_mc_stat
struct	reg_iop_sw_spu_rw_bus_clr_mask
struct	reg_iop_sw_spu_rw_bus_set_mask
struct	reg_iop_sw_spu_rw_bus_oe_clr_mask
struct	reg_iop_sw_spu_rw_bus_oe_set_mask
struct	reg_iop_sw_spu_rw_gio_clr_mask
struct	reg_iop_sw_spu_rw_gio_set_mask
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask
struct	reg_iop_sw_spu_rw_gio_oe_set_mask
struct	reg_iop_sw_spu_rw_bus_clr_mask_lo
struct	reg_iop_sw_spu_rw_bus_clr_mask_hi
struct	reg_iop_sw_spu_rw_bus_set_mask_lo
struct	reg_iop_sw_spu_rw_bus_set_mask_hi
struct	reg_iop_sw_spu_rw_gio_clr_mask_lo
struct	reg_iop_sw_spu_rw_gio_clr_mask_hi
struct	reg_iop_sw_spu_rw_gio_set_mask_lo
struct	reg_iop_sw_spu_rw_gio_set_mask_hi
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask_lo
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask_hi
struct	reg_iop_sw_spu_rw_gio_oe_set_mask_lo
struct	reg_iop_sw_spu_rw_gio_oe_set_mask_hi
struct	reg_iop_sw_spu_rw_cpu_intr
struct	reg_iop_sw_spu_r_cpu_intr
struct	reg_iop_sw_spu_r_hw_intr
struct	reg_iop_sw_spu_rw_mpu_intr
struct	reg_iop_sw_spu_r_mpu_intr

Macros
#define	REG_RD(scope, inst, reg)
#define	REG_WR(scope, inst, reg, val)
#define	REG_RD_VECT(scope, inst, reg, index)
#define	REG_WR_VECT(scope, inst, reg, index, val)
#define	REG_RD_INT(scope, inst, reg)   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_WR_INT(scope, inst, reg, val)   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#define	REG_RD_INT_VECT(scope, inst, reg, index)
#define	REG_WR_INT_VECT(scope, inst, reg, index, val)
#define	REG_TYPE_CONV(type, orgtype, val)   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#define	reg_page_size   8192
#define	REG_ADDR(scope, inst, reg)   ( (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_ADDR_VECT(scope, inst, reg, index)
#define	REG_RD_ADDR_iop_sw_spu_r_mpu_trace   0
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl   4
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl   4
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_data   8
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_data   8
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_addr   12
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_addr   12
#define	REG_RD_ADDR_iop_sw_spu_rs_mc_data   16
#define	REG_RD_ADDR_iop_sw_spu_r_mc_data   20
#define	REG_RD_ADDR_iop_sw_spu_r_mc_stat   24
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask   28
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask   28
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask   32
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask   32
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask   36
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask   36
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask   40
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask   40
#define	REG_RD_ADDR_iop_sw_spu_r_bus_in   44
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask   48
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask   48
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask   52
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask   52
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   56
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   56
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask   60
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask   60
#define	REG_RD_ADDR_iop_sw_spu_r_gio_in   64
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo   68
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo   68
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi   72
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi   72
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo   76
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo   76
#define	REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi   80
#define	REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi   80
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   84
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   84
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   88
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   88
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo   92
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo   92
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi   96
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi   96
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   100
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   100
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   104
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   104
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   108
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   108
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   112
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   112
#define	REG_RD_ADDR_iop_sw_spu_rw_cpu_intr   116
#define	REG_WR_ADDR_iop_sw_spu_rw_cpu_intr   116
#define	REG_RD_ADDR_iop_sw_spu_r_cpu_intr   120
#define	REG_RD_ADDR_iop_sw_spu_r_hw_intr   124
#define	REG_RD_ADDR_iop_sw_spu_rw_mpu_intr   128
#define	REG_WR_ADDR_iop_sw_spu_rw_mpu_intr   128
#define	REG_RD_ADDR_iop_sw_spu_r_mpu_intr   132

Typedefs
typedef unsigned int	reg_iop_sw_spu_r_mpu_trace
typedef unsigned int	reg_iop_sw_spu_rw_mc_addr
typedef unsigned int	reg_iop_sw_spu_rs_mc_data
typedef unsigned int	reg_iop_sw_spu_r_mc_data
typedef unsigned int	reg_iop_sw_spu_r_bus_in
typedef unsigned int	reg_iop_sw_spu_r_gio_in

Enumerations
enum	{   regk_iop_sw_spu_copy = 0x00000000, regk_iop_sw_spu_no = 0x00000000, regk_iop_sw_spu_nop = 0x00000000, regk_iop_sw_spu_rd = 0x00000002,   regk_iop_sw_spu_reg_copy = 0x00000001, regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,   regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,   regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_spu_set = 0x00000001, regk_iop_sw_spu_wr = 0x00000003, regk_iop_sw_spu_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(		scope,
			inst,
			reg
	)		( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 72 of file iop_sw_spu_defs.h.

#define REG_ADDR_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )

Definition at line 77 of file iop_sw_spu_defs.h.

#define reg_page_size   8192

Definition at line 68 of file iop_sw_spu_defs.h.

#define REG_RD	(		scope,
			inst,
			reg
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 15 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_bus_in   44

Definition at line 175 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr   120

Definition at line 352 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_gio_in   64

Definition at line 207 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_hw_intr   124

Definition at line 374 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mc_data   20

Definition at line 117 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mc_stat   24

Definition at line 129 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr   132

Definition at line 419 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace   0

Definition at line 86 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rs_mc_data   16

Definition at line 113 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask   28

Definition at line 138 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi   72

Definition at line 224 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo   68

Definition at line 215 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask   36

Definition at line 159 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask   40

Definition at line 170 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask   32

Definition at line 148 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi   80

Definition at line 242 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo   76

Definition at line 233 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr   116

Definition at line 329 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask   48

Definition at line 181 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   88

Definition at line 258 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   84

Definition at line 250 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   56

Definition at line 195 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   104

Definition at line 290 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   100

Definition at line 282 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask   60

Definition at line 202 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   112

Definition at line 306 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   108

Definition at line 298 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask   52

Definition at line 188 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi   96

Definition at line 274 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo   92

Definition at line 266 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr   12

Definition at line 108 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl   4

Definition at line 96 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_data   8

Definition at line 103 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr   128

Definition at line 396 of file iop_sw_spu_defs.h.

#define REG_RD_INT	(		scope,
			inst,
			reg
	)		REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 41 of file iop_sw_spu_defs.h.

#define REG_RD_INT_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 51 of file iop_sw_spu_defs.h.

#define REG_RD_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 27 of file iop_sw_spu_defs.h.

#define REG_TYPE_CONV	(		type,
			orgtype,
			val
	)		( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 63 of file iop_sw_spu_defs.h.

#define REG_WR	(		scope,
			inst,
			reg,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 21 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask   28

Definition at line 139 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi   72

Definition at line 225 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo   68

Definition at line 216 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask   36

Definition at line 160 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask   40

Definition at line 171 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask   32

Definition at line 149 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi   80

Definition at line 243 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo   76

Definition at line 234 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr   116

Definition at line 330 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask   48

Definition at line 182 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   88

Definition at line 259 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   84

Definition at line 251 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   56

Definition at line 196 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   104

Definition at line 291 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   100

Definition at line 283 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask   60

Definition at line 203 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   112

Definition at line 307 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   108

Definition at line 299 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask   52

Definition at line 189 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi   96

Definition at line 275 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo   92

Definition at line 267 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr   12

Definition at line 109 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl   4

Definition at line 97 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_data   8

Definition at line 104 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr   128

Definition at line 397 of file iop_sw_spu_defs.h.

#define REG_WR_INT	(		scope,
			inst,
			reg,
			val
	)		REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 46 of file iop_sw_spu_defs.h.

#define REG_WR_INT_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 57 of file iop_sw_spu_defs.h.

#define REG_WR_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 34 of file iop_sw_spu_defs.h.

Typedef Documentation

typedef unsigned int reg_iop_sw_spu_r_bus_in

Definition at line 174 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_gio_in

Definition at line 206 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_mc_data

Definition at line 116 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_mpu_trace

Definition at line 85 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_rs_mc_data

Definition at line 112 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_rw_mc_addr

Definition at line 107 of file iop_sw_spu_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_spu_copy
regk_iop_sw_spu_no
regk_iop_sw_spu_nop
regk_iop_sw_spu_rd
regk_iop_sw_spu_reg_copy
regk_iop_sw_spu_rw_bus_clr_mask_default
regk_iop_sw_spu_rw_bus_oe_clr_mask_default
regk_iop_sw_spu_rw_bus_oe_set_mask_default
regk_iop_sw_spu_rw_bus_set_mask_default
regk_iop_sw_spu_rw_gio_clr_mask_default
regk_iop_sw_spu_rw_gio_oe_clr_mask_default
regk_iop_sw_spu_rw_gio_oe_set_mask_default
regk_iop_sw_spu_rw_gio_set_mask_default
regk_iop_sw_spu_set
regk_iop_sw_spu_wr
regk_iop_sw_spu_yes

Definition at line 423 of file iop_sw_spu_defs.h.