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Macros
regs-lcd.h File Reference
#include <mach/bitfield.h>

Go to the source code of this file.

Macros

#define LCCR0   (0x000) /* LCD Controller Control Register 0 */
 
#define LCCR1   (0x004) /* LCD Controller Control Register 1 */
 
#define LCCR2   (0x008) /* LCD Controller Control Register 2 */
 
#define LCCR3   (0x00C) /* LCD Controller Control Register 3 */
 
#define LCCR4   (0x010) /* LCD Controller Control Register 4 */
 
#define LCCR5   (0x014) /* LCD Controller Control Register 5 */
 
#define LCSR   (0x038) /* LCD Controller Status Register 0 */
 
#define LCSR1   (0x034) /* LCD Controller Status Register 1 */
 
#define LIIDR   (0x03C) /* LCD Controller Interrupt ID Register */
 
#define TMEDRGBR   (0x040) /* TMED RGB Seed Register */
 
#define TMEDCR   (0x044) /* TMED Control Register */
 
#define FBR0   (0x020) /* DMA Channel 0 Frame Branch Register */
 
#define FBR1   (0x024) /* DMA Channel 1 Frame Branch Register */
 
#define FBR2   (0x028) /* DMA Channel 2 Frame Branch Register */
 
#define FBR3   (0x02C) /* DMA Channel 2 Frame Branch Register */
 
#define FBR4   (0x030) /* DMA Channel 2 Frame Branch Register */
 
#define FBR5   (0x110) /* DMA Channel 2 Frame Branch Register */
 
#define FBR6   (0x114) /* DMA Channel 2 Frame Branch Register */
 
#define OVL1C1   (0x050) /* Overlay 1 Control Register 1 */
 
#define OVL1C2   (0x060) /* Overlay 1 Control Register 2 */
 
#define OVL2C1   (0x070) /* Overlay 2 Control Register 1 */
 
#define OVL2C2   (0x080) /* Overlay 2 Control Register 2 */
 
#define CMDCR   (0x100) /* Command Control Register */
 
#define PRSR   (0x104) /* Panel Read Status Register */
 
#define LCCR3_BPP(x)   ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
 
#define LCCR3_PDFOR_0   (0 << 30)
 
#define LCCR3_PDFOR_1   (1 << 30)
 
#define LCCR3_PDFOR_2   (2 << 30)
 
#define LCCR3_PDFOR_3   (3 << 30)
 
#define LCCR4_PAL_FOR_0   (0 << 15)
 
#define LCCR4_PAL_FOR_1   (1 << 15)
 
#define LCCR4_PAL_FOR_2   (2 << 15)
 
#define LCCR4_PAL_FOR_3   (3 << 15)
 
#define LCCR4_PAL_FOR_MASK   (3 << 15)
 
#define FDADR0   (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
 
#define FDADR1   (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
 
#define FDADR2   (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
 
#define FDADR3   (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
 
#define FDADR4   (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
 
#define FDADR5   (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
 
#define FDADR6   (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
 
#define LCCR0_ENB   (1 << 0) /* LCD Controller enable */
 
#define LCCR0_CMS   (1 << 1) /* Color/Monochrome Display Select */
 
#define LCCR0_Color   (LCCR0_CMS*0) /* Color display */
 
#define LCCR0_Mono   (LCCR0_CMS*1) /* Monochrome display */
 
#define LCCR0_SDS   (1 << 2) /* Single/Dual Panel Display Select */
 
#define LCCR0_Sngl   (LCCR0_SDS*0) /* Single panel display */
 
#define LCCR0_Dual   (LCCR0_SDS*1) /* Dual panel display */
 
#define LCCR0_LDM   (1 << 3) /* LCD Disable Done Mask */
 
#define LCCR0_SFM   (1 << 4) /* Start of frame mask */
 
#define LCCR0_IUM   (1 << 5) /* Input FIFO underrun mask */
 
#define LCCR0_EFM   (1 << 6) /* End of Frame mask */
 
#define LCCR0_PAS   (1 << 7) /* Passive/Active display Select */
 
#define LCCR0_Pas   (LCCR0_PAS*0) /* Passive display (STN) */
 
#define LCCR0_Act   (LCCR0_PAS*1) /* Active display (TFT) */
 
#define LCCR0_DPD   (1 << 9) /* Double Pixel Data (monochrome) */
 
#define LCCR0_4PixMono   (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
 
#define LCCR0_8PixMono   (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
 
#define LCCR0_DIS   (1 << 10) /* LCD Disable */
 
#define LCCR0_QDM   (1 << 11) /* LCD Quick Disable mask */
 
#define LCCR0_PDD   (0xff << 12) /* Palette DMA request delay */
 
#define LCCR0_PDD_S   12
 
#define LCCR0_BM   (1 << 20) /* Branch mask */
 
#define LCCR0_OUM   (1 << 21) /* Output FIFO underrun mask */
 
#define LCCR0_LCDT   (1 << 22) /* LCD panel type */
 
#define LCCR0_RDSTM   (1 << 23) /* Read status interrupt mask */
 
#define LCCR0_CMDIM   (1 << 24) /* Command interrupt mask */
 
#define LCCR0_OUC   (1 << 25) /* Overlay Underlay control bit */
 
#define LCCR0_LDDALT   (1 << 26) /* LDD alternate mapping control */
 
#define LCCR1_PPL   Fld (10, 0) /* Pixels Per Line - 1 */
 
#define LCCR1_DisWdth(Pixel)   (((Pixel) - 1) << FShft (LCCR1_PPL))
 
#define LCCR1_HSW   Fld (6, 10) /* Horizontal Synchronization */
 
#define LCCR1_HorSnchWdth(Tpix)   (((Tpix) - 1) << FShft (LCCR1_HSW))
 
#define LCCR1_ELW   Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
 
#define LCCR1_EndLnDel(Tpix)   (((Tpix) - 1) << FShft (LCCR1_ELW))
 
#define LCCR1_BLW   Fld (8, 24) /* Beginning-of-Line pixel clock */
 
#define LCCR1_BegLnDel(Tpix)   (((Tpix) - 1) << FShft (LCCR1_BLW))
 
#define LCCR2_LPP   Fld (10, 0) /* Line Per Panel - 1 */
 
#define LCCR2_DisHght(Line)   (((Line) - 1) << FShft (LCCR2_LPP))
 
#define LCCR2_VSW   Fld (6, 10) /* Vertical Synchronization pulse - 1 */
 
#define LCCR2_VrtSnchWdth(Tln)   (((Tln) - 1) << FShft (LCCR2_VSW))
 
#define LCCR2_EFW   Fld (8, 16) /* End-of-Frame line clock Wait */
 
#define LCCR2_EndFrmDel(Tln)   ((Tln) << FShft (LCCR2_EFW))
 
#define LCCR2_BFW   Fld (8, 24) /* Beginning-of-Frame line clock */
 
#define LCCR2_BegFrmDel(Tln)   ((Tln) << FShft (LCCR2_BFW))
 
#define LCCR3_API   (0xf << 16) /* AC Bias pin trasitions per interrupt */
 
#define LCCR3_API_S   16
 
#define LCCR3_VSP   (1 << 20) /* vertical sync polarity */
 
#define LCCR3_HSP   (1 << 21) /* horizontal sync polarity */
 
#define LCCR3_PCP   (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
 
#define LCCR3_PixRsEdg   (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
 
#define LCCR3_PixFlEdg   (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
 
#define LCCR3_OEP   (1 << 23) /* Output Enable Polarity */
 
#define LCCR3_OutEnH   (LCCR3_OEP*0) /* Output Enable active High */
 
#define LCCR3_OutEnL   (LCCR3_OEP*1) /* Output Enable active Low */
 
#define LCCR3_DPC   (1 << 27) /* double pixel clock mode */
 
#define LCCR3_PCD   Fld (8, 0) /* Pixel Clock Divisor */
 
#define LCCR3_PixClkDiv(Div)   (((Div) << FShft (LCCR3_PCD)))
 
#define LCCR3_ACB   Fld (8, 8) /* AC Bias */
 
#define LCCR3_Acb(Acb)   (((Acb) << FShft (LCCR3_ACB)))
 
#define LCCR3_HorSnchH   (LCCR3_HSP*0) /* HSP Active High */
 
#define LCCR3_HorSnchL   (LCCR3_HSP*1) /* HSP Active Low */
 
#define LCCR3_VrtSnchH   (LCCR3_VSP*0) /* VSP Active High */
 
#define LCCR3_VrtSnchL   (LCCR3_VSP*1) /* VSP Active Low */
 
#define LCCR5_IUM(x)   (1 << ((x) + 23)) /* input underrun mask */
 
#define LCCR5_BSM(x)   (1 << ((x) + 15)) /* branch mask */
 
#define LCCR5_EOFM(x)   (1 << ((x) + 7)) /* end of frame mask */
 
#define LCCR5_SOFM(x)   (1 << ((x) + 0)) /* start of frame mask */
 
#define LCSR_LDD   (1 << 0) /* LCD Disable Done */
 
#define LCSR_SOF   (1 << 1) /* Start of frame */
 
#define LCSR_BER   (1 << 2) /* Bus error */
 
#define LCSR_ABC   (1 << 3) /* AC Bias count */
 
#define LCSR_IUL   (1 << 4) /* input FIFO underrun Lower panel */
 
#define LCSR_IUU   (1 << 5) /* input FIFO underrun Upper panel */
 
#define LCSR_OU   (1 << 6) /* output FIFO underrun */
 
#define LCSR_QD   (1 << 7) /* quick disable */
 
#define LCSR_EOF   (1 << 8) /* end of frame */
 
#define LCSR_BS   (1 << 9) /* branch status */
 
#define LCSR_SINT   (1 << 10) /* subsequent interrupt */
 
#define LCSR_RD_ST   (1 << 11) /* read status */
 
#define LCSR_CMD_INT   (1 << 12) /* command interrupt */
 
#define LCSR1_IU(x)   (1 << ((x) + 23)) /* Input FIFO underrun */
 
#define LCSR1_BS(x)   (1 << ((x) + 15)) /* Branch Status */
 
#define LCSR1_EOF(x)   (1 << ((x) + 7)) /* End of Frame Status */
 
#define LCSR1_SOF(x)   (1 << ((x) - 1)) /* Start of Frame Status */
 
#define LDCMD_PAL   (1 << 26) /* instructs DMA to load palette buffer */
 
#define OVLxC1_PPL(x)   ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */
 
#define OVLxC1_LPO(x)   ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
 
#define OVLxC1_BPP(x)   (((x) & 0xf) << 20) /* Bits Per Pixel */
 
#define OVLxC1_OEN   (1 << 31) /* Enable bit for Overlay */
 
#define OVLxC2_XPOS(x)   (((x) & 0x3ff) << 0) /* Horizontal Position */
 
#define OVLxC2_YPOS(x)   (((x) & 0x3ff) << 10) /* Vertical Position */
 
#define OVL2C2_PFOR(x)   (((x) & 0x7) << 20) /* Pixel Format */
 
#define PRSR_DATA(x)   ((x) & 0xff) /* Panel Data */
 
#define PRSR_A0   (1 << 8) /* Read Data Source */
 
#define PRSR_ST_OK   (1 << 9) /* Status OK */
 
#define PRSR_CON_NT   (1 << 10) /* Continue to Next Command */
 
#define SMART_CMD_A0   (0x1 << 8)
 
#define SMART_CMD_READ_STATUS_REG   (0x0 << 9)
 
#define SMART_CMD_READ_FRAME_BUFFER   ((0x0 << 9) | SMART_CMD_A0)
 
#define SMART_CMD_WRITE_COMMAND   (0x1 << 9)
 
#define SMART_CMD_WRITE_DATA   ((0x1 << 9) | SMART_CMD_A0)
 
#define SMART_CMD_WRITE_FRAME   ((0x2 << 9) | SMART_CMD_A0)
 
#define SMART_CMD_WAIT_FOR_VSYNC   (0x3 << 9)
 
#define SMART_CMD_NOOP   (0x4 << 9)
 
#define SMART_CMD_INTERRUPT   (0x5 << 9)
 
#define SMART_CMD(x)   (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
 
#define SMART_DAT(x)   (SMART_CMD_WRITE_DATA | ((x) & 0xff))
 
#define SMART_CMD_DELAY   (0x6 << 9)
 
#define SMART_DELAY(ms)   (SMART_CMD_DELAY | ((ms) & 0xff))
 

Macro Definition Documentation

#define CMDCR   (0x100) /* Command Control Register */

Definition at line 34 of file regs-lcd.h.

#define FBR0   (0x020) /* DMA Channel 0 Frame Branch Register */

Definition at line 21 of file regs-lcd.h.

#define FBR1   (0x024) /* DMA Channel 1 Frame Branch Register */

Definition at line 22 of file regs-lcd.h.

#define FBR2   (0x028) /* DMA Channel 2 Frame Branch Register */

Definition at line 23 of file regs-lcd.h.

#define FBR3   (0x02C) /* DMA Channel 2 Frame Branch Register */

Definition at line 24 of file regs-lcd.h.

#define FBR4   (0x030) /* DMA Channel 2 Frame Branch Register */

Definition at line 25 of file regs-lcd.h.

#define FBR5   (0x110) /* DMA Channel 2 Frame Branch Register */

Definition at line 26 of file regs-lcd.h.

#define FBR6   (0x114) /* DMA Channel 2 Frame Branch Register */

Definition at line 27 of file regs-lcd.h.

#define FDADR0   (0x200) /* DMA Channel 0 Frame Descriptor Address Register */

Definition at line 50 of file regs-lcd.h.

#define FDADR1   (0x210) /* DMA Channel 1 Frame Descriptor Address Register */

Definition at line 51 of file regs-lcd.h.

#define FDADR2   (0x220) /* DMA Channel 2 Frame Descriptor Address Register */

Definition at line 52 of file regs-lcd.h.

#define FDADR3   (0x230) /* DMA Channel 3 Frame Descriptor Address Register */

Definition at line 53 of file regs-lcd.h.

#define FDADR4   (0x240) /* DMA Channel 4 Frame Descriptor Address Register */

Definition at line 54 of file regs-lcd.h.

#define FDADR5   (0x250) /* DMA Channel 5 Frame Descriptor Address Register */

Definition at line 55 of file regs-lcd.h.

#define FDADR6   (0x260) /* DMA Channel 6 Frame Descriptor Address Register */

Definition at line 56 of file regs-lcd.h.

#define LCCR0   (0x000) /* LCD Controller Control Register 0 */

Definition at line 9 of file regs-lcd.h.

#define LCCR0_4PixMono   (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */

Definition at line 74 of file regs-lcd.h.

#define LCCR0_8PixMono   (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */

Definition at line 75 of file regs-lcd.h.

#define LCCR0_Act   (LCCR0_PAS*1) /* Active display (TFT) */

Definition at line 72 of file regs-lcd.h.

#define LCCR0_BM   (1 << 20) /* Branch mask */

Definition at line 80 of file regs-lcd.h.

#define LCCR0_CMDIM   (1 << 24) /* Command interrupt mask */

Definition at line 84 of file regs-lcd.h.

#define LCCR0_CMS   (1 << 1) /* Color/Monochrome Display Select */

Definition at line 59 of file regs-lcd.h.

#define LCCR0_Color   (LCCR0_CMS*0) /* Color display */

Definition at line 60 of file regs-lcd.h.

#define LCCR0_DIS   (1 << 10) /* LCD Disable */

Definition at line 76 of file regs-lcd.h.

#define LCCR0_DPD   (1 << 9) /* Double Pixel Data (monochrome) */

Definition at line 73 of file regs-lcd.h.

#define LCCR0_Dual   (LCCR0_SDS*1) /* Dual panel display */

Definition at line 64 of file regs-lcd.h.

#define LCCR0_EFM   (1 << 6) /* End of Frame mask */

Definition at line 69 of file regs-lcd.h.

#define LCCR0_ENB   (1 << 0) /* LCD Controller enable */

Definition at line 58 of file regs-lcd.h.

#define LCCR0_IUM   (1 << 5) /* Input FIFO underrun mask */

Definition at line 68 of file regs-lcd.h.

#define LCCR0_LCDT   (1 << 22) /* LCD panel type */

Definition at line 82 of file regs-lcd.h.

#define LCCR0_LDDALT   (1 << 26) /* LDD alternate mapping control */

Definition at line 86 of file regs-lcd.h.

#define LCCR0_LDM   (1 << 3) /* LCD Disable Done Mask */

Definition at line 66 of file regs-lcd.h.

#define LCCR0_Mono   (LCCR0_CMS*1) /* Monochrome display */

Definition at line 61 of file regs-lcd.h.

#define LCCR0_OUC   (1 << 25) /* Overlay Underlay control bit */

Definition at line 85 of file regs-lcd.h.

#define LCCR0_OUM   (1 << 21) /* Output FIFO underrun mask */

Definition at line 81 of file regs-lcd.h.

#define LCCR0_PAS   (1 << 7) /* Passive/Active display Select */

Definition at line 70 of file regs-lcd.h.

#define LCCR0_Pas   (LCCR0_PAS*0) /* Passive display (STN) */

Definition at line 71 of file regs-lcd.h.

#define LCCR0_PDD   (0xff << 12) /* Palette DMA request delay */

Definition at line 78 of file regs-lcd.h.

#define LCCR0_PDD_S   12

Definition at line 79 of file regs-lcd.h.

#define LCCR0_QDM   (1 << 11) /* LCD Quick Disable mask */

Definition at line 77 of file regs-lcd.h.

#define LCCR0_RDSTM   (1 << 23) /* Read status interrupt mask */

Definition at line 83 of file regs-lcd.h.

#define LCCR0_SDS   (1 << 2) /* Single/Dual Panel Display Select */

Definition at line 62 of file regs-lcd.h.

#define LCCR0_SFM   (1 << 4) /* Start of frame mask */

Definition at line 67 of file regs-lcd.h.

#define LCCR0_Sngl   (LCCR0_SDS*0) /* Single panel display */

Definition at line 63 of file regs-lcd.h.

#define LCCR1   (0x004) /* LCD Controller Control Register 1 */

Definition at line 10 of file regs-lcd.h.

#define LCCR1_BegLnDel (   Tpix)    (((Tpix) - 1) << FShft (LCCR1_BLW))

Definition at line 98 of file regs-lcd.h.

#define LCCR1_BLW   Fld (8, 24) /* Beginning-of-Line pixel clock */

Definition at line 97 of file regs-lcd.h.

#define LCCR1_DisWdth (   Pixel)    (((Pixel) - 1) << FShft (LCCR1_PPL))

Definition at line 89 of file regs-lcd.h.

#define LCCR1_ELW   Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */

Definition at line 94 of file regs-lcd.h.

#define LCCR1_EndLnDel (   Tpix)    (((Tpix) - 1) << FShft (LCCR1_ELW))

Definition at line 95 of file regs-lcd.h.

#define LCCR1_HorSnchWdth (   Tpix)    (((Tpix) - 1) << FShft (LCCR1_HSW))

Definition at line 92 of file regs-lcd.h.

#define LCCR1_HSW   Fld (6, 10) /* Horizontal Synchronization */

Definition at line 91 of file regs-lcd.h.

#define LCCR1_PPL   Fld (10, 0) /* Pixels Per Line - 1 */

Definition at line 88 of file regs-lcd.h.

#define LCCR2   (0x008) /* LCD Controller Control Register 2 */

Definition at line 11 of file regs-lcd.h.

#define LCCR2_BegFrmDel (   Tln)    ((Tln) << FShft (LCCR2_BFW))

Definition at line 110 of file regs-lcd.h.

#define LCCR2_BFW   Fld (8, 24) /* Beginning-of-Frame line clock */

Definition at line 109 of file regs-lcd.h.

#define LCCR2_DisHght (   Line)    (((Line) - 1) << FShft (LCCR2_LPP))

Definition at line 101 of file regs-lcd.h.

#define LCCR2_EFW   Fld (8, 16) /* End-of-Frame line clock Wait */

Definition at line 106 of file regs-lcd.h.

#define LCCR2_EndFrmDel (   Tln)    ((Tln) << FShft (LCCR2_EFW))

Definition at line 107 of file regs-lcd.h.

#define LCCR2_LPP   Fld (10, 0) /* Line Per Panel - 1 */

Definition at line 100 of file regs-lcd.h.

#define LCCR2_VrtSnchWdth (   Tln)    (((Tln) - 1) << FShft (LCCR2_VSW))

Definition at line 104 of file regs-lcd.h.

#define LCCR2_VSW   Fld (6, 10) /* Vertical Synchronization pulse - 1 */

Definition at line 103 of file regs-lcd.h.

#define LCCR3   (0x00C) /* LCD Controller Control Register 3 */

Definition at line 12 of file regs-lcd.h.

#define LCCR3_ACB   Fld (8, 8) /* AC Bias */

Definition at line 128 of file regs-lcd.h.

#define LCCR3_Acb (   Acb)    (((Acb) << FShft (LCCR3_ACB)))

Definition at line 129 of file regs-lcd.h.

#define LCCR3_API   (0xf << 16) /* AC Bias pin trasitions per interrupt */

Definition at line 112 of file regs-lcd.h.

#define LCCR3_API_S   16

Definition at line 113 of file regs-lcd.h.

#define LCCR3_BPP (   x)    ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))

Definition at line 37 of file regs-lcd.h.

#define LCCR3_DPC   (1 << 27) /* double pixel clock mode */

Definition at line 124 of file regs-lcd.h.

#define LCCR3_HorSnchH   (LCCR3_HSP*0) /* HSP Active High */

Definition at line 131 of file regs-lcd.h.

#define LCCR3_HorSnchL   (LCCR3_HSP*1) /* HSP Active Low */

Definition at line 132 of file regs-lcd.h.

#define LCCR3_HSP   (1 << 21) /* horizontal sync polarity */

Definition at line 115 of file regs-lcd.h.

#define LCCR3_OEP   (1 << 23) /* Output Enable Polarity */

Definition at line 120 of file regs-lcd.h.

#define LCCR3_OutEnH   (LCCR3_OEP*0) /* Output Enable active High */

Definition at line 121 of file regs-lcd.h.

#define LCCR3_OutEnL   (LCCR3_OEP*1) /* Output Enable active Low */

Definition at line 122 of file regs-lcd.h.

#define LCCR3_PCD   Fld (8, 0) /* Pixel Clock Divisor */

Definition at line 125 of file regs-lcd.h.

#define LCCR3_PCP   (1 << 22) /* Pixel Clock Polarity (L_PCLK) */

Definition at line 116 of file regs-lcd.h.

#define LCCR3_PDFOR_0   (0 << 30)

Definition at line 39 of file regs-lcd.h.

#define LCCR3_PDFOR_1   (1 << 30)

Definition at line 40 of file regs-lcd.h.

#define LCCR3_PDFOR_2   (2 << 30)

Definition at line 41 of file regs-lcd.h.

#define LCCR3_PDFOR_3   (3 << 30)

Definition at line 42 of file regs-lcd.h.

#define LCCR3_PixClkDiv (   Div)    (((Div) << FShft (LCCR3_PCD)))

Definition at line 126 of file regs-lcd.h.

#define LCCR3_PixFlEdg   (LCCR3_PCP*1) /* Pixel clock Falling-Edge */

Definition at line 118 of file regs-lcd.h.

#define LCCR3_PixRsEdg   (LCCR3_PCP*0) /* Pixel clock Rising-Edge */

Definition at line 117 of file regs-lcd.h.

#define LCCR3_VrtSnchH   (LCCR3_VSP*0) /* VSP Active High */

Definition at line 134 of file regs-lcd.h.

#define LCCR3_VrtSnchL   (LCCR3_VSP*1) /* VSP Active Low */

Definition at line 135 of file regs-lcd.h.

#define LCCR3_VSP   (1 << 20) /* vertical sync polarity */

Definition at line 114 of file regs-lcd.h.

#define LCCR4   (0x010) /* LCD Controller Control Register 4 */

Definition at line 13 of file regs-lcd.h.

#define LCCR4_PAL_FOR_0   (0 << 15)

Definition at line 44 of file regs-lcd.h.

#define LCCR4_PAL_FOR_1   (1 << 15)

Definition at line 45 of file regs-lcd.h.

#define LCCR4_PAL_FOR_2   (2 << 15)

Definition at line 46 of file regs-lcd.h.

#define LCCR4_PAL_FOR_3   (3 << 15)

Definition at line 47 of file regs-lcd.h.

#define LCCR4_PAL_FOR_MASK   (3 << 15)

Definition at line 48 of file regs-lcd.h.

#define LCCR5   (0x014) /* LCD Controller Control Register 5 */

Definition at line 14 of file regs-lcd.h.

#define LCCR5_BSM (   x)    (1 << ((x) + 15)) /* branch mask */

Definition at line 138 of file regs-lcd.h.

#define LCCR5_EOFM (   x)    (1 << ((x) + 7)) /* end of frame mask */

Definition at line 139 of file regs-lcd.h.

#define LCCR5_IUM (   x)    (1 << ((x) + 23)) /* input underrun mask */

Definition at line 137 of file regs-lcd.h.

#define LCCR5_SOFM (   x)    (1 << ((x) + 0)) /* start of frame mask */

Definition at line 140 of file regs-lcd.h.

#define LCSR   (0x038) /* LCD Controller Status Register 0 */

Definition at line 15 of file regs-lcd.h.

#define LCSR1   (0x034) /* LCD Controller Status Register 1 */

Definition at line 16 of file regs-lcd.h.

#define LCSR1_BS (   x)    (1 << ((x) + 15)) /* Branch Status */

Definition at line 157 of file regs-lcd.h.

#define LCSR1_EOF (   x)    (1 << ((x) + 7)) /* End of Frame Status */

Definition at line 158 of file regs-lcd.h.

#define LCSR1_IU (   x)    (1 << ((x) + 23)) /* Input FIFO underrun */

Definition at line 156 of file regs-lcd.h.

#define LCSR1_SOF (   x)    (1 << ((x) - 1)) /* Start of Frame Status */

Definition at line 159 of file regs-lcd.h.

#define LCSR_ABC   (1 << 3) /* AC Bias count */

Definition at line 145 of file regs-lcd.h.

#define LCSR_BER   (1 << 2) /* Bus error */

Definition at line 144 of file regs-lcd.h.

#define LCSR_BS   (1 << 9) /* branch status */

Definition at line 151 of file regs-lcd.h.

#define LCSR_CMD_INT   (1 << 12) /* command interrupt */

Definition at line 154 of file regs-lcd.h.

#define LCSR_EOF   (1 << 8) /* end of frame */

Definition at line 150 of file regs-lcd.h.

#define LCSR_IUL   (1 << 4) /* input FIFO underrun Lower panel */

Definition at line 146 of file regs-lcd.h.

#define LCSR_IUU   (1 << 5) /* input FIFO underrun Upper panel */

Definition at line 147 of file regs-lcd.h.

#define LCSR_LDD   (1 << 0) /* LCD Disable Done */

Definition at line 142 of file regs-lcd.h.

#define LCSR_OU   (1 << 6) /* output FIFO underrun */

Definition at line 148 of file regs-lcd.h.

#define LCSR_QD   (1 << 7) /* quick disable */

Definition at line 149 of file regs-lcd.h.

#define LCSR_RD_ST   (1 << 11) /* read status */

Definition at line 153 of file regs-lcd.h.

#define LCSR_SINT   (1 << 10) /* subsequent interrupt */

Definition at line 152 of file regs-lcd.h.

#define LCSR_SOF   (1 << 1) /* Start of frame */

Definition at line 143 of file regs-lcd.h.

#define LDCMD_PAL   (1 << 26) /* instructs DMA to load palette buffer */

Definition at line 161 of file regs-lcd.h.

#define LIIDR   (0x03C) /* LCD Controller Interrupt ID Register */

Definition at line 17 of file regs-lcd.h.

#define OVL1C1   (0x050) /* Overlay 1 Control Register 1 */

Definition at line 29 of file regs-lcd.h.

#define OVL1C2   (0x060) /* Overlay 1 Control Register 2 */

Definition at line 30 of file regs-lcd.h.

#define OVL2C1   (0x070) /* Overlay 2 Control Register 1 */

Definition at line 31 of file regs-lcd.h.

#define OVL2C2   (0x080) /* Overlay 2 Control Register 2 */

Definition at line 32 of file regs-lcd.h.

#define OVL2C2_PFOR (   x)    (((x) & 0x7) << 20) /* Pixel Format */

Definition at line 170 of file regs-lcd.h.

#define OVLxC1_BPP (   x)    (((x) & 0xf) << 20) /* Bits Per Pixel */

Definition at line 166 of file regs-lcd.h.

#define OVLxC1_LPO (   x)    ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */

Definition at line 165 of file regs-lcd.h.

#define OVLxC1_OEN   (1 << 31) /* Enable bit for Overlay */

Definition at line 167 of file regs-lcd.h.

#define OVLxC1_PPL (   x)    ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */

Definition at line 164 of file regs-lcd.h.

#define OVLxC2_XPOS (   x)    (((x) & 0x3ff) << 0) /* Horizontal Position */

Definition at line 168 of file regs-lcd.h.

#define OVLxC2_YPOS (   x)    (((x) & 0x3ff) << 10) /* Vertical Position */

Definition at line 169 of file regs-lcd.h.

#define PRSR   (0x104) /* Panel Read Status Register */

Definition at line 35 of file regs-lcd.h.

#define PRSR_A0   (1 << 8) /* Read Data Source */

Definition at line 174 of file regs-lcd.h.

#define PRSR_CON_NT   (1 << 10) /* Continue to Next Command */

Definition at line 176 of file regs-lcd.h.

#define PRSR_DATA (   x)    ((x) & 0xff) /* Panel Data */

Definition at line 173 of file regs-lcd.h.

#define PRSR_ST_OK   (1 << 9) /* Status OK */

Definition at line 175 of file regs-lcd.h.

#define SMART_CMD (   x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))

Definition at line 188 of file regs-lcd.h.

#define SMART_CMD_A0   (0x1 << 8)

Definition at line 178 of file regs-lcd.h.

#define SMART_CMD_DELAY   (0x6 << 9)

Definition at line 195 of file regs-lcd.h.

#define SMART_CMD_INTERRUPT   (0x5 << 9)

Definition at line 186 of file regs-lcd.h.

#define SMART_CMD_NOOP   (0x4 << 9)

Definition at line 185 of file regs-lcd.h.

#define SMART_CMD_READ_FRAME_BUFFER   ((0x0 << 9) | SMART_CMD_A0)

Definition at line 180 of file regs-lcd.h.

#define SMART_CMD_READ_STATUS_REG   (0x0 << 9)

Definition at line 179 of file regs-lcd.h.

#define SMART_CMD_WAIT_FOR_VSYNC   (0x3 << 9)

Definition at line 184 of file regs-lcd.h.

#define SMART_CMD_WRITE_COMMAND   (0x1 << 9)

Definition at line 181 of file regs-lcd.h.

#define SMART_CMD_WRITE_DATA   ((0x1 << 9) | SMART_CMD_A0)

Definition at line 182 of file regs-lcd.h.

#define SMART_CMD_WRITE_FRAME   ((0x2 << 9) | SMART_CMD_A0)

Definition at line 183 of file regs-lcd.h.

#define SMART_DAT (   x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))

Definition at line 189 of file regs-lcd.h.

#define SMART_DELAY (   ms)    (SMART_CMD_DELAY | ((ms) & 0xff))

Definition at line 196 of file regs-lcd.h.

#define TMEDCR   (0x044) /* TMED Control Register */

Definition at line 19 of file regs-lcd.h.

#define TMEDRGBR   (0x040) /* TMED RGB Seed Register */

Definition at line 18 of file regs-lcd.h.