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mach64_ct.c
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1 
2 /*
3  * ATI Mach64 CT/VT/GT/LT Support
4  */
5 
6 #include <linux/fb.h>
7 #include <linux/delay.h>
8 #include <asm/io.h>
9 #include <video/mach64.h>
10 #include "atyfb.h"
11 #ifdef CONFIG_PPC
12 #include <asm/machdep.h>
13 #endif
14 
15 #undef DEBUG
16 
17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
21 
22 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
23 {
24  u8 res;
25 
26  /* write addr byte */
27  aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
28  /* read the register value */
29  res = aty_ld_8(CLOCK_CNTL_DATA, par);
30  return res;
31 }
32 
33 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
34 {
35  /* write addr byte */
36  aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
37  /* write the register value */
38  aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
39  aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
40 }
41 
42 /*
43  * by Daniel Mantione
45  *
46  *
47  * ATI Mach64 CT clock synthesis description.
48  *
49  * All clocks on the Mach64 can be calculated using the same principle:
50  *
51  * XTALIN * x * FB_DIV
52  * CLK = ----------------------
53  * PLL_REF_DIV * POST_DIV
54  *
55  * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
56  * PLL_REF_DIV can be set by the user, but is the same for all clocks.
57  * FB_DIV can be set by the user for each clock individually, it should be set
58  * between 128 and 255, the chip will generate a bad clock signal for too low
59  * values.
60  * x depends on the type of clock; usually it is 2, but for the MCLK it can also
61  * be set to 4.
62  * POST_DIV can be set by the user for each clock individually, Possible values
63  * are 1,2,4,8 and for some clocks other values are available too.
64  * CLK is of course the clock speed that is generated.
65  *
66  * The Mach64 has these clocks:
67  *
68  * MCLK The clock rate of the chip
69  * XCLK The clock rate of the on-chip memory
70  * VCLK0 First pixel clock of first CRT controller
71  * VCLK1 Second pixel clock of first CRT controller
72  * VCLK2 Third pixel clock of first CRT controller
73  * VCLK3 Fourth pixel clock of first CRT controller
74  * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
75  * V2CLK Pixel clock of the second CRT controller.
76  * SCLK Multi-purpose clock
77  *
78  * - MCLK and XCLK use the same FB_DIV
79  * - VCLK0 .. VCLK3 use the same FB_DIV
80  * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
81  * i.e. CRT monitor connected to laptop has different resolution than built
82  * in LCD monitor.
83  * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
84  * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT.
85  * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
86  * the Rage XL and the Rage Mobility
87  *
88  * SCLK can be used to:
89  * - Clock the chip instead of MCLK
90  * - Replace XTALIN with a user defined frequency
91  * - Generate the pixel clock for the LCD monitor (instead of VCLK)
92  */
93 
94  /*
95  * It can be quite hard to calculate XCLK and MCLK if they don't run at the
96  * same frequency. Luckily, until now all cards that need asynchrone clock
97  * speeds seem to have SCLK.
98  * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
99  */
100 
101 /* ------------------------------------------------------------------------- */
102 
103 /*
104  * PLL programming (Mach64 CT family)
105  *
106  *
107  * This procedure sets the display fifo. The display fifo is a buffer that
108  * contains data read from the video memory that waits to be processed by
109  * the CRT controller.
110  *
111  * On the more modern Mach64 variants, the chip doesn't calculate the
112  * interval after which the display fifo has to be reloaded from memory
113  * automatically, the driver has to do it instead.
114  */
115 
116 #define Maximum_DSP_PRECISION 7
117 static u8 postdividers[] = {1,2,4,8,3};
118 
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
120 {
121  u32 dsp_off, dsp_on, dsp_xclks;
122  u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
123  u8 vshift, xshift;
124  s8 dsp_precision;
125 
126  multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
127  divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
128 
129  ras_multiplier = pll->xclkmaxrasdelay;
130  ras_divider = 1;
131 
132  if (bpp>=8)
133  divider = divider * (bpp >> 2);
134 
135  vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
136 
137  if (bpp == 0)
138  vshift--; /* ... but only 32 bits in VGA mode. */
139 
140 #ifdef CONFIG_FB_ATY_GENERIC_LCD
141  if (pll->xres != 0) {
142  struct atyfb_par *par = (struct atyfb_par *) info->par;
143 
144  multiplier = multiplier * par->lcd_width;
145  divider = divider * pll->xres & ~7;
146 
147  ras_multiplier = ras_multiplier * par->lcd_width;
148  ras_divider = ras_divider * pll->xres & ~7;
149  }
150 #endif
151  /* If we don't do this, 32 bits for multiplier & divider won't be
152  enough in certain situations! */
153  while (((multiplier | divider) & 1) == 0) {
154  multiplier = multiplier >> 1;
155  divider = divider >> 1;
156  }
157 
158  /* Determine DSP precision first */
159  tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
160 
161  for (dsp_precision = -5; tmp; dsp_precision++)
162  tmp >>= 1;
163  if (dsp_precision < 0)
164  dsp_precision = 0;
165  else if (dsp_precision > Maximum_DSP_PRECISION)
166  dsp_precision = Maximum_DSP_PRECISION;
167 
168  xshift = 6 - dsp_precision;
169  vshift += xshift;
170 
171  /* Move on to dsp_off */
172  dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
173  (1 << (vshift - xshift));
174 
175 /* if (bpp == 0)
176  dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
177  else */
178  {
179  dsp_on = ((multiplier << vshift) + divider) / divider;
180  tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider;
181  if (dsp_on < tmp)
182  dsp_on = tmp;
183  dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
184  }
185 
186  /* Calculate rounding factor and apply it to dsp_on */
187  tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
188  dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
189 
190  if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) {
191  dsp_on = dsp_off - (multiplier << vshift) / divider;
192  dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
193  }
194 
195  /* Last but not least: dsp_xclks */
196  dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
197 
198  /* Get register values. */
199  pll->dsp_on_off = (dsp_on << 16) + dsp_off;
200  pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
201 #ifdef DEBUG
202  printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n",
203  __func__, pll->dsp_config, pll->dsp_on_off);
204 #endif
205  return 0;
206 }
207 
208 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
209 {
210  u32 q;
211  struct atyfb_par *par = (struct atyfb_par *) info->par;
212  int pllvclk;
213 
214  /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
215  q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
216  if (q < 16*8 || q > 255*8) {
217  printk(KERN_CRIT "atyfb: vclk out of range\n");
218  return -EINVAL;
219  } else {
220  pll->vclk_post_div = (q < 128*8);
221  pll->vclk_post_div += (q < 64*8);
222  pll->vclk_post_div += (q < 32*8);
223  }
224  pll->vclk_post_div_real = postdividers[pll->vclk_post_div];
225  // pll->vclk_post_div <<= 6;
226  pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
227  pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
228  (par->ref_clk_per * pll->pll_ref_div);
229 #ifdef DEBUG
230  printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
231  __func__, pllvclk, pllvclk / pll->vclk_post_div_real);
232 #endif
233  pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
234 
235  /* Set ECP (scaler/overlay clock) divider */
236  if (par->pll_limits.ecp_max) {
237  int ecp = pllvclk / pll->vclk_post_div_real;
238  int ecp_div = 0;
239 
240  while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
241  ecp >>= 1;
242  ecp_div++;
243  }
244  pll->pll_vclk_cntl |= ecp_div << 4;
245  }
246 
247  return 0;
248 }
249 
250 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
251 {
252  struct atyfb_par *par = (struct atyfb_par *) info->par;
253  int err;
254 
255  if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
256  return err;
257  if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
258  return err;
259  /*aty_calc_pll_ct(info, &pll->ct);*/
260  return 0;
261 }
262 
263 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
264 {
265  struct atyfb_par *par = (struct atyfb_par *) info->par;
266  u32 ret;
267  ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
268 #ifdef CONFIG_FB_ATY_GENERIC_LCD
269  if(pll->ct.xres > 0) {
270  ret *= par->lcd_width;
271  ret /= pll->ct.xres;
272  }
273 #endif
274 #ifdef DEBUG
275  printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret);
276 #endif
277  return ret;
278 }
279 
280 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
281 {
282  struct atyfb_par *par = (struct atyfb_par *) info->par;
283  u32 crtc_gen_cntl, lcd_gen_cntrl;
284  u8 tmp, tmp2;
285 
286  lcd_gen_cntrl = 0;
287 #ifdef DEBUG
288  printk("atyfb(%s): about to program:\n"
289  "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n",
290  __func__,
291  pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
292 
293  printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
294  __func__,
295  par->clk_wr_offset, pll->ct.vclk_fb_div,
296  pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
297 #endif
298 #ifdef CONFIG_FB_ATY_GENERIC_LCD
299  if (par->lcd_table != 0) {
300  /* turn off LCD */
301  lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
302  aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
303  }
304 #endif
306 
307  /* Temporarily switch to accelerator mode */
308  crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
309  if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
310  aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
311 
312  /* Reset VCLK generator */
313  aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
314 
315  /* Set post-divider */
316  tmp2 = par->clk_wr_offset << 1;
317  tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
318  tmp &= ~(0x03U << tmp2);
319  tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
320  aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
321 
322  /* Set extended post-divider */
323  tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
324  tmp &= ~(0x10U << par->clk_wr_offset);
325  tmp &= 0xF0U;
326  tmp |= pll->ct.pll_ext_cntl;
327  aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
328 
329  /* Set feedback divider */
330  tmp = VCLK0_FB_DIV + par->clk_wr_offset;
331  aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
332 
333  aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
334 
335  /* End VCLK generator reset */
336  aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
337  mdelay(5);
338 
339  aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
340  aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
341  mdelay(1);
342 
343  /* Restore mode register */
344  if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
345  aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
346 
347  if (M64_HAS(GTB_DSP)) {
348  u8 dll_cntl;
349 
350  if (M64_HAS(XL_DLL))
351  dll_cntl = 0x80;
352  else if (par->ram_type >= SDRAM)
353  dll_cntl = 0xa6;
354  else
355  dll_cntl = 0xa0;
356  aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
357  aty_st_pll_ct(VFC_CNTL, 0x1b, par);
358  aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
359  aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
360 
361  mdelay(10);
362  aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
363  mdelay(10);
364  aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
365  mdelay(10);
366  aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
367  }
368 #ifdef CONFIG_FB_ATY_GENERIC_LCD
369  if (par->lcd_table != 0) {
370  /* restore LCD */
371  aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
372  }
373 #endif
374 }
375 
376 static void __devinit aty_get_pll_ct(const struct fb_info *info,
377  union aty_pll *pll)
378 {
379  struct atyfb_par *par = (struct atyfb_par *) info->par;
380  u8 tmp, clock;
381 
382  clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
383  tmp = clock << 1;
384  pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
385 
386  pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
387  pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
388  pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
389  pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
390 
391  pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
392  pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
393 
394  if (M64_HAS(GTB_DSP)) {
395  pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
396  pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
397  }
398 }
399 
400 static int __devinit aty_init_pll_ct(const struct fb_info *info,
401  union aty_pll *pll)
402 {
403  struct atyfb_par *par = (struct atyfb_par *) info->par;
404  u8 mpost_div, xpost_div, sclk_post_div_real;
405  u32 q, memcntl, trp;
406  u32 dsp_config, dsp_on_off, vga_dsp_config, vga_dsp_on_off;
407 #ifdef DEBUG
408  int pllmclk, pllsclk;
409 #endif
410  pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
411  pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
412  pll->ct.xclk_ref_div = 1;
413  switch (pll->ct.xclk_post_div) {
414  case 0: case 1: case 2: case 3:
415  break;
416 
417  case 4:
418  pll->ct.xclk_ref_div = 3;
419  pll->ct.xclk_post_div = 0;
420  break;
421 
422  default:
423  printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
424  return -EINVAL;
425  }
426  pll->ct.mclk_fb_mult = 2;
427  if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
428  pll->ct.mclk_fb_mult = 4;
429  pll->ct.xclk_post_div -= 1;
430  }
431 
432 #ifdef DEBUG
433  printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n",
434  __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
435 #endif
436 
437  memcntl = aty_ld_le32(MEM_CNTL, par);
438  trp = (memcntl & 0x300) >> 8;
439 
440  pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
441  pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
442 
443  if (M64_HAS(FIFO_32)) {
444  pll->ct.fifo_size = 32;
445  } else {
446  pll->ct.fifo_size = 24;
447  pll->ct.xclkpagefaultdelay += 2;
448  pll->ct.xclkmaxrasdelay += 3;
449  }
450 
451  switch (par->ram_type) {
452  case DRAM:
453  if (info->fix.smem_len<=ONE_MB) {
454  pll->ct.dsp_loop_latency = 10;
455  } else {
456  pll->ct.dsp_loop_latency = 8;
457  pll->ct.xclkpagefaultdelay += 2;
458  }
459  break;
460  case EDO:
461  case PSEUDO_EDO:
462  if (info->fix.smem_len<=ONE_MB) {
463  pll->ct.dsp_loop_latency = 9;
464  } else {
465  pll->ct.dsp_loop_latency = 8;
466  pll->ct.xclkpagefaultdelay += 1;
467  }
468  break;
469  case SDRAM:
470  if (info->fix.smem_len<=ONE_MB) {
471  pll->ct.dsp_loop_latency = 11;
472  } else {
473  pll->ct.dsp_loop_latency = 10;
474  pll->ct.xclkpagefaultdelay += 1;
475  }
476  break;
477  case SGRAM:
478  pll->ct.dsp_loop_latency = 8;
479  pll->ct.xclkpagefaultdelay += 3;
480  break;
481  default:
482  pll->ct.dsp_loop_latency = 11;
483  pll->ct.xclkpagefaultdelay += 3;
484  break;
485  }
486 
487  if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
488  pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
489 
490  /* Allow BIOS to override */
491  dsp_config = aty_ld_le32(DSP_CONFIG, par);
492  dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
493  vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par);
494  vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par);
495 
496  if (dsp_config)
497  pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
498 #if 0
499  FIXME: is it relevant for us?
500  if ((!dsp_on_off && !M64_HAS(RESET_3D)) ||
501  ((dsp_on_off == vga_dsp_on_off) &&
502  (!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) {
503  vga_dsp_on_off &= VGA_DSP_OFF;
504  vga_dsp_config &= VGA_DSP_XCLKS_PER_QW;
505  if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24)
506  pll->ct.fifo_size = 32;
507  else
508  pll->ct.fifo_size = 24;
509  }
510 #endif
511  /* Exit if the user does not want us to tamper with the clock
512  rates of her chip. */
513  if (par->mclk_per == 0) {
514  u8 mclk_fb_div, pll_ext_cntl;
515  pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
516  pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
517  pll->ct.xclk_post_div_real = postdividers[pll_ext_cntl & 0x07];
518  mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
519  if (pll_ext_cntl & PLL_MFB_TIMES_4_2B)
520  mclk_fb_div <<= 1;
521  pll->ct.mclk_fb_div = mclk_fb_div;
522  return 0;
523  }
524 
525  pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
526 
527  /* FIXME: use the VTB/GTB /3 post divider if it's better suited */
528  q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
529  (pll->ct.mclk_fb_mult * par->xclk_per);
530 
531  if (q < 16*8 || q > 255*8) {
532  printk(KERN_CRIT "atxfb: xclk out of range\n");
533  return -EINVAL;
534  } else {
535  xpost_div = (q < 128*8);
536  xpost_div += (q < 64*8);
537  xpost_div += (q < 32*8);
538  }
539  pll->ct.xclk_post_div_real = postdividers[xpost_div];
540  pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
541 
542 #ifdef CONFIG_PPC
543  if (machine_is(powermac)) {
544  /* Override PLL_EXT_CNTL & 0x07. */
545  pll->ct.xclk_post_div = xpost_div;
546  pll->ct.xclk_ref_div = 1;
547  }
548 #endif
549 
550 #ifdef DEBUG
551  pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
552  (par->ref_clk_per * pll->ct.pll_ref_div);
553  printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n",
554  __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
555 #endif
556 
557  if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
558  pll->ct.pll_gen_cntl = OSC_EN;
559  else
560  pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
561 
562  if (M64_HAS(MAGIC_POSTDIV))
563  pll->ct.pll_ext_cntl = 0;
564  else
565  pll->ct.pll_ext_cntl = xpost_div;
566 
567  if (pll->ct.mclk_fb_mult == 4)
568  pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
569 
570  if (par->mclk_per == par->xclk_per) {
571  pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
572  } else {
573  /*
574  * The chip clock is not equal to the memory clock.
575  * Therefore we will use sclk to clock the chip.
576  */
577  pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
578 
579  q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
580  if (q < 16*8 || q > 255*8) {
581  printk(KERN_CRIT "atyfb: mclk out of range\n");
582  return -EINVAL;
583  } else {
584  mpost_div = (q < 128*8);
585  mpost_div += (q < 64*8);
586  mpost_div += (q < 32*8);
587  }
588  sclk_post_div_real = postdividers[mpost_div];
589  pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
590  pll->ct.spll_cntl2 = mpost_div << 4;
591 #ifdef DEBUG
592  pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
593  (par->ref_clk_per * pll->ct.pll_ref_div);
594  printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n",
595  __func__, pllsclk, pllsclk / sclk_post_div_real);
596 #endif
597  }
598 
599  /* Disable the extra precision pixel clock controls since we do not use them. */
600  pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
601  pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
602 
603  return 0;
604 }
605 
606 static void aty_resume_pll_ct(const struct fb_info *info,
607  union aty_pll *pll)
608 {
609  struct atyfb_par *par = info->par;
610 
611  if (par->mclk_per != par->xclk_per) {
612  /*
613  * This disables the sclk, crashes the computer as reported:
614  * aty_st_pll_ct(SPLL_CNTL2, 3, info);
615  *
616  * So it seems the sclk must be enabled before it is used;
617  * so PLL_GEN_CNTL must be programmed *after* the sclk.
618  */
619  aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
620  aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
621  /*
622  * SCLK has been started. Wait for the PLL to lock. 5 ms
623  * should be enough according to mach64 programmer's guide.
624  */
625  mdelay(5);
626  }
627 
628  aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
629  aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
630  aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
631  aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
632  aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);
633 }
634 
635 static int dummy(void)
636 {
637  return 0;
638 }
639 
640 const struct aty_dac_ops aty_dac_ct = {
641  .set_dac = (void *) dummy,
642 };
643 
644 const struct aty_pll_ops aty_pll_ct = {
645  .var_to_pll = aty_var_to_pll_ct,
646  .pll_to_var = aty_pll_to_var_ct,
647  .set_pll = aty_set_pll_ct,
648  .get_pll = aty_get_pll_ct,
649  .init_pll = aty_init_pll_ct,
650  .resume_pll = aty_resume_pll_ct,
651 };