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Linux Kernel
3.7.1
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#include <linux/pci.h>#include <linux/interrupt.h>#include <linux/ata.h>#include <linux/delay.h>#include <linux/hdreg.h>#include <linux/uaccess.h>#include <linux/random.h>#include <linux/smp.h>#include <linux/compat.h>#include <linux/fs.h>#include <linux/module.h>#include <linux/genhd.h>#include <linux/blkdev.h>#include <linux/bio.h>#include <linux/dma-mapping.h>#include <linux/idr.h>#include <linux/kthread.h>#include <../drivers/ata/ahci.h>#include <linux/export.h>#include <linux/debugfs.h>#include "mtip32xx.h"Go to the source code of this file.
Macros | |
| #define | HW_CMD_SLOT_SZ (MTIP_MAX_COMMAND_SLOTS * 32) |
| #define | HW_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (MTIP_MAX_SG * 16)) |
| #define | HW_CMD_TBL_AR_SZ (HW_CMD_TBL_SZ * MTIP_MAX_COMMAND_SLOTS) |
| #define | HW_PORT_PRIV_DMA_SZ (HW_CMD_SLOT_SZ + HW_CMD_TBL_AR_SZ + AHCI_RX_FIS_SZ) |
| #define | HOST_CAP_NZDMA (1 << 19) |
| #define | HOST_HSORG 0xFC |
| #define | HSORG_DISABLE_SLOTGRP_INTR (1<<24) |
| #define | HSORG_DISABLE_SLOTGRP_PXIS (1<<16) |
| #define | HSORG_HWREV 0xFF00 |
| #define | HSORG_STYLE 0x8 |
| #define | HSORG_SLOTGROUPS 0x7 |
| #define | PORT_COMMAND_ISSUE 0x38 |
| #define | PORT_SDBV 0x7C |
| #define | PORT_OFFSET 0x100 |
| #define | PORT_MEM_SIZE 0x80 |
| #define | PORT_IRQ_ERR |
| #define | PORT_IRQ_LEGACY (PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) |
| #define | PORT_IRQ_HANDLED |
| #define | DEF_PORT_IRQ (PORT_IRQ_ERR | PORT_IRQ_LEGACY | PORT_IRQ_SDB_FIS) |
| #define | MTIP_PRODUCT_UNKNOWN 0x00 |
| #define | MTIP_PRODUCT_ASICFPGA 0x11 |
Functions | |
| MODULE_DEVICE_TABLE (pci, mtip_pci_tbl) | |
| MODULE_AUTHOR ("Micron Technology, Inc") | |
| MODULE_DESCRIPTION ("Micron RealSSD PCIe Block Driver") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_VERSION (MTIP_DRV_VERSION) | |
| module_init (mtip_init) | |
| module_exit (mtip_exit) | |
| #define DEF_PORT_IRQ (PORT_IRQ_ERR | PORT_IRQ_LEGACY | PORT_IRQ_SDB_FIS) |
Definition at line 74 of file mtip32xx.c.
| #define HOST_CAP_NZDMA (1 << 19) |
Definition at line 49 of file mtip32xx.c.
| #define HOST_HSORG 0xFC |
Definition at line 50 of file mtip32xx.c.
| #define HSORG_DISABLE_SLOTGRP_INTR (1<<24) |
Definition at line 51 of file mtip32xx.c.
| #define HSORG_DISABLE_SLOTGRP_PXIS (1<<16) |
Definition at line 52 of file mtip32xx.c.
| #define HSORG_HWREV 0xFF00 |
Definition at line 53 of file mtip32xx.c.
| #define HSORG_SLOTGROUPS 0x7 |
Definition at line 55 of file mtip32xx.c.
| #define HSORG_STYLE 0x8 |
Definition at line 54 of file mtip32xx.c.
| #define HW_CMD_SLOT_SZ (MTIP_MAX_COMMAND_SLOTS * 32) |
Definition at line 43 of file mtip32xx.c.
| #define HW_CMD_TBL_AR_SZ (HW_CMD_TBL_SZ * MTIP_MAX_COMMAND_SLOTS) |
Definition at line 45 of file mtip32xx.c.
| #define HW_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (MTIP_MAX_SG * 16)) |
Definition at line 44 of file mtip32xx.c.
| #define HW_PORT_PRIV_DMA_SZ (HW_CMD_SLOT_SZ + HW_CMD_TBL_AR_SZ + AHCI_RX_FIS_SZ) |
Definition at line 46 of file mtip32xx.c.
| #define MTIP_PRODUCT_ASICFPGA 0x11 |
Definition at line 79 of file mtip32xx.c.
| #define MTIP_PRODUCT_UNKNOWN 0x00 |
Definition at line 78 of file mtip32xx.c.
| #define PORT_COMMAND_ISSUE 0x38 |
Definition at line 57 of file mtip32xx.c.
| #define PORT_IRQ_ERR |
Definition at line 63 of file mtip32xx.c.
| #define PORT_IRQ_HANDLED |
Definition at line 70 of file mtip32xx.c.
| #define PORT_IRQ_LEGACY (PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) |
Definition at line 68 of file mtip32xx.c.
| #define PORT_MEM_SIZE 0x80 |
Definition at line 61 of file mtip32xx.c.
| #define PORT_OFFSET 0x100 |
Definition at line 60 of file mtip32xx.c.
| #define PORT_SDBV 0x7C |
Definition at line 58 of file mtip32xx.c.
| MODULE_AUTHOR | ( | "Micron | Technology, |
| Inc" | |||
| ) |
| MODULE_DESCRIPTION | ( | "Micron RealSSD PCIe Block Driver" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| mtip_pci_tbl | |||
| ) |
| module_exit | ( | mtip_exit | ) |
| module_init | ( | mtip_init | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| MODULE_VERSION | ( | MTIP_DRV_VERSION | ) |
1.8.2