|
| #define | ATHEROS_VENDOR_ID 0x168c |
| |
| #define | AR5416_DEVID_PCI 0x0023 |
| |
| #define | AR5416_DEVID_PCIE 0x0024 |
| |
| #define | AR9160_DEVID_PCI 0x0027 |
| |
| #define | AR9280_DEVID_PCI 0x0029 |
| |
| #define | AR9280_DEVID_PCIE 0x002a |
| |
| #define | AR9285_DEVID_PCIE 0x002b |
| |
| #define | AR2427_DEVID_PCIE 0x002c |
| |
| #define | AR9287_DEVID_PCI 0x002d |
| |
| #define | AR9287_DEVID_PCIE 0x002e |
| |
| #define | AR9300_DEVID_PCIE 0x0030 |
| |
| #define | AR9300_DEVID_AR9340 0x0031 |
| |
| #define | AR9300_DEVID_AR9485_PCIE 0x0032 |
| |
| #define | AR9300_DEVID_AR9580 0x0033 |
| |
| #define | AR9300_DEVID_AR9462 0x0034 |
| |
| #define | AR9300_DEVID_AR9330 0x0035 |
| |
| #define | AR9300_DEVID_QCA955X 0x0038 |
| |
| #define | AR9485_DEVID_AR1111 0x0037 |
| |
| #define | AR9300_DEVID_AR9565 0x0036 |
| |
| #define | AR5416_AR9100_DEVID 0x000b |
| |
| #define | AR_SUBVENDOR_ID_NOG 0x0e11 |
| |
| #define | AR_SUBVENDOR_ID_NEW_A 0x7065 |
| |
| #define | AR5416_MAGIC 0x19641014 |
| |
| #define | AR9280_COEX2WIRE_SUBSYSID 0x309b |
| |
| #define | AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa |
| |
| #define | AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab |
| |
| #define | ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
| |
| #define | ATH_DEFAULT_NOISE_FLOOR -95 |
| |
| #define | ATH9K_RSSI_BAD -128 |
| |
| #define | ATH9K_NUM_CHANNELS 38 |
| |
| #define | REG_WRITE(_ah, _reg, _val) (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
| |
| #define | REG_READ(_ah, _reg) (_ah)->reg_ops.read((_ah), (_reg)) |
| |
| #define | REG_READ_MULTI(_ah, _addr, _val, _cnt) (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
| |
| #define | REG_RMW(_ah, _reg, _set, _clr) (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) |
| |
| #define | ENABLE_REGWRITE_BUFFER(_ah) |
| |
| #define | REGWRITE_BUFFER_FLUSH(_ah) |
| |
| #define | PR_EEP(_s, _val) |
| |
| #define | SM(_v, _f) (((_v) << _f##_S) & _f) |
| |
| #define | MS(_v, _f) (((_v) & _f) >> _f##_S) |
| |
| #define | REG_RMW_FIELD(_a, _r, _f, _v) REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
| |
| #define | REG_READ_FIELD(_a, _r, _f) (((REG_READ(_a, _r) & _f) >> _f##_S)) |
| |
| #define | REG_SET_BIT(_a, _r, _f) REG_RMW(_a, _r, (_f), 0) |
| |
| #define | REG_CLR_BIT(_a, _r, _f) REG_RMW(_a, _r, 0, (_f)) |
| |
| #define | DO_DELAY(x) |
| |
| #define | REG_WRITE_ARRAY(iniarray, column, regWr) ath9k_hw_write_array(ah, iniarray, column, &(regWr)) |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d |
| |
| #define | AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e |
| |
| #define | AR_GPIOD_MASK 0x00001FFF |
| |
| #define | AR_GPIO_BIT(_gpio) (1 << (_gpio)) |
| |
| #define | BASE_ACTIVATE_DELAY 100 |
| |
| #define | RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
| |
| #define | COEF_SCALE_S 24 |
| |
| #define | HT40_CHANNEL_CENTER_SHIFT 10 |
| |
| #define | ATH9K_ANTENNA0_CHAINMASK 0x1 |
| |
| #define | ATH9K_ANTENNA1_CHAINMASK 0x2 |
| |
| #define | ATH9K_NUM_DMA_DEBUG_REGS 8 |
| |
| #define | ATH9K_NUM_QUEUES 10 |
| |
| #define | MAX_RATE_POWER 63 |
| |
| #define | AH_WAIT_TIMEOUT 100000 /* (us) */ |
| |
| #define | AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
| |
| #define | AH_TIME_QUANTUM 10 |
| |
| #define | AR_KEYTABLE_SIZE 128 |
| |
| #define | POWER_UP_TIME 10000 |
| |
| #define | SPUR_RSSI_THRESH 40 |
| |
| #define | UPPER_5G_SUB_BAND_START 5700 |
| |
| #define | MID_5G_SUB_BAND_START 5400 |
| |
| #define | CAB_TIMEOUT_VAL 10 |
| |
| #define | BEACON_TIMEOUT_VAL 10 |
| |
| #define | MIN_BEACON_TIMEOUT_VAL 1 |
| |
| #define | SLEEP_SLOP 3 |
| |
| #define | INIT_CONFIG_STATUS 0x00000000 |
| |
| #define | INIT_RSSI_THR 0x00000700 |
| |
| #define | INIT_BCON_CNTRL_REG 0x00000000 |
| |
| #define | TU_TO_USEC(_tu) ((_tu) << 10) |
| |
| #define | ATH9K_HW_RX_HP_QDEPTH 16 |
| |
| #define | ATH9K_HW_RX_LP_QDEPTH 128 |
| |
| #define | PAPRD_GAIN_TABLE_ENTRIES 32 |
| |
| #define | PAPRD_TABLE_SZ 24 |
| |
| #define | PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 |
| |
| #define | KAL_FRAME_LEN 28 |
| |
| #define | KAL_FRAME_TYPE 0x2 /* data frame */ |
| |
| #define | KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ |
| |
| #define | KAL_DURATION_ID 0x3d |
| |
| #define | KAL_NUM_DATA_WORDS 6 |
| |
| #define | KAL_NUM_DESC_WORDS 12 |
| |
| #define | KAL_ANTENNA_MODE 1 |
| |
| #define | KAL_TO_DS 1 |
| |
| #define | KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ |
| |
| #define | KAL_TIMEOUT 900 |
| |
| #define | MAX_PATTERN_SIZE 256 |
| |
| #define | MAX_PATTERN_MASK_SIZE 32 |
| |
| #define | MAX_NUM_PATTERN 8 |
| |
| #define | MAX_NUM_USER_PATTERN |
| |
| #define | AH_WOW_USER_PATTERN_EN BIT(0) |
| |
| #define | AH_WOW_MAGIC_PATTERN_EN BIT(1) |
| |
| #define | AH_WOW_LINK_CHANGE BIT(2) |
| |
| #define | AH_WOW_BEACON_MISS BIT(3) |
| |
| #define | SPUR_DISABLE 0 |
| |
| #define | SPUR_ENABLE_IOCTL 1 |
| |
| #define | SPUR_ENABLE_EEPROM 2 |
| |
| #define | AR_SPUR_5413_1 1640 |
| |
| #define | AR_SPUR_5413_2 1200 |
| |
| #define | AR_NO_SPUR 0x8000 |
| |
| #define | AR_BASE_FREQ_2GHZ 2300 |
| |
| #define | AR_BASE_FREQ_5GHZ 4900 |
| |
| #define | AR_SPUR_FEEQ_BOUND_HT40 19 |
| |
| #define | AR_SPUR_FEEQ_BOUND_HT20 10 |
| |
| #define | CHANNEL_CW_INT 0x00002 |
| |
| #define | CHANNEL_CCK 0x00020 |
| |
| #define | CHANNEL_OFDM 0x00040 |
| |
| #define | CHANNEL_2GHZ 0x00080 |
| |
| #define | CHANNEL_5GHZ 0x00100 |
| |
| #define | CHANNEL_PASSIVE 0x00200 |
| |
| #define | CHANNEL_DYN 0x00400 |
| |
| #define | CHANNEL_HALF 0x04000 |
| |
| #define | CHANNEL_QUARTER 0x08000 |
| |
| #define | CHANNEL_HT20 0x10000 |
| |
| #define | CHANNEL_HT40PLUS 0x20000 |
| |
| #define | CHANNEL_HT40MINUS 0x40000 |
| |
| #define | CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
| |
| #define | CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
| |
| #define | CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
| |
| #define | CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) |
| |
| #define | CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) |
| |
| #define | CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) |
| |
| #define | CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) |
| |
| #define | CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) |
| |
| #define | CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) |
| |
| #define | CHANNEL_ALL |
| |
| #define | MAX_RTT_TABLE_ENTRY 6 |
| |
| #define | MAX_IQCAL_MEASUREMENT 8 |
| |
| #define | MAX_CL_TAB_ENTRY 16 |
| |
| #define | IS_CHAN_G(_c) |
| |
| #define | IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) |
| |
| #define | IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) |
| |
| #define | IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) |
| |
| #define | IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
| |
| #define | IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) |
| |
| #define | IS_CHAN_A_FAST_CLOCK(_ah, _c) |
| |
| #define | IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) |
| |
| #define | IS_CHAN_HT20(_c) |
| |
| #define | IS_CHAN_HT40(_c) |
| |
| #define | IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) |
| |
| #define | ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
| |
| #define | ATH_MAX_GEN_TIMER 16 |
| |
| #define | AR_GENTMR_BIT(_index) (1 << (_index)) |
| |
| #define | debruijn32 0x077CB531U |
| |
| #define | AH_USE_EEPROM 0x1 |
| |
| #define | AH_UNPLUGGED 0x2 /* The card has been physically removed. */ |
| |
| #define | AH_FASTCC 0x4 |
| |
| #define | totalPowerMeasI meas0.unsign |
| |
| #define | totalPowerMeasQ meas1.unsign |
| |
| #define | totalIqCorrMeas meas2.sign |
| |
| #define | totalAdcIOddPhase meas0.unsign |
| |
| #define | totalAdcIEvenPhase meas1.unsign |
| |
| #define | totalAdcQOddPhase meas2.unsign |
| |
| #define | totalAdcQEvenPhase meas3.unsign |
| |
| #define | totalAdcDcOffsetIOddPhase meas0.sign |
| |
| #define | totalAdcDcOffsetIEvenPhase meas1.sign |
| |
| #define | totalAdcDcOffsetQOddPhase meas2.sign |
| |
| #define | totalAdcDcOffsetQEvenPhase meas3.sign |
| |
| #define | ATH9K_CLOCK_RATE_CCK 22 |
| |
| #define | ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| |
| #define | ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
| |
| #define | ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 |
| |
|
| enum | ath_hw_txq_subtype { ATH_TXQ_AC_BE = 0,
ATH_TXQ_AC_BK = 1,
ATH_TXQ_AC_VI = 2,
ATH_TXQ_AC_VO = 3
} |
| |
| enum | ath_ini_subsys { ATH_INI_PRE = 0,
ATH_INI_CORE,
ATH_INI_POST,
ATH_INI_NUM_SPLIT
} |
| |
| enum | ath9k_hw_caps {
ATH9K_HW_CAP_HT = BIT(0),
ATH9K_HW_CAP_RFSILENT = BIT(1),
ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
ATH9K_HW_CAP_EDMA = BIT(4),
ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
ATH9K_HW_CAP_LDPC = BIT(6),
ATH9K_HW_CAP_FASTCLOCK = BIT(7),
ATH9K_HW_CAP_SGI_20 = BIT(8),
ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
ATH9K_HW_CAP_2GHZ = BIT(11),
ATH9K_HW_CAP_5GHZ = BIT(12),
ATH9K_HW_CAP_APM = BIT(13),
ATH9K_HW_CAP_RTT = BIT(14),
ATH9K_HW_CAP_MCI = BIT(15),
ATH9K_HW_CAP_DFS = BIT(16),
ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
ATH9K_HW_WOW_PATTERN_MATCH_EXACT = BIT(18),
ATH9K_HW_WOW_PATTERN_MATCH_DWORD = BIT(19)
} |
| |
| enum | ath9k_int {
ATH9K_INT_RX = 0x00000001,
ATH9K_INT_RXDESC = 0x00000002,
ATH9K_INT_RXHP = 0x00000001,
ATH9K_INT_RXLP = 0x00000002,
ATH9K_INT_RXNOFRM = 0x00000008,
ATH9K_INT_RXEOL = 0x00000010,
ATH9K_INT_RXORN = 0x00000020,
ATH9K_INT_TX = 0x00000040,
ATH9K_INT_TXDESC = 0x00000080,
ATH9K_INT_TIM_TIMER = 0x00000100,
ATH9K_INT_MCI = 0x00000200,
ATH9K_INT_BB_WATCHDOG = 0x00000400,
ATH9K_INT_TXURN = 0x00000800,
ATH9K_INT_MIB = 0x00001000,
ATH9K_INT_RXPHY = 0x00004000,
ATH9K_INT_RXKCM = 0x00008000,
ATH9K_INT_SWBA = 0x00010000,
ATH9K_INT_BMISS = 0x00040000,
ATH9K_INT_BNR = 0x00100000,
ATH9K_INT_TIM = 0x00200000,
ATH9K_INT_DTIM = 0x00400000,
ATH9K_INT_DTIMSYNC = 0x00800000,
ATH9K_INT_GPIO = 0x01000000,
ATH9K_INT_CABEND = 0x02000000,
ATH9K_INT_TSFOOR = 0x04000000,
ATH9K_INT_GENTIMER = 0x08000000,
ATH9K_INT_CST = 0x10000000,
ATH9K_INT_GTT = 0x20000000,
ATH9K_INT_FATAL = 0x40000000,
ATH9K_INT_GLOBAL = 0x80000000,
ATH9K_INT_BMISC,
ATH9K_INT_COMMON,
ATH9K_INT_NOCARD = 0xffffffff
} |
| |
| enum | ath9k_power_mode { ATH9K_PM_AWAKE = 0,
ATH9K_PM_FULL_SLEEP,
ATH9K_PM_NETWORK_SLEEP,
ATH9K_PM_UNDEFINED
} |
| |
| enum | ser_reg_mode { SER_REG_MODE_OFF = 0,
SER_REG_MODE_ON = 1,
SER_REG_MODE_AUTO = 2
} |
| |
| enum | ath9k_rx_qtype { ATH9K_RX_QUEUE_HP,
ATH9K_RX_QUEUE_LP,
ATH9K_RX_QUEUE_MAX
} |
| |
| enum | { ATH9K_RESET_POWER_ON,
ATH9K_RESET_WARM,
ATH9K_RESET_COLD
} |
| |
| enum | ath_cal_list { TX_IQ_CAL = BIT(0),
TX_IQ_ON_AGC_CAL = BIT(1),
TX_CL_CAL = BIT(2)
} |
| |
|
| void | ath9k_hw_deinit (struct ath_hw *ah) |
| |
| int | ath9k_hw_init (struct ath_hw *ah) |
| |
| int | ath9k_hw_reset (struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, bool fastcc) |
| |
| int | ath9k_hw_fill_cap_info (struct ath_hw *ah) |
| |
| u32 | ath9k_regd_get_ctl (struct ath_regulatory *reg, struct ath9k_channel *chan) |
| |
| void | ath9k_hw_cfg_gpio_input (struct ath_hw *ah, u32 gpio) |
| |
| u32 | ath9k_hw_gpio_get (struct ath_hw *ah, u32 gpio) |
| |
| void | ath9k_hw_cfg_output (struct ath_hw *ah, u32 gpio, u32 ah_signal_type) |
| |
| void | ath9k_hw_set_gpio (struct ath_hw *ah, u32 gpio, u32 val) |
| |
| void | ath9k_hw_setantenna (struct ath_hw *ah, u32 antenna) |
| |
| void | ath9k_hw_synth_delay (struct ath_hw *ah, struct ath9k_channel *chan, int hw_delay) |
| |
| bool | ath9k_hw_wait (struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
| |
| void | ath9k_hw_write_array (struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt) |
| |
| u32 | ath9k_hw_reverse_bits (u32 val, u32 n) |
| |
| u16 | ath9k_hw_computetxtime (struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, bool shortPreamble) |
| |
| void | ath9k_hw_get_channel_centers (struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers) |
| |
| u32 | ath9k_hw_getrxfilter (struct ath_hw *ah) |
| |
| void | ath9k_hw_setrxfilter (struct ath_hw *ah, u32 bits) |
| |
| bool | ath9k_hw_phy_disable (struct ath_hw *ah) |
| |
| bool | ath9k_hw_disable (struct ath_hw *ah) |
| |
| void | ath9k_hw_set_txpowerlimit (struct ath_hw *ah, u32 limit, bool test) |
| |
| void | ath9k_hw_setopmode (struct ath_hw *ah) |
| |
| void | ath9k_hw_setmcastfilter (struct ath_hw *ah, u32 filter0, u32 filter1) |
| |
| void | ath9k_hw_write_associd (struct ath_hw *ah) |
| |
| u32 | ath9k_hw_gettsf32 (struct ath_hw *ah) |
| |
| u64 | ath9k_hw_gettsf64 (struct ath_hw *ah) |
| |
| void | ath9k_hw_settsf64 (struct ath_hw *ah, u64 tsf64) |
| |
| void | ath9k_hw_reset_tsf (struct ath_hw *ah) |
| |
| void | ath9k_hw_set_tsfadjust (struct ath_hw *ah, bool set) |
| |
| void | ath9k_hw_init_global_settings (struct ath_hw *ah) |
| |
| u32 | ar9003_get_pll_sqsum_dvc (struct ath_hw *ah) |
| |
| void | ath9k_hw_set11nmac2040 (struct ath_hw *ah) |
| |
| void | ath9k_hw_beaconinit (struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
| |
| void | ath9k_hw_set_sta_beacon_timers (struct ath_hw *ah, const struct ath9k_beacon_state *bs) |
| |
| bool | ath9k_hw_check_alive (struct ath_hw *ah) |
| |
| bool | ath9k_hw_setpower (struct ath_hw *ah, enum ath9k_power_mode mode) |
| |
| struct ath_gen_timer * | ath_gen_timer_alloc (struct ath_hw *ah, void(*trigger)(void *), void(*overflow)(void *), void *arg, u8 timer_index) |
| |
| void | ath9k_hw_gen_timer_start (struct ath_hw *ah, struct ath_gen_timer *timer, u32 timer_next, u32 timer_period) |
| |
| void | ath9k_hw_gen_timer_stop (struct ath_hw *ah, struct ath_gen_timer *timer) |
| |
| void | ath_gen_timer_free (struct ath_hw *ah, struct ath_gen_timer *timer) |
| |
| void | ath_gen_timer_isr (struct ath_hw *hw) |
| |
| void | ath9k_hw_name (struct ath_hw *ah, char *hw_name, size_t len) |
| |
| void | ath9k_hw_get_delta_slope_vals (struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent) |
| |
| void | ath9k_hw_apply_txpower (struct ath_hw *ah, struct ath9k_channel *chan, bool test) |
| |
| int | ar9002_hw_rf_claim (struct ath_hw *ah) |
| |
| void | ar9002_hw_enable_async_fifo (struct ath_hw *ah) |
| |
| void | ar9003_hw_bb_watchdog_config (struct ath_hw *ah) |
| |
| void | ar9003_hw_bb_watchdog_read (struct ath_hw *ah) |
| |
| void | ar9003_hw_bb_watchdog_dbg_info (struct ath_hw *ah) |
| |
| void | ar9003_hw_disable_phy_restart (struct ath_hw *ah) |
| |
| void | ar9003_paprd_enable (struct ath_hw *ah, bool val) |
| |
| void | ar9003_paprd_populate_single_table (struct ath_hw *ah, struct ath9k_hw_cal_data *caldata, int chain) |
| |
| int | ar9003_paprd_create_curve (struct ath_hw *ah, struct ath9k_hw_cal_data *caldata, int chain) |
| |
| int | ar9003_paprd_setup_gain_table (struct ath_hw *ah, int chain) |
| |
| int | ar9003_paprd_init_table (struct ath_hw *ah) |
| |
| bool | ar9003_paprd_is_done (struct ath_hw *ah) |
| |
| void | ar5008_hw_attach_phy_ops (struct ath_hw *ah) |
| |
| void | ar9002_hw_attach_phy_ops (struct ath_hw *ah) |
| |
| void | ar9003_hw_attach_phy_ops (struct ath_hw *ah) |
| |
| void | ar9002_hw_attach_calib_ops (struct ath_hw *ah) |
| |
| void | ar9003_hw_attach_calib_ops (struct ath_hw *ah) |
| |
| void | ar9002_hw_attach_ops (struct ath_hw *ah) |
| |
| void | ar9003_hw_attach_ops (struct ath_hw *ah) |
| |
| void | ar9002_hw_load_ani_reg (struct ath_hw *ah, struct ath9k_channel *chan) |
| |
| void | ath9k_ani_reset (struct ath_hw *ah, bool is_scanning) |
| |
| void | ath9k_hw_ani_monitor (struct ath_hw *ah, struct ath9k_channel *chan) |
| |
1.8.2