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enum | Gi_Auto_Increment_Reg_Bits { Gi_Auto_Increment_Mask = 0xff
} |
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enum | Gi_Command_Reg_Bits {
Gi_Arm_Bit = 0x1,
Gi_Save_Trace_Bit = 0x2,
Gi_Load_Bit = 0x4,
Gi_Disarm_Bit = 0x10,
Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
Gi_Write_Switch_Bit = 0x80,
Gi_Synchronize_Gate_Bit = 0x100,
Gi_Little_Big_Endian_Bit = 0x200,
Gi_Bank_Switch_Start_Bit = 0x400,
Gi_Bank_Switch_Mode_Bit = 0x800,
Gi_Bank_Switch_Enable_Bit = 0x1000,
Gi_Arm_Copy_Bit = 0x2000,
Gi_Save_Trace_Copy_Bit = 0x4000,
Gi_Disarm_Copy_Bit = 0x8000
} |
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enum | Gi_Counting_Mode_Reg_Bits {
Gi_Counting_Mode_Mask = 0x7,
Gi_Counting_Mode_Normal_Bits = 0x0,
Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
Gi_Counting_Mode_Sync_Source_Bits = 0x6,
Gi_Index_Mode_Bit = 0x10,
Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
Gi_HW_Arm_Enable_Bit = 0x80,
Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
Gi_660x_Prescale_X8_Bit = 0x1000,
Gi_M_Series_Prescale_X8_Bit = 0x2000,
Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
Gi_660x_Alternate_Sync_Bit = 0x2000,
Gi_M_Series_Alternate_Sync_Bit = 0x4000,
Gi_660x_Prescale_X2_Bit = 0x4000,
Gi_M_Series_Prescale_X2_Bit = 0x8000
} |
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enum | Gi_Input_Select_Bits {
Gi_Read_Acknowledges_Irq = 0x1,
Gi_Write_Acknowledges_Irq = 0x2,
Gi_Source_Select_Mask = 0x7c,
Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
Gi_Gate_Select_Load_Source_Bit = 0x1000,
Gi_Or_Gate_Bit = 0x2000,
Gi_Output_Polarity_Bit = 0x4000,
Gi_Source_Polarity_Bit = 0x8000
} |
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enum | Gi_Mode_Bits {
Gi_Gating_Mode_Mask = 0x3,
Gi_Gating_Disabled_Bits = 0x0,
Gi_Level_Gating_Bits = 0x1,
Gi_Rising_Edge_Gating_Bits = 0x2,
Gi_Falling_Edge_Gating_Bits = 0x3,
Gi_Gate_On_Both_Edges_Bit = 0x4,
Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
Gi_Edge_Gate_Starts_Bits = 0x10,
Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
Gi_Stop_Mode_Mask = 0x60,
Gi_Stop_on_Gate_Bits = 0x00,
Gi_Stop_on_Gate_or_TC_Bits = 0x20,
Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
Gi_Load_Source_Select_Bit = 0x80,
Gi_Output_Mode_Mask = 0x300,
Gi_Output_TC_Pulse_Bits = 0x100,
Gi_Output_TC_Toggle_Bits = 0x200,
Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
Gi_Counting_Once_Mask = 0xc00,
Gi_No_Hardware_Disarm_Bits = 0x000,
Gi_Disarm_at_TC_Bits = 0x400,
Gi_Disarm_at_Gate_Bits = 0x800,
Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
Gi_Loading_On_TC_Bit = 0x1000,
Gi_Gate_Polarity_Bit = 0x2000,
Gi_Loading_On_Gate_Bit = 0x4000,
Gi_Reload_Source_Switching_Bit = 0x8000
} |
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enum | Gi_Second_Gate_Bits {
Gi_Second_Gate_Mode_Bit = 0x1,
Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
Gi_Second_Gate_Polarity_Bit = 0x2000,
Gi_Second_Gate_Subselect_Bit = 0x4000,
Gi_Source_Subselect_Bit = 0x8000
} |
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enum | Gxx_Status_Bits {
G0_Save_Bit = 0x1,
G1_Save_Bit = 0x2,
G0_Counting_Bit = 0x4,
G1_Counting_Bit = 0x8,
G0_Next_Load_Source_Bit = 0x10,
G1_Next_Load_Source_Bit = 0x20,
G0_Stale_Data_Bit = 0x40,
G1_Stale_Data_Bit = 0x80,
G0_Armed_Bit = 0x100,
G1_Armed_Bit = 0x200,
G0_No_Load_Between_Gates_Bit = 0x400,
G1_No_Load_Between_Gates_Bit = 0x800,
G0_TC_Error_Bit = 0x1000,
G1_TC_Error_Bit = 0x2000,
G0_Gate_Error_Bit = 0x4000,
G1_Gate_Error_Bit = 0x8000
} |
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enum | Gxx_Joint_Status2_Bits {
G0_Output_Bit = 0x1,
G1_Output_Bit = 0x2,
G0_HW_Save_Bit = 0x1000,
G1_HW_Save_Bit = 0x2000,
G0_Permanent_Stale_Bit = 0x4000,
G1_Permanent_Stale_Bit = 0x8000
} |
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enum | Gi_DMA_Config_Reg_Bits { Gi_DMA_Enable_Bit = 0x1,
Gi_DMA_Write_Bit = 0x2,
Gi_DMA_Int_Bit = 0x4
} |
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enum | Gi_DMA_Status_Reg_Bits { Gi_DMA_Readbank_Bit = 0x2000,
Gi_DRQ_Error_Bit = 0x4000,
Gi_DRQ_Status_Bit = 0x8000
} |
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enum | G02_Interrupt_Acknowledge_Bits { G0_Gate_Error_Confirm_Bit = 0x20,
G0_TC_Error_Confirm_Bit = 0x40
} |
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enum | G13_Interrupt_Acknowledge_Bits { G1_Gate_Error_Confirm_Bit = 0x2,
G1_TC_Error_Confirm_Bit = 0x4
} |
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enum | Gxx_Interrupt_Acknowledge_Bits { Gi_TC_Interrupt_Ack_Bit = 0x4000,
Gi_Gate_Interrupt_Ack_Bit = 0x8000
} |
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enum | Gi_Status_Bits { Gi_Gate_Interrupt_Bit = 0x4,
Gi_TC_Bit = 0x8,
Gi_Interrupt_Bit = 0x8000
} |
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enum | G02_Interrupt_Enable_Bits { G0_TC_Interrupt_Enable_Bit = 0x40,
G0_Gate_Interrupt_Enable_Bit = 0x100
} |
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enum | G13_Interrupt_Enable_Bits { G1_TC_Interrupt_Enable_Bit = 0x200,
G1_Gate_Interrupt_Enable_Bit = 0x400
} |
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