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#define | TX_DC_ENTRIES 16 |
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#define | TX_DC_ENTRIES_ORDER 1 |
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#define | RX_DC_ENTRIES 64 |
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#define | RX_DC_ENTRIES_ORDER 3 |
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#define | EFX_INT_ERROR_EXPIRE 3600 |
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#define | EFX_MAX_INT_ERRORS 5 |
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#define | EFX_RX_FLUSH_COUNT 4 |
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#define | _EFX_CHANNEL_MAGIC_TEST 0x000101 |
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#define | _EFX_CHANNEL_MAGIC_FILL 0x000102 |
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#define | _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103 |
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#define | _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104 |
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#define | _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data)) |
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#define | _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8) |
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#define | EFX_CHANNEL_MAGIC_TEST(_channel) _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel) |
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#define | EFX_CHANNEL_MAGIC_FILL(_rx_queue) |
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#define | EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) |
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#define | EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) |
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#define | REGISTER_REVISION_A 1 |
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#define | REGISTER_REVISION_B 2 |
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#define | REGISTER_REVISION_C 3 |
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#define | REGISTER_REVISION_Z 3 /* latest revision */ |
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#define | REGISTER(name, min_rev, max_rev) |
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#define | REGISTER_AA(name) REGISTER(name, A, A) |
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#define | REGISTER_AB(name) REGISTER(name, A, B) |
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#define | REGISTER_AZ(name) REGISTER(name, A, Z) |
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#define | REGISTER_BB(name) REGISTER(name, B, B) |
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#define | REGISTER_BZ(name) REGISTER(name, B, Z) |
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#define | REGISTER_CZ(name) REGISTER(name, C, Z) |
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#define | REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) |
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#define | REGISTER_TABLE(name, min_rev, max_rev) |
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#define | REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) |
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#define | REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) |
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#define | REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) |
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#define | REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) |
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#define | REGISTER_TABLE_BB_CZ(name) |
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#define | REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) |
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int | efx_nic_test_registers (struct efx_nic *efx, const struct efx_nic_register_test *regs, size_t n_regs) |
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int | efx_nic_alloc_buffer (struct efx_nic *efx, struct efx_buffer *buffer, unsigned int len) |
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void | efx_nic_free_buffer (struct efx_nic *efx, struct efx_buffer *buffer) |
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void | efx_nic_push_buffers (struct efx_tx_queue *tx_queue) |
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int | efx_nic_probe_tx (struct efx_tx_queue *tx_queue) |
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void | efx_nic_init_tx (struct efx_tx_queue *tx_queue) |
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void | efx_nic_fini_tx (struct efx_tx_queue *tx_queue) |
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void | efx_nic_remove_tx (struct efx_tx_queue *tx_queue) |
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void | efx_nic_notify_rx_desc (struct efx_rx_queue *rx_queue) |
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int | efx_nic_probe_rx (struct efx_rx_queue *rx_queue) |
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void | efx_nic_init_rx (struct efx_rx_queue *rx_queue) |
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void | efx_nic_fini_rx (struct efx_rx_queue *rx_queue) |
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void | efx_nic_remove_rx (struct efx_rx_queue *rx_queue) |
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int | efx_nic_flush_queues (struct efx_nic *efx) |
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void | efx_nic_eventq_read_ack (struct efx_channel *channel) |
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void | efx_generate_event (struct efx_nic *efx, unsigned int evq, efx_qword_t *event) |
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int | efx_nic_process_eventq (struct efx_channel *channel, int budget) |
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bool | efx_nic_event_present (struct efx_channel *channel) |
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int | efx_nic_probe_eventq (struct efx_channel *channel) |
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void | efx_nic_init_eventq (struct efx_channel *channel) |
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void | efx_nic_fini_eventq (struct efx_channel *channel) |
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void | efx_nic_remove_eventq (struct efx_channel *channel) |
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void | efx_nic_event_test_start (struct efx_channel *channel) |
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void | efx_nic_generate_fill_event (struct efx_rx_queue *rx_queue) |
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void | efx_nic_enable_interrupts (struct efx_nic *efx) |
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void | efx_nic_disable_interrupts (struct efx_nic *efx) |
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void | efx_nic_irq_test_start (struct efx_nic *efx) |
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irqreturn_t | efx_nic_fatal_interrupt (struct efx_nic *efx) |
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void | efx_nic_push_rx_indir_table (struct efx_nic *efx) |
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int | efx_nic_init_interrupt (struct efx_nic *efx) |
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void | efx_nic_fini_interrupt (struct efx_nic *efx) |
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void | efx_nic_dimension_resources (struct efx_nic *efx, unsigned sram_lim_qw) |
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u32 | efx_nic_fpga_ver (struct efx_nic *efx) |
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void | efx_nic_init_common (struct efx_nic *efx) |
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size_t | efx_nic_get_regs_len (struct efx_nic *efx) |
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void | efx_nic_get_regs (struct efx_nic *efx, void *buf) |
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