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drivers
gpu
drm
nouveau
nv50_fence.c
Go to the documentation of this file.
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <
[email protected]
>
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*/
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#include <
core/object.h
>
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#include <
core/class.h
>
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#include "
nouveau_drm.h
"
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#include "
nouveau_dma.h
"
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#include "
nouveau_fence.h
"
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#include "
nv50_display.h
"
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struct
nv50_fence_chan
{
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struct
nouveau_fence_chan
base
;
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};
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struct
nv50_fence_priv
{
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struct
nouveau_fence_priv
base
;
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struct
nouveau_bo
*
bo
;
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spinlock_t
lock
;
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u32
sequence
;
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};
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static
int
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nv50_fence_context_new(
struct
nouveau_channel
*
chan
)
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{
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struct
drm_device
*
dev
= chan->
drm
->dev;
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struct
nv50_fence_priv
*
priv
= chan->
drm
->fence;
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struct
nv50_fence_chan
*fctx;
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struct
ttm_mem_reg
*
mem
= &priv->
bo
->bo.mem;
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struct
nouveau_object
*object;
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int
ret
,
i
;
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fctx = chan->
fence
= kzalloc(
sizeof
(*fctx),
GFP_KERNEL
);
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if
(!fctx)
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return
-
ENOMEM
;
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nouveau_fence_context_new
(&fctx->
base
);
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ret =
nouveau_object_new
(nv_object(chan->
cli
), chan->
handle
,
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NvSema
, 0x0002,
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&(
struct
nv_dma_class
) {
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.flags =
NV_DMA_TARGET_VRAM
|
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NV_DMA_ACCESS_RDWR
,
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.start = mem->
start
*
PAGE_SIZE
,
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.limit = mem->
size
- 1,
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},
sizeof
(
struct
nv_dma_class
),
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&object);
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/* dma objects for display sync channel semaphore blocks */
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for
(
i
= 0; !
ret
&&
i
<
dev
->mode_config.num_crtc;
i
++) {
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struct
nouveau_bo
*
bo
=
nv50_display_crtc_sema
(
dev
,
i
);
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ret
=
nouveau_object_new
(nv_object(
chan
->cli),
chan
->handle,
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NvEvoSema0
+
i
, 0x003d,
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&(
struct
nv_dma_class
) {
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.flags =
NV_DMA_TARGET_VRAM
|
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NV_DMA_ACCESS_RDWR
,
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.start = bo->
bo
.offset,
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.limit = bo->
bo
.offset + 0xfff,
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},
sizeof
(
struct
nv_dma_class
),
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&object);
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}
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if
(
ret
)
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nv10_fence_context_del
(
chan
);
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return
ret
;
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}
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int
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nv50_fence_create
(
struct
nouveau_drm
*drm)
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{
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struct
nv50_fence_priv
*
priv
;
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int
ret
= 0;
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priv = drm->
fence
= kzalloc(
sizeof
(*priv),
GFP_KERNEL
);
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if
(!priv)
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return
-
ENOMEM
;
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priv->
base
.dtor =
nv10_fence_destroy
;
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priv->
base
.context_new = nv50_fence_context_new;
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priv->
base
.context_del =
nv10_fence_context_del
;
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priv->
base
.emit =
nv10_fence_emit
;
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priv->
base
.read =
nv10_fence_read
;
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priv->
base
.sync =
nv17_fence_sync
;
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spin_lock_init
(&priv->
lock
);
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ret =
nouveau_bo_new
(drm->
dev
, 4096, 0x1000,
TTM_PL_FLAG_VRAM
,
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0, 0x0000,
NULL
, &priv->
bo
);
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if
(!ret) {
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ret =
nouveau_bo_pin
(priv->
bo
,
TTM_PL_FLAG_VRAM
);
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if
(!ret)
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ret =
nouveau_bo_map
(priv->
bo
);
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if
(ret)
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nouveau_bo_ref(
NULL
, &priv->
bo
);
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}
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if
(ret == 0) {
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nouveau_bo_wr32
(priv->
bo
, 0x000, 0x00000000);
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priv->
base
.sync =
nv17_fence_sync
;
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}
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if
(ret)
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nv10_fence_destroy
(drm);
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return
ret
;
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}
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