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omap_hwmod_2420_data.c
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1 /*
2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * XXX handle crossbar/shared link difference for L3?
13  * XXX these should be marked initdata for multi-OMAP kernels
14  */
15 #include <linux/platform_data/spi-omap2-mcspi.h>
16 
17 #include <plat/omap_hwmod.h>
18 #include <plat/dma.h>
19 #include <plat/serial.h>
20 #include <plat/i2c.h>
21 #include <plat/dmtimer.h>
22 #include "l3_2xxx.h"
23 #include "l4_2xxx.h"
24 #include <plat/mmc.h>
25 
26 #include "omap_hwmod_common_data.h"
27 
28 #include "cm-regbits-24xx.h"
29 #include "prm-regbits-24xx.h"
30 #include "wd_timer.h"
31 
32 /*
33  * OMAP2420 hardware module integration data
34  *
35  * All of the data in this section should be autogeneratable from the
36  * TI hardware database or other technical documentation. Data that
37  * is driver-specific or driver-kernel integration-specific belongs
38  * elsewhere.
39  */
40 
41 /*
42  * IP blocks
43  */
44 
45 /* IVA1 (IVA1) */
46 static struct omap_hwmod_class iva1_hwmod_class = {
47  .name = "iva1",
48 };
49 
50 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
51  { .name = "iva", .rst_shift = 8 },
52 };
53 
54 static struct omap_hwmod omap2420_iva_hwmod = {
55  .name = "iva",
56  .class = &iva1_hwmod_class,
57  .clkdm_name = "iva1_clkdm",
58  .rst_lines = omap2420_iva_resets,
59  .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
60  .main_clk = "iva1_ifck",
61 };
62 
63 /* DSP */
64 static struct omap_hwmod_class dsp_hwmod_class = {
65  .name = "dsp",
66 };
67 
68 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
69  { .name = "logic", .rst_shift = 0 },
70  { .name = "mmu", .rst_shift = 1 },
71 };
72 
73 static struct omap_hwmod omap2420_dsp_hwmod = {
74  .name = "dsp",
75  .class = &dsp_hwmod_class,
76  .clkdm_name = "dsp_clkdm",
77  .rst_lines = omap2420_dsp_resets,
78  .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
79  .main_clk = "dsp_fck",
80 };
81 
82 /* I2C common */
83 static struct omap_hwmod_class_sysconfig i2c_sysc = {
84  .rev_offs = 0x00,
85  .sysc_offs = 0x20,
86  .syss_offs = 0x10,
87  .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
88  .sysc_fields = &omap_hwmod_sysc_type1,
89 };
90 
91 static struct omap_hwmod_class i2c_class = {
92  .name = "i2c",
93  .sysc = &i2c_sysc,
94  .rev = OMAP_I2C_IP_VERSION_1,
95  .reset = &omap_i2c_reset,
96 };
97 
98 static struct omap_i2c_dev_attr i2c_dev_attr = {
99  .flags = OMAP_I2C_FLAG_NO_FIFO |
100  OMAP_I2C_FLAG_SIMPLE_CLOCK |
101  OMAP_I2C_FLAG_16BIT_DATA_REG |
102  OMAP_I2C_FLAG_BUS_SHIFT_2,
103 };
104 
105 /* I2C1 */
106 static struct omap_hwmod omap2420_i2c1_hwmod = {
107  .name = "i2c1",
108  .mpu_irqs = omap2_i2c1_mpu_irqs,
109  .sdma_reqs = omap2_i2c1_sdma_reqs,
110  .main_clk = "i2c1_fck",
111  .prcm = {
112  .omap2 = {
113  .module_offs = CORE_MOD,
114  .prcm_reg_id = 1,
115  .module_bit = OMAP2420_EN_I2C1_SHIFT,
116  .idlest_reg_id = 1,
117  .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
118  },
119  },
120  .class = &i2c_class,
121  .dev_attr = &i2c_dev_attr,
122  .flags = HWMOD_16BIT_REG,
123 };
124 
125 /* I2C2 */
126 static struct omap_hwmod omap2420_i2c2_hwmod = {
127  .name = "i2c2",
128  .mpu_irqs = omap2_i2c2_mpu_irqs,
129  .sdma_reqs = omap2_i2c2_sdma_reqs,
130  .main_clk = "i2c2_fck",
131  .prcm = {
132  .omap2 = {
133  .module_offs = CORE_MOD,
134  .prcm_reg_id = 1,
135  .module_bit = OMAP2420_EN_I2C2_SHIFT,
136  .idlest_reg_id = 1,
137  .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
138  },
139  },
140  .class = &i2c_class,
141  .dev_attr = &i2c_dev_attr,
142  .flags = HWMOD_16BIT_REG,
143 };
144 
145 /* dma attributes */
146 static struct omap_dma_dev_attr dma_dev_attr = {
147  .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
148  IS_CSSA_32 | IS_CDSA_32,
149  .lch_count = 32,
150 };
151 
152 static struct omap_hwmod omap2420_dma_system_hwmod = {
153  .name = "dma",
154  .class = &omap2xxx_dma_hwmod_class,
155  .mpu_irqs = omap2_dma_system_irqs,
156  .main_clk = "core_l3_ck",
157  .dev_attr = &dma_dev_attr,
158  .flags = HWMOD_NO_IDLEST,
159 };
160 
161 /* mailbox */
162 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
163  { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
164  { .name = "iva", .irq = 34 + OMAP_INTC_START, },
165  { .irq = -1 },
166 };
167 
168 static struct omap_hwmod omap2420_mailbox_hwmod = {
169  .name = "mailbox",
170  .class = &omap2xxx_mailbox_hwmod_class,
171  .mpu_irqs = omap2420_mailbox_irqs,
172  .main_clk = "mailboxes_ick",
173  .prcm = {
174  .omap2 = {
175  .prcm_reg_id = 1,
176  .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
177  .module_offs = CORE_MOD,
178  .idlest_reg_id = 1,
179  .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
180  },
181  },
182 };
183 
184 /*
185  * 'mcbsp' class
186  * multi channel buffered serial port controller
187  */
188 
189 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
190  .name = "mcbsp",
191 };
192 
193 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
194  { .role = "pad_fck", .clk = "mcbsp_clks" },
195  { .role = "prcm_fck", .clk = "func_96m_ck" },
196 };
197 
198 /* mcbsp1 */
199 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
200  { .name = "tx", .irq = 59 + OMAP_INTC_START, },
201  { .name = "rx", .irq = 60 + OMAP_INTC_START, },
202  { .irq = -1 },
203 };
204 
205 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
206  .name = "mcbsp1",
207  .class = &omap2420_mcbsp_hwmod_class,
208  .mpu_irqs = omap2420_mcbsp1_irqs,
209  .sdma_reqs = omap2_mcbsp1_sdma_reqs,
210  .main_clk = "mcbsp1_fck",
211  .prcm = {
212  .omap2 = {
213  .prcm_reg_id = 1,
214  .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
215  .module_offs = CORE_MOD,
216  .idlest_reg_id = 1,
217  .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
218  },
219  },
220  .opt_clks = mcbsp_opt_clks,
221  .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
222 };
223 
224 /* mcbsp2 */
225 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
226  { .name = "tx", .irq = 62 + OMAP_INTC_START, },
227  { .name = "rx", .irq = 63 + OMAP_INTC_START, },
228  { .irq = -1 },
229 };
230 
231 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
232  .name = "mcbsp2",
233  .class = &omap2420_mcbsp_hwmod_class,
234  .mpu_irqs = omap2420_mcbsp2_irqs,
235  .sdma_reqs = omap2_mcbsp2_sdma_reqs,
236  .main_clk = "mcbsp2_fck",
237  .prcm = {
238  .omap2 = {
239  .prcm_reg_id = 1,
240  .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
241  .module_offs = CORE_MOD,
242  .idlest_reg_id = 1,
243  .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
244  },
245  },
246  .opt_clks = mcbsp_opt_clks,
247  .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
248 };
249 
250 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
251  .rev_offs = 0x3c,
252  .sysc_offs = 0x64,
253  .syss_offs = 0x68,
254  .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
255  .sysc_fields = &omap_hwmod_sysc_type1,
256 };
257 
258 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
259  .name = "msdi",
260  .sysc = &omap2420_msdi_sysc,
261  .reset = &omap_msdi_reset,
262 };
263 
264 /* msdi1 */
265 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
266  { .irq = 83 + OMAP_INTC_START, },
267  { .irq = -1 },
268 };
269 
270 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
271  { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
272  { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
273  { .dma_req = -1 }
274 };
275 
276 static struct omap_hwmod omap2420_msdi1_hwmod = {
277  .name = "msdi1",
278  .class = &omap2420_msdi_hwmod_class,
279  .mpu_irqs = omap2420_msdi1_irqs,
280  .sdma_reqs = omap2420_msdi1_sdma_reqs,
281  .main_clk = "mmc_fck",
282  .prcm = {
283  .omap2 = {
284  .prcm_reg_id = 1,
285  .module_bit = OMAP2420_EN_MMC_SHIFT,
286  .module_offs = CORE_MOD,
287  .idlest_reg_id = 1,
288  .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
289  },
290  },
291  .flags = HWMOD_16BIT_REG,
292 };
293 
294 /* HDQ1W/1-wire */
295 static struct omap_hwmod omap2420_hdq1w_hwmod = {
296  .name = "hdq1w",
297  .mpu_irqs = omap2_hdq1w_mpu_irqs,
298  .main_clk = "hdq_fck",
299  .prcm = {
300  .omap2 = {
301  .module_offs = CORE_MOD,
302  .prcm_reg_id = 1,
303  .module_bit = OMAP24XX_EN_HDQ_SHIFT,
304  .idlest_reg_id = 1,
305  .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
306  },
307  },
308  .class = &omap2_hdq1w_class,
309 };
310 
311 /*
312  * interfaces
313  */
314 
315 /* L4 CORE -> I2C1 interface */
316 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
317  .master = &omap2xxx_l4_core_hwmod,
318  .slave = &omap2420_i2c1_hwmod,
319  .clk = "i2c1_ick",
320  .addr = omap2_i2c1_addr_space,
321  .user = OCP_USER_MPU | OCP_USER_SDMA,
322 };
323 
324 /* L4 CORE -> I2C2 interface */
325 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
326  .master = &omap2xxx_l4_core_hwmod,
327  .slave = &omap2420_i2c2_hwmod,
328  .clk = "i2c2_ick",
329  .addr = omap2_i2c2_addr_space,
330  .user = OCP_USER_MPU | OCP_USER_SDMA,
331 };
332 
333 /* IVA <- L3 interface */
334 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
335  .master = &omap2xxx_l3_main_hwmod,
336  .slave = &omap2420_iva_hwmod,
337  .clk = "core_l3_ck",
338  .user = OCP_USER_MPU | OCP_USER_SDMA,
339 };
340 
341 /* DSP <- L3 interface */
342 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
343  .master = &omap2xxx_l3_main_hwmod,
344  .slave = &omap2420_dsp_hwmod,
345  .clk = "dsp_ick",
346  .user = OCP_USER_MPU | OCP_USER_SDMA,
347 };
348 
349 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
350  {
351  .pa_start = 0x48028000,
352  .pa_end = 0x48028000 + SZ_1K - 1,
353  .flags = ADDR_TYPE_RT
354  },
355  { }
356 };
357 
358 /* l4_wkup -> timer1 */
359 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
360  .master = &omap2xxx_l4_wkup_hwmod,
361  .slave = &omap2xxx_timer1_hwmod,
362  .clk = "gpt1_ick",
363  .addr = omap2420_timer1_addrs,
364  .user = OCP_USER_MPU | OCP_USER_SDMA,
365 };
366 
367 /* l4_wkup -> wd_timer2 */
368 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
369  {
370  .pa_start = 0x48022000,
371  .pa_end = 0x4802207f,
372  .flags = ADDR_TYPE_RT
373  },
374  { }
375 };
376 
377 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
378  .master = &omap2xxx_l4_wkup_hwmod,
379  .slave = &omap2xxx_wd_timer2_hwmod,
380  .clk = "mpu_wdt_ick",
381  .addr = omap2420_wd_timer2_addrs,
382  .user = OCP_USER_MPU | OCP_USER_SDMA,
383 };
384 
385 /* l4_wkup -> gpio1 */
386 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
387  {
388  .pa_start = 0x48018000,
389  .pa_end = 0x480181ff,
390  .flags = ADDR_TYPE_RT
391  },
392  { }
393 };
394 
395 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
396  .master = &omap2xxx_l4_wkup_hwmod,
397  .slave = &omap2xxx_gpio1_hwmod,
398  .clk = "gpios_ick",
399  .addr = omap2420_gpio1_addr_space,
400  .user = OCP_USER_MPU | OCP_USER_SDMA,
401 };
402 
403 /* l4_wkup -> gpio2 */
404 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
405  {
406  .pa_start = 0x4801a000,
407  .pa_end = 0x4801a1ff,
408  .flags = ADDR_TYPE_RT
409  },
410  { }
411 };
412 
413 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
414  .master = &omap2xxx_l4_wkup_hwmod,
415  .slave = &omap2xxx_gpio2_hwmod,
416  .clk = "gpios_ick",
417  .addr = omap2420_gpio2_addr_space,
418  .user = OCP_USER_MPU | OCP_USER_SDMA,
419 };
420 
421 /* l4_wkup -> gpio3 */
422 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
423  {
424  .pa_start = 0x4801c000,
425  .pa_end = 0x4801c1ff,
426  .flags = ADDR_TYPE_RT
427  },
428  { }
429 };
430 
431 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
432  .master = &omap2xxx_l4_wkup_hwmod,
433  .slave = &omap2xxx_gpio3_hwmod,
434  .clk = "gpios_ick",
435  .addr = omap2420_gpio3_addr_space,
436  .user = OCP_USER_MPU | OCP_USER_SDMA,
437 };
438 
439 /* l4_wkup -> gpio4 */
440 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
441  {
442  .pa_start = 0x4801e000,
443  .pa_end = 0x4801e1ff,
444  .flags = ADDR_TYPE_RT
445  },
446  { }
447 };
448 
449 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
450  .master = &omap2xxx_l4_wkup_hwmod,
451  .slave = &omap2xxx_gpio4_hwmod,
452  .clk = "gpios_ick",
453  .addr = omap2420_gpio4_addr_space,
454  .user = OCP_USER_MPU | OCP_USER_SDMA,
455 };
456 
457 /* dma_system -> L3 */
458 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
459  .master = &omap2420_dma_system_hwmod,
460  .slave = &omap2xxx_l3_main_hwmod,
461  .clk = "core_l3_ck",
462  .user = OCP_USER_MPU | OCP_USER_SDMA,
463 };
464 
465 /* l4_core -> dma_system */
466 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
467  .master = &omap2xxx_l4_core_hwmod,
468  .slave = &omap2420_dma_system_hwmod,
469  .clk = "sdma_ick",
470  .addr = omap2_dma_system_addrs,
471  .user = OCP_USER_MPU | OCP_USER_SDMA,
472 };
473 
474 /* l4_core -> mailbox */
475 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
476  .master = &omap2xxx_l4_core_hwmod,
477  .slave = &omap2420_mailbox_hwmod,
478  .addr = omap2_mailbox_addrs,
479  .user = OCP_USER_MPU | OCP_USER_SDMA,
480 };
481 
482 /* l4_core -> mcbsp1 */
483 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
484  .master = &omap2xxx_l4_core_hwmod,
485  .slave = &omap2420_mcbsp1_hwmod,
486  .clk = "mcbsp1_ick",
487  .addr = omap2_mcbsp1_addrs,
488  .user = OCP_USER_MPU | OCP_USER_SDMA,
489 };
490 
491 /* l4_core -> mcbsp2 */
492 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
493  .master = &omap2xxx_l4_core_hwmod,
494  .slave = &omap2420_mcbsp2_hwmod,
495  .clk = "mcbsp2_ick",
496  .addr = omap2xxx_mcbsp2_addrs,
497  .user = OCP_USER_MPU | OCP_USER_SDMA,
498 };
499 
500 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
501  {
502  .pa_start = 0x4809c000,
503  .pa_end = 0x4809c000 + SZ_128 - 1,
504  .flags = ADDR_TYPE_RT,
505  },
506  { }
507 };
508 
509 /* l4_core -> msdi1 */
510 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
511  .master = &omap2xxx_l4_core_hwmod,
512  .slave = &omap2420_msdi1_hwmod,
513  .clk = "mmc_ick",
514  .addr = omap2420_msdi1_addrs,
515  .user = OCP_USER_MPU | OCP_USER_SDMA,
516 };
517 
518 /* l4_core -> hdq1w interface */
519 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
520  .master = &omap2xxx_l4_core_hwmod,
521  .slave = &omap2420_hdq1w_hwmod,
522  .clk = "hdq_ick",
523  .addr = omap2_hdq1w_addr_space,
524  .user = OCP_USER_MPU | OCP_USER_SDMA,
525  .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
526 };
527 
528 
529 /* l4_wkup -> 32ksync_counter */
530 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
531  {
532  .pa_start = 0x48004000,
533  .pa_end = 0x4800401f,
534  .flags = ADDR_TYPE_RT
535  },
536  { }
537 };
538 
539 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
540  {
541  .pa_start = 0x6800a000,
542  .pa_end = 0x6800afff,
543  .flags = ADDR_TYPE_RT
544  },
545  { }
546 };
547 
548 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
549  .master = &omap2xxx_l4_wkup_hwmod,
550  .slave = &omap2xxx_counter_32k_hwmod,
551  .clk = "sync_32k_ick",
552  .addr = omap2420_counter_32k_addrs,
553  .user = OCP_USER_MPU | OCP_USER_SDMA,
554 };
555 
556 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
557  .master = &omap2xxx_l3_main_hwmod,
558  .slave = &omap2xxx_gpmc_hwmod,
559  .clk = "core_l3_ck",
560  .addr = omap2420_gpmc_addrs,
561  .user = OCP_USER_MPU | OCP_USER_SDMA,
562 };
563 
564 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
565  &omap2xxx_l3_main__l4_core,
566  &omap2xxx_mpu__l3_main,
567  &omap2xxx_dss__l3,
568  &omap2xxx_l4_core__mcspi1,
569  &omap2xxx_l4_core__mcspi2,
570  &omap2xxx_l4_core__l4_wkup,
571  &omap2_l4_core__uart1,
572  &omap2_l4_core__uart2,
573  &omap2_l4_core__uart3,
574  &omap2420_l4_core__i2c1,
575  &omap2420_l4_core__i2c2,
576  &omap2420_l3__iva,
577  &omap2420_l3__dsp,
578  &omap2420_l4_wkup__timer1,
579  &omap2xxx_l4_core__timer2,
580  &omap2xxx_l4_core__timer3,
581  &omap2xxx_l4_core__timer4,
582  &omap2xxx_l4_core__timer5,
583  &omap2xxx_l4_core__timer6,
584  &omap2xxx_l4_core__timer7,
585  &omap2xxx_l4_core__timer8,
586  &omap2xxx_l4_core__timer9,
587  &omap2xxx_l4_core__timer10,
588  &omap2xxx_l4_core__timer11,
589  &omap2xxx_l4_core__timer12,
590  &omap2420_l4_wkup__wd_timer2,
591  &omap2xxx_l4_core__dss,
592  &omap2xxx_l4_core__dss_dispc,
593  &omap2xxx_l4_core__dss_rfbi,
594  &omap2xxx_l4_core__dss_venc,
595  &omap2420_l4_wkup__gpio1,
596  &omap2420_l4_wkup__gpio2,
597  &omap2420_l4_wkup__gpio3,
598  &omap2420_l4_wkup__gpio4,
599  &omap2420_dma_system__l3,
600  &omap2420_l4_core__dma_system,
601  &omap2420_l4_core__mailbox,
602  &omap2420_l4_core__mcbsp1,
603  &omap2420_l4_core__mcbsp2,
604  &omap2420_l4_core__msdi1,
605  &omap2xxx_l4_core__rng,
606  &omap2420_l4_core__hdq1w,
607  &omap2420_l4_wkup__counter_32k,
608  &omap2420_l3__gpmc,
609  NULL,
610 };
611 
612 int __init omap2420_hwmod_init(void)
613 {
614  omap_hwmod_init();
615  return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
616 }
Generated on Thu Jan 10 2013 13:00:52 for Linux Kernel by   doxygen 1.8.2