19 #include <linux/kernel.h>
20 #include <linux/module.h>
32 #include <mach/board.h>
35 #define DRV_NAME "pata_at91"
36 #define DRV_VERSION "0.3"
38 #define CF_IDE_OFFSET 0x00c00000
39 #define CF_ALT_IDE_OFFSET 0x00e00000
40 #define CF_IDE_RES_SIZE 0x08
41 #define CS_PULSE_MAXIMUM 319
43 #define ER_SMC_RECALC 2
77 if (*value < range->
min) {
81 }
else if ((range->
min <= *value) && (*value <= range->
max))
109 static int calc_smc_vals(
struct device *
dev,
110 int *
setup,
int *pulse,
int *cycle,
int *cs_pulse)
115 {.
min = 0, .max = 31},
116 {.min = 128, .max = 159}
119 {.
min = 0, .max = 63},
120 {.min = 256, .max = 319}
123 {.
min = 0, .max = 127},
124 {.min = 256, .max = 383},
125 {.min = 512, .max = 639},
126 {.min = 768, .max = 895}
129 ret_val = adjust_smc_value(setup, range_setup,
ARRAY_SIZE(range_setup));
131 dev_warn(dev,
"maximal SMC Setup value\n");
135 ret_val = adjust_smc_value(pulse, range_pulse,
ARRAY_SIZE(range_pulse));
137 dev_warn(dev,
"maximal SMC Pulse value\n");
141 ret_val = adjust_smc_value(cycle, range_cycle,
ARRAY_SIZE(range_cycle));
143 dev_warn(dev,
"maximal SMC Cycle value\n");
147 dev_err(dev,
"unable to calculate valid SMC settings\n");
151 ret_val = adjust_smc_value(cs_pulse, range_pulse,
154 dev_warn(dev,
"maximal SMC CS Pulse value\n");
155 }
else if (ret_val != 0) {
157 dev_warn(dev,
"SMC Cycle extended\n");
171 static void to_smc_format(
int *setup,
int *pulse,
int *cycle,
int *cs_pulse)
173 *setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
174 *pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
175 *cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
176 *cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
179 static unsigned long calc_mck_cycles(
unsigned long ns,
unsigned long mck_hz)
190 mul = (mck_hz / 10000) << 16;
193 return (ns * mul + 65536) >> 16;
215 unsigned int cs_pulse;
217 unsigned long mck_hz;
221 cycle = calc_mck_cycles(ata->
cyc8b, mck_hz);
222 setup = calc_mck_cycles(ata->
setup, mck_hz);
223 pulse = calc_mck_cycles(ata->
act8b, mck_hz);
224 tdf_cycles = calc_mck_cycles(t6z, mck_hz);
227 ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
231 dev_err(dev,
"Interface may not operate correctly\n");
233 dev_dbg(dev,
"SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
234 setup, pulse, cycle, cs_pulse);
235 to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
241 if (tdf_cycles > 15) {
243 dev_warn(dev,
"maximal SMC TDF Cycles value\n");
246 dev_dbg(dev,
"Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
249 smc.nwe_setup =
smc.nrd_setup = setup;
250 smc.ncs_write_setup =
smc.ncs_read_setup = 0;
252 smc.nwe_pulse =
smc.nrd_pulse = pulse;
253 smc.ncs_write_pulse =
smc.ncs_read_pulse = cs_pulse;
255 smc.write_cycle =
smc.read_cycle = cycle;
272 dev_warn(ap->
dev,
"Failed to compute ATA timing %d, "
273 "set PIO_0 timing\n", ret);
276 set_smc_timing(ap->
dev, adev, info, &
timing);
279 static unsigned int pata_at91_data_xfer_noirq(
struct ata_device *dev,
283 unsigned int consumed;
311 .sff_data_xfer = pata_at91_data_xfer_noirq,
312 .set_piomode = pata_at91_set_piomode,
332 dev_err(&pdev->
dev,
"invalid number of resources\n");
339 dev_err(dev,
"failed to get mem resource\n");
353 ap->
ops = &pata_at91_port_ops;
357 if (!gpio_is_valid(irq)) {
365 dev_err(dev,
"failed to allocate memory for private data\n");
371 if (IS_ERR(info->
mck)) {
372 dev_err(dev,
"failed to get access to mck clock\n");
385 dev_err(dev,
"failed to map IO base\n");
394 dev_err(dev,
"failed to map CTL base\n");
399 ap->ioaddr.cmd_addr = info->
ide_addr;
400 ap->ioaddr.ctl_addr = info->
alt_addr + 0x06;
401 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
413 irq_flags, &pata_at91_sht);
443 .probe = pata_at91_probe,