|
| #define | PC300_PROTO_MLPPP 1 |
| |
| #define | PC300_MAXCHAN 2 /* Number of channels per card */ |
| |
| #define | PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ |
| |
| #define | PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ |
| |
| #define | PC300_OSC_CLOCK 24576000 |
| |
| #define | PC300_PCI_CLOCK 33000000 |
| |
| #define | BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */ |
| |
| #define | DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */ |
| |
| #define | DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */ |
| |
| #define | N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */ |
| |
| #define | N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */ |
| |
| #define | DMA_TX_BASE |
| |
| #define | DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ) |
| |
| #define | DMA_TX_BD_BASE 0x0000 |
| |
| #define | DMA_RX_BD_BASE |
| |
| #define | TX_BD_ADDR(chan, n) |
| |
| #define | RX_BD_ADDR(chan, n) |
| |
| #define | F_REG(reg, chan) (0x200*(chan) + ((reg)<<2)) |
| |
| #define | cpc_writeb(port, val) {writeb((u8)(val),(port)); mb();} |
| |
| #define | cpc_writew(port, val) {writew((ushort)(val),(port)); mb();} |
| |
| #define | cpc_writel(port, val) {writel((u32)(val),(port)); mb();} |
| |
| #define | cpc_readb(port) readb(port) |
| |
| #define | cpc_readw(port) readw(port) |
| |
| #define | cpc_readl(port) readl(port) |
| |
| #define | PLX_9050_LINT1_ENABLE 0x01 |
| |
| #define | PLX_9050_LINT1_POL 0x02 |
| |
| #define | PLX_9050_LINT1_STATUS 0x04 |
| |
| #define | PLX_9050_LINT2_ENABLE 0x08 |
| |
| #define | PLX_9050_LINT2_POL 0x10 |
| |
| #define | PLX_9050_LINT2_STATUS 0x20 |
| |
| #define | PLX_9050_INTR_ENABLE 0x40 |
| |
| #define | PLX_9050_SW_INTR 0x80 |
| |
| #define | PC300_CLKSEL_MASK (0x00000004UL) |
| |
| #define | PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3)) |
| |
| #define | PC300_CTYPE_MASK (0x00000800UL) |
| |
| #define | CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */ |
| |
| #define | CPLD_REG2 0x144 /* Clock enable , LED control */ |
| |
| #define | CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */ |
| |
| #define | CPLD_V2_REG2 0x104 /* Clock enable , LED control */ |
| |
| #define | CPLD_ID_REG 0x108 /* CPLD version */ |
| |
| #define | CPLD_REG1_FALC_RESET 0x01 |
| |
| #define | CPLD_REG1_SCA_RESET 0x02 |
| |
| #define | CPLD_REG1_GLOBAL_CLK 0x08 |
| |
| #define | CPLD_REG1_FALC_DCD 0x10 |
| |
| #define | CPLD_REG1_FALC_CTS 0x20 |
| |
| #define | CPLD_REG2_FALC_TX_CLK 0x01 |
| |
| #define | CPLD_REG2_FALC_RX_CLK 0x02 |
| |
| #define | CPLD_REG2_FALC_LED1 0x10 |
| |
| #define | CPLD_REG2_FALC_LED2 0x20 |
| |
| #define | PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ |
| |
| #define | N_SPPP_IOCTLS 2 |
| |
| #define | PC300_RSV 0x01 |
| |
| #define | PC300_X21 0x02 |
| |
| #define | PC300_TE 0x03 |
| |
| #define | PC300_PCI 0x00 |
| |
| #define | PC300_PMC 0x01 |
| |
| #define | PC300_LC_AMI 0x01 |
| |
| #define | PC300_LC_B8ZS 0x02 |
| |
| #define | PC300_LC_NRZ 0x03 |
| |
| #define | PC300_LC_HDB3 0x04 |
| |
| #define | PC300_FR_ESF 0x01 |
| |
| #define | PC300_FR_D4 0x02 |
| |
| #define | PC300_FR_ESF_JAPAN 0x03 |
| |
| #define | PC300_FR_MF_CRC4 0x04 |
| |
| #define | PC300_FR_MF_NON_CRC4 0x05 |
| |
| #define | PC300_FR_UNFRAMED 0x06 |
| |
| #define | PC300_LBO_0_DB 0x00 |
| |
| #define | PC300_LBO_7_5_DB 0x01 |
| |
| #define | PC300_LBO_15_DB 0x02 |
| |
| #define | PC300_LBO_22_5_DB 0x03 |
| |
| #define | PC300_RX_SENS_SH 0x01 |
| |
| #define | PC300_RX_SENS_LH 0x02 |
| |
| #define | PC300_TX_TIMEOUT (2*HZ) |
| |
| #define | PC300_TX_QUEUE_LEN 100 |
| |
| #define | PC300_DEF_MTU 1600 |
| |
1.8.2