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pc300_drv.c
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1 #define USE_PCI_CLOCK
2 static const char rcsid[] =
3 "Revision: 3.4.5 Date: 2002/03/07 ";
4 
5 /*
6  * pc300.c Cyclades-PC300(tm) Driver.
7  *
8  * Author: Ivan Passos <[email protected]>
9  * Maintainer: PC300 Maintainer <[email protected]>
10  *
11  * Copyright: (c) 1999-2003 Cyclades Corp.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version
16  * 2 of the License, or (at your option) any later version.
17  *
18  * Using tabstop = 4.
19  *
20  * $Log: pc300_drv.c,v $
21  * Revision 3.23 2002/03/20 13:58:40 henrique
22  * Fixed ortographic mistakes
23  *
24  * Revision 3.22 2002/03/13 16:56:56 henrique
25  * Take out the debug messages
26  *
27  * Revision 3.21 2002/03/07 14:17:09 henrique
28  * License data fixed
29  *
30  * Revision 3.20 2002/01/17 17:58:52 ivan
31  * Support for PC300-TE/M (PMC).
32  *
33  * Revision 3.19 2002/01/03 17:08:47 daniela
34  * Enables DMA reception when the SCA-II disables it improperly.
35  *
36  * Revision 3.18 2001/12/03 18:47:50 daniela
37  * Esthetic changes.
38  *
39  * Revision 3.17 2001/10/19 16:50:13 henrique
40  * Patch to kernel 2.4.12 and new generic hdlc.
41  *
42  * Revision 3.16 2001/10/16 15:12:31 regina
43  * clear statistics
44  *
45  * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46  * More DMA fixes for noisy lines.
47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50  * Fixed BOF interrupt treatment. Created dma_start routine.
51  * Changed min and max to cpc_min and cpc_max.
52  *
53  * Revision 3.10 2001/08/06 12:01:51 regina
54  * Fixed problem in DSR_DE bit.
55  *
56  * Revision 3.9 2001/07/18 19:27:26 daniela
57  * Added some history comments.
58  *
59  * Revision 3.8 2001/07/12 13:11:19 regina
60  * bug fix - DCD-OFF in pc300 tty driver
61  *
62  * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63  * Removing kernel 2.4.3 and previous support.
64  * DMA transmission bug fix.
65  * MTU check in cpc_net_rx fixed.
66  * Boot messages reviewed.
67  * New configuration parameters (line code, CRC calculation and clock).
68  *
69  * Revision 3.2 2001/06/22 13:13:02 regina
70  * MLPPP implementation. Changed the header of message trace to include
71  * the device name. New format : "hdlcX[R/T]: ".
72  * Default configuration changed.
73  *
74  * Revision 3.1 2001/06/15 regina
75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76  * upping major version number
77  *
78  * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79  * PC300 initial CVS version (3.4.0-pre1)
80  *
81  * Revision 3.0.1.2 2001/06/08 daniela
82  * Did some changes in the DMA programming implementation to avoid the
83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84  *
85  * Revision 3.0.1.1 2001/05/02 daniela
86  * Added kernel 2.4.3 support.
87  *
88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
89  * Added Frame Relay Support.
90  * Driver now uses HDLC generic driver to provide protocol support.
91  *
92  * Revision 3.0.0.8 2001/03/02 daniela
93  * Fixed ram size detection.
94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95  *
96  * Revision 3.0.0.7 2001/02/23 daniela
97  * netif_stop_queue called before the SCA-II transmition commands in
98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99  * transmition interrupts.
100  * Fixed falc_check_status for Unframed E1.
101  *
102  * Revision 3.0.0.6 2000/12/13 daniela
103  * Implemented pc300util support: trace, statistics, status and loopback
104  * tests for the PC300 TE boards.
105  *
106  * Revision 3.0.0.5 2000/12/12 ivan
107  * Added support for Unframed E1.
108  * Implemented monitor mode.
109  * Fixed DCD sensitivity on the second channel.
110  * Driver now complies with new PCI kernel architecture.
111  *
112  * Revision 3.0.0.4 2000/09/28 ivan
113  * Implemented DCD sensitivity.
114  * Moved hardware-specific open to the end of cpc_open, to avoid race
115  * conditions with early reception interrupts.
116  * Included code for [request|release]_mem_region().
117  * Changed location of pc300.h .
118  * Minor code revision (contrib. of Jeff Garzik).
119  *
120  * Revision 3.0.0.3 2000/07/03 ivan
121  * Previous bugfix for the framing errors with external clock made X21
122  * boards stop working. This version fixes it.
123  *
124  * Revision 3.0.0.2 2000/06/23 ivan
125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126  * handling when Tx timeouts occur.
127  * Revisited Rx statistics.
128  * Fixed a bug in the SCA-II programming that would cause framing errors
129  * when external clock was configured.
130  *
131  * Revision 3.0.0.1 2000/05/26 ivan
132  * Added logic in the SCA interrupt handler so that no board can monopolize
133  * the driver.
134  * Request PLX I/O region, although driver doesn't use it, to avoid
135  * problems with other drivers accessing it.
136  *
137  * Revision 3.0.0.0 2000/05/15 ivan
138  * Did some changes in the DMA programming implementation to avoid the
139  * occurrence of a SCA-II bug in the second channel.
140  * Implemented workaround for PLX9050 bug that would cause a system lockup
141  * in certain systems, depending on the MMIO addresses allocated to the
142  * board.
143  * Fixed the FALC chip programming to avoid synchronization problems in the
144  * second channel (TE only).
145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146  * cpc_queue_xmit().
147  * Changed the built-in driver implementation so that the driver can use the
148  * general 'hdlcN' naming convention instead of proprietary device names.
149  * Driver load messages are now device-centric, instead of board-centric.
150  * Dynamic allocation of net_device structures.
151  * Code is now compliant with the new module interface (module_[init|exit]).
152  * Make use of the PCI helper functions to access PCI resources.
153  *
154  * Revision 2.0.0.0 2000/04/15 ivan
155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156  *
157  * Revision 1.1.0.0 2000/02/28 ivan
158  * Major changes in the driver architecture.
159  * Softnet compliancy implemented.
160  * Driver now reports physical instead of virtual memory addresses.
161  * Added cpc_change_mtu function.
162  *
163  * Revision 1.0.0.0 1999/12/16 ivan
164  * First official release.
165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166  * Support for monolythic installation (i.e., drv built into the kernel).
167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
168  * SCA programming now covers X.21 as well.
169  *
170  * Revision 0.3.1.0 1999/11/18 ivan
171  * Made X.25 support configuration-dependent (as it depends on external
172  * modules to work).
173  * Changed X.25-specific function names to comply with adopted convention.
174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175  * Fixed bug in ch_config that would disable interrupts on a previously
176  * enabled channel if the other channel on the same board was enabled later.
177  *
178  * Revision 0.3.0.0 1999/11/16 daniela
179  * X.25 support.
180  *
181  * Revision 0.2.3.0 1999/11/15 ivan
182  * Function cpc_ch_status now provides more detailed information.
183  * Added support for X.21 clock configuration.
184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185  * Now using PCI clock instead of internal oscillator clock for the SCA.
186  *
187  * Revision 0.2.2.0 1999/11/10 ivan
188  * Changed the *_dma_buf_check functions so that they would print only
189  * the useful info instead of the whole buffer descriptor bank.
190  * Fixed bug in cpc_queue_xmit that would eventually crash the system
191  * in case of a packet drop.
192  * Implemented TX underrun handling.
193  * Improved SCA fine tuning to boost up its performance.
194  *
195  * Revision 0.2.1.0 1999/11/03 ivan
196  * Added functions *dma_buf_pt_init to allow independent initialization
197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198  * Kernel buffer release and tbusy clearing is now done in the interrupt
199  * handler.
200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
201  * Added a protocol-specific code section in cpc_net_rx.
202  * Removed printk level defs (they might be added back after the beta phase).
203  *
204  * Revision 0.2.0.0 1999/10/28 ivan
205  * Revisited the code so that new protocols can be easily added / supported.
206  *
207  * Revision 0.1.0.1 1999/10/20 ivan
208  * Mostly "esthetic" changes.
209  *
210  * Revision 0.1.0.0 1999/10/11 ivan
211  * Initial version.
212  *
213  */
214 
215 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
216 
217 #include <linux/module.h>
218 #include <linux/kernel.h>
219 #include <linux/mm.h>
220 #include <linux/ioport.h>
221 #include <linux/pci.h>
222 #include <linux/errno.h>
223 #include <linux/string.h>
224 #include <linux/init.h>
225 #include <linux/delay.h>
226 #include <linux/net.h>
227 #include <linux/skbuff.h>
228 #include <linux/if_arp.h>
229 #include <linux/netdevice.h>
230 #include <linux/etherdevice.h>
231 #include <linux/spinlock.h>
232 #include <linux/if.h>
233 #include <linux/slab.h>
234 #include <net/arp.h>
235 
236 #include <asm/io.h>
237 #include <asm/uaccess.h>
238 
239 #include "pc300.h"
240 
241 #define CPC_LOCK(card,flags) \
242  do { \
243  spin_lock_irqsave(&card->card_lock, flags); \
244  } while (0)
245 
246 #define CPC_UNLOCK(card,flags) \
247  do { \
248  spin_unlock_irqrestore(&card->card_lock, flags); \
249  } while (0)
250 
251 #undef PC300_DEBUG_PCI
252 #undef PC300_DEBUG_INTR
253 #undef PC300_DEBUG_TX
254 #undef PC300_DEBUG_RX
255 #undef PC300_DEBUG_OTHER
256 
257 static DEFINE_PCI_DEVICE_TABLE(cpc_pci_dev_id) = {
258  /* PC300/RSV or PC300/X21, 2 chan */
259  {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
260  /* PC300/RSV or PC300/X21, 1 chan */
261  {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
262  /* PC300/TE, 2 chan */
263  {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
264  /* PC300/TE, 1 chan */
265  {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
266  /* PC300/TE-M, 2 chan */
267  {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
268  /* PC300/TE-M, 1 chan */
269  {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
270  /* End of table */
271  {0,},
272 };
273 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
274 
275 #ifndef cpc_min
276 #define cpc_min(a,b) (((a)<(b))?(a):(b))
277 #endif
278 #ifndef cpc_max
279 #define cpc_max(a,b) (((a)>(b))?(a):(b))
280 #endif
281 
282 /* prototypes */
283 static void tx_dma_buf_pt_init(pc300_t *, int);
284 static void tx_dma_buf_init(pc300_t *, int);
285 static void rx_dma_buf_pt_init(pc300_t *, int);
286 static void rx_dma_buf_init(pc300_t *, int);
287 static void tx_dma_buf_check(pc300_t *, int);
288 static void rx_dma_buf_check(pc300_t *, int);
289 static irqreturn_t cpc_intr(int, void *);
290 static int clock_rate_calc(u32, u32, int *);
291 static u32 detect_ram(pc300_t *);
292 static void plx_init(pc300_t *);
293 static void cpc_trace(struct net_device *, struct sk_buff *, char);
294 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
295 static int cpc_close(struct net_device *dev);
296 
297 #ifdef CONFIG_PC300_MLPPP
298 void cpc_tty_init(pc300dev_t * dev);
299 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
300 void cpc_tty_receive(pc300dev_t * pc300dev);
301 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
302 #endif
303 
304 /************************/
305 /*** DMA Routines ***/
306 /************************/
307 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
308 {
309  int i;
310  int ch_factor = ch * N_DMA_TX_BUF;
311  volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
312  + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
313 
314  for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
315  cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
316  (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
317  cpc_writel(&ptdescr->ptbuf,
318  (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
319  }
320 }
321 
322 static void tx_dma_buf_init(pc300_t * card, int ch)
323 {
324  int i;
325  int ch_factor = ch * N_DMA_TX_BUF;
326  volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
327  + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
328 
329  for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
330  memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
331  cpc_writew(&ptdescr->len, 0);
332  cpc_writeb(&ptdescr->status, DST_OSB);
333  }
334  tx_dma_buf_pt_init(card, ch);
335 }
336 
337 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
338 {
339  int i;
340  int ch_factor = ch * N_DMA_RX_BUF;
341  volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
342  + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
343 
344  for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
345  cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
346  (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
347  cpc_writel(&ptdescr->ptbuf,
348  (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
349  }
350 }
351 
352 static void rx_dma_buf_init(pc300_t * card, int ch)
353 {
354  int i;
355  int ch_factor = ch * N_DMA_RX_BUF;
356  volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
357  + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
358 
359  for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
360  memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
361  cpc_writew(&ptdescr->len, 0);
362  cpc_writeb(&ptdescr->status, 0);
363  }
364  rx_dma_buf_pt_init(card, ch);
365 }
366 
367 static void tx_dma_buf_check(pc300_t * card, int ch)
368 {
369  volatile pcsca_bd_t __iomem *ptdescr;
370  int i;
371  u16 first_bd = card->chan[ch].tx_first_bd;
372  u16 next_bd = card->chan[ch].tx_next_bd;
373 
374  printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
375  first_bd, TX_BD_ADDR(ch, first_bd),
376  next_bd, TX_BD_ADDR(ch, next_bd));
377  for (i = first_bd,
378  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
379  i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
380  i = (i + 1) & (N_DMA_TX_BUF - 1),
381  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
382  printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
383  ch, i, cpc_readl(&ptdescr->next),
384  cpc_readl(&ptdescr->ptbuf),
385  cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
386  }
387  printk("\n");
388 }
389 
390 #ifdef PC300_DEBUG_OTHER
391 /* Show all TX buffer descriptors */
392 static void tx1_dma_buf_check(pc300_t * card, int ch)
393 {
394  volatile pcsca_bd_t __iomem *ptdescr;
395  int i;
396  u16 first_bd = card->chan[ch].tx_first_bd;
397  u16 next_bd = card->chan[ch].tx_next_bd;
398  u32 scabase = card->hw.scabase;
399 
400  printk ("\nnfree_tx_bd = %d\n", card->chan[ch].nfree_tx_bd);
401  printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
402  first_bd, TX_BD_ADDR(ch, first_bd),
403  next_bd, TX_BD_ADDR(ch, next_bd));
404  printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
405  cpc_readl(scabase + DTX_REG(CDAL, ch)),
406  cpc_readl(scabase + DTX_REG(EDAL, ch)));
407  for (i = 0; i < N_DMA_TX_BUF; i++) {
408  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
409  printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
410  ch, i, cpc_readl(&ptdescr->next),
411  cpc_readl(&ptdescr->ptbuf),
412  cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
413  }
414  printk("\n");
415 }
416 #endif
417 
418 static void rx_dma_buf_check(pc300_t * card, int ch)
419 {
420  volatile pcsca_bd_t __iomem *ptdescr;
421  int i;
422  u16 first_bd = card->chan[ch].rx_first_bd;
423  u16 last_bd = card->chan[ch].rx_last_bd;
424  int ch_factor;
425 
426  ch_factor = ch * N_DMA_RX_BUF;
427  printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
428  for (i = 0, ptdescr = (card->hw.rambase +
429  DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
430  i < N_DMA_RX_BUF; i++, ptdescr++) {
431  if (cpc_readb(&ptdescr->status) & DST_OSB)
432  printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
433  ch, i, cpc_readl(&ptdescr->next),
434  cpc_readl(&ptdescr->ptbuf),
435  cpc_readb(&ptdescr->status),
436  cpc_readw(&ptdescr->len));
437  }
438  printk("\n");
439 }
440 
441 static int dma_get_rx_frame_size(pc300_t * card, int ch)
442 {
443  volatile pcsca_bd_t __iomem *ptdescr;
444  u16 first_bd = card->chan[ch].rx_first_bd;
445  int rcvd = 0;
446  volatile u8 status;
447 
448  ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
449  while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
450  rcvd += cpc_readw(&ptdescr->len);
451  first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
452  if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
453  /* Return the size of a good frame or incomplete bad frame
454  * (dma_buf_read will clean the buffer descriptors in this case). */
455  return rcvd;
456  }
457  ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
458  }
459  return -1;
460 }
461 
462 /*
463  * dma_buf_write: writes a frame to the Tx DMA buffers
464  * NOTE: this function writes one frame at a time.
465  */
466 static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
467 {
468  int i, nchar;
469  volatile pcsca_bd_t __iomem *ptdescr;
470  int tosend = len;
471  u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
472 
473  if (nbuf >= card->chan[ch].nfree_tx_bd) {
474  return -ENOMEM;
475  }
476 
477  for (i = 0; i < nbuf; i++) {
478  ptdescr = (card->hw.rambase +
479  TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
480  nchar = cpc_min(BD_DEF_LEN, tosend);
481  if (cpc_readb(&ptdescr->status) & DST_OSB) {
482  memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
483  &ptdata[len - tosend], nchar);
484  cpc_writew(&ptdescr->len, nchar);
485  card->chan[ch].nfree_tx_bd--;
486  if ((i + 1) == nbuf) {
487  /* This must be the last BD to be used */
488  cpc_writeb(&ptdescr->status, DST_EOM);
489  } else {
490  cpc_writeb(&ptdescr->status, 0);
491  }
492  } else {
493  return -ENOMEM;
494  }
495  tosend -= nchar;
496  card->chan[ch].tx_next_bd =
497  (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
498  }
499  /* If it gets to here, it means we have sent the whole frame */
500  return 0;
501 }
502 
503 /*
504  * dma_buf_read: reads a frame from the Rx DMA buffers
505  * NOTE: this function reads one frame at a time.
506  */
507 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
508 {
509  int nchar;
510  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
511  volatile pcsca_bd_t __iomem *ptdescr;
512  int rcvd = 0;
513  volatile u8 status;
514 
515  ptdescr = (card->hw.rambase +
516  RX_BD_ADDR(ch, chan->rx_first_bd));
517  while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
518  nchar = cpc_readw(&ptdescr->len);
519  if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT)) ||
520  (nchar > BD_DEF_LEN)) {
521 
522  if (nchar > BD_DEF_LEN)
523  status |= DST_RBIT;
524  rcvd = -status;
525  /* Discard remaining descriptors used by the bad frame */
526  while (chan->rx_first_bd != chan->rx_last_bd) {
527  cpc_writeb(&ptdescr->status, 0);
528  chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
529  if (status & DST_EOM)
530  break;
531  ptdescr = (card->hw.rambase +
532  cpc_readl(&ptdescr->next));
533  status = cpc_readb(&ptdescr->status);
534  }
535  break;
536  }
537  if (nchar != 0) {
538  if (skb) {
539  memcpy_fromio(skb_put(skb, nchar),
540  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
541  }
542  rcvd += nchar;
543  }
544  cpc_writeb(&ptdescr->status, 0);
545  cpc_writeb(&ptdescr->len, 0);
546  chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
547 
548  if (status & DST_EOM)
549  break;
550 
551  ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
552  }
553 
554  if (rcvd != 0) {
555  /* Update pointer */
556  chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
557  /* Update EDA */
558  cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
559  RX_BD_ADDR(ch, chan->rx_last_bd));
560  }
561  return rcvd;
562 }
563 
564 static void tx_dma_stop(pc300_t * card, int ch)
565 {
566  void __iomem *scabase = card->hw.scabase;
567  u8 drr_ena_bit = 1 << (5 + 2 * ch);
568  u8 drr_rst_bit = 1 << (1 + 2 * ch);
569 
570  /* Disable DMA */
571  cpc_writeb(scabase + DRR, drr_ena_bit);
572  cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
573 }
574 
575 static void rx_dma_stop(pc300_t * card, int ch)
576 {
577  void __iomem *scabase = card->hw.scabase;
578  u8 drr_ena_bit = 1 << (4 + 2 * ch);
579  u8 drr_rst_bit = 1 << (2 * ch);
580 
581  /* Disable DMA */
582  cpc_writeb(scabase + DRR, drr_ena_bit);
583  cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
584 }
585 
586 static void rx_dma_start(pc300_t * card, int ch)
587 {
588  void __iomem *scabase = card->hw.scabase;
589  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
590 
591  /* Start DMA */
592  cpc_writel(scabase + DRX_REG(CDAL, ch),
593  RX_BD_ADDR(ch, chan->rx_first_bd));
594  if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
595  RX_BD_ADDR(ch, chan->rx_first_bd)) {
596  cpc_writel(scabase + DRX_REG(CDAL, ch),
597  RX_BD_ADDR(ch, chan->rx_first_bd));
598  }
599  cpc_writel(scabase + DRX_REG(EDAL, ch),
600  RX_BD_ADDR(ch, chan->rx_last_bd));
601  cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
602  cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
603  if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
604  cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
605  }
606 }
607 
608 /*************************/
609 /*** FALC Routines ***/
610 /*************************/
611 static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
612 {
613  void __iomem *falcbase = card->hw.falcbase;
614  unsigned long i = 0;
615 
616  while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
617  if (i++ >= PC300_FALC_MAXLOOP) {
618  printk("%s: FALC command locked(cmd=0x%x).\n",
619  card->chan[ch].d.name, cmd);
620  break;
621  }
622  }
623  cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
624 }
625 
626 static void falc_intr_enable(pc300_t * card, int ch)
627 {
628  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
629  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
630  falc_t *pfalc = (falc_t *) & chan->falc;
631  void __iomem *falcbase = card->hw.falcbase;
632 
633  /* Interrupt pins are open-drain */
634  cpc_writeb(falcbase + F_REG(IPC, ch),
635  cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
636  /* Conters updated each second */
637  cpc_writeb(falcbase + F_REG(FMR1, ch),
638  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
639  /* Enable SEC and ES interrupts */
640  cpc_writeb(falcbase + F_REG(IMR3, ch),
641  cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
642  if (conf->fr_mode == PC300_FR_UNFRAMED) {
643  cpc_writeb(falcbase + F_REG(IMR4, ch),
644  cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
645  } else {
646  cpc_writeb(falcbase + F_REG(IMR4, ch),
647  cpc_readb(falcbase + F_REG(IMR4, ch)) &
648  ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
649  }
650  if (conf->media == IF_IFACE_T1) {
651  cpc_writeb(falcbase + F_REG(IMR3, ch),
652  cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
653  } else {
654  cpc_writeb(falcbase + F_REG(IPC, ch),
655  cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
656  if (conf->fr_mode == PC300_FR_UNFRAMED) {
657  cpc_writeb(falcbase + F_REG(IMR2, ch),
658  cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
659  } else {
660  cpc_writeb(falcbase + F_REG(IMR2, ch),
661  cpc_readb(falcbase + F_REG(IMR2, ch)) &
662  ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
663  if (pfalc->multiframe_mode) {
664  cpc_writeb(falcbase + F_REG(IMR2, ch),
665  cpc_readb(falcbase + F_REG(IMR2, ch)) &
666  ~(IMR2_T400MS | IMR2_MFAR));
667  } else {
668  cpc_writeb(falcbase + F_REG(IMR2, ch),
669  cpc_readb(falcbase + F_REG(IMR2, ch)) |
670  IMR2_T400MS | IMR2_MFAR);
671  }
672  }
673  }
674 }
675 
676 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
677 {
678  void __iomem *falcbase = card->hw.falcbase;
679  u8 tshf = card->chan[ch].falc.offset;
680 
681  cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
682  cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
683  ~(0x80 >> ((timeslot - tshf) & 0x07)));
684  cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
685  cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
686  (0x80 >> (timeslot & 0x07)));
687  cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
688  cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
689  (0x80 >> (timeslot & 0x07)));
690 }
691 
692 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
693 {
694  void __iomem *falcbase = card->hw.falcbase;
695  u8 tshf = card->chan[ch].falc.offset;
696 
697  cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
698  cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
699  (0x80 >> ((timeslot - tshf) & 0x07)));
700  cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
701  cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
702  ~(0x80 >> (timeslot & 0x07)));
703  cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
704  cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
705  ~(0x80 >> (timeslot & 0x07)));
706 }
707 
708 static void falc_close_all_timeslots(pc300_t * card, int ch)
709 {
710  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
711  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
712  void __iomem *falcbase = card->hw.falcbase;
713 
714  cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
715  cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
716  cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
717  cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
718  cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
719  cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
720  cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
721  cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
722  cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
723  if (conf->media == IF_IFACE_E1) {
724  cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
725  cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
726  cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
727  }
728 }
729 
730 static void falc_open_all_timeslots(pc300_t * card, int ch)
731 {
732  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
733  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
734  void __iomem *falcbase = card->hw.falcbase;
735 
736  cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
737  if (conf->fr_mode == PC300_FR_UNFRAMED) {
738  cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
739  cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
740  } else {
741  /* Timeslot 0 is never enabled */
742  cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
743  cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
744  }
745  cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
746  cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
747  cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
748  cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
749  cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
750  cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
751  if (conf->media == IF_IFACE_E1) {
752  cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
753  cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
754  cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
755  } else {
756  cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
757  cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
758  cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
759  }
760 }
761 
762 static void falc_init_timeslot(pc300_t * card, int ch)
763 {
764  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
765  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
766  falc_t *pfalc = (falc_t *) & chan->falc;
767  int tslot;
768 
769  for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
770  if (conf->tslot_bitmap & (1 << tslot)) {
771  // Channel enabled
772  falc_open_timeslot(card, ch, tslot + 1);
773  } else {
774  // Channel disabled
775  falc_close_timeslot(card, ch, tslot + 1);
776  }
777  }
778 }
779 
780 static void falc_enable_comm(pc300_t * card, int ch)
781 {
782  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
783  falc_t *pfalc = (falc_t *) & chan->falc;
784 
785  if (pfalc->full_bandwidth) {
786  falc_open_all_timeslots(card, ch);
787  } else {
788  falc_init_timeslot(card, ch);
789  }
790  // CTS/DCD ON
791  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
792  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
793  ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
794 }
795 
796 static void falc_disable_comm(pc300_t * card, int ch)
797 {
798  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
799  falc_t *pfalc = (falc_t *) & chan->falc;
800 
801  if (pfalc->loop_active != 2) {
802  falc_close_all_timeslots(card, ch);
803  }
804  // CTS/DCD OFF
805  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
806  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
807  ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
808 }
809 
810 static void falc_init_t1(pc300_t * card, int ch)
811 {
812  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
813  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
814  falc_t *pfalc = (falc_t *) & chan->falc;
815  void __iomem *falcbase = card->hw.falcbase;
816  u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
817 
818  /* Switch to T1 mode (PCM 24) */
819  cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
820 
821  /* Wait 20 us for setup */
822  udelay(20);
823 
824  /* Transmit Buffer Size (1 frame) */
825  cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
826 
827  /* Clock mode */
828  if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
829  cpc_writeb(falcbase + F_REG(LIM0, ch),
830  cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
831  } else { /* Slave mode */
832  cpc_writeb(falcbase + F_REG(LIM0, ch),
833  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
834  cpc_writeb(falcbase + F_REG(LOOP, ch),
835  cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
836  }
837 
838  cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
839  cpc_writeb(falcbase + F_REG(FMR0, ch),
840  cpc_readb(falcbase + F_REG(FMR0, ch)) &
841  ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
842 
843  switch (conf->lcode) {
844  case PC300_LC_AMI:
845  cpc_writeb(falcbase + F_REG(FMR0, ch),
846  cpc_readb(falcbase + F_REG(FMR0, ch)) |
847  FMR0_XC1 | FMR0_RC1);
848  /* Clear Channel register to ON for all channels */
849  cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
850  cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
851  cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
852  break;
853 
854  case PC300_LC_B8ZS:
855  cpc_writeb(falcbase + F_REG(FMR0, ch),
856  cpc_readb(falcbase + F_REG(FMR0, ch)) |
857  FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
858  break;
859 
860  case PC300_LC_NRZ:
861  cpc_writeb(falcbase + F_REG(FMR0, ch),
862  cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
863  break;
864  }
865 
866  cpc_writeb(falcbase + F_REG(LIM0, ch),
867  cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
868  cpc_writeb(falcbase + F_REG(LIM0, ch),
869  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
870  /* Set interface mode to 2 MBPS */
871  cpc_writeb(falcbase + F_REG(FMR1, ch),
872  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
873 
874  switch (conf->fr_mode) {
875  case PC300_FR_ESF:
876  pfalc->multiframe_mode = 0;
877  cpc_writeb(falcbase + F_REG(FMR4, ch),
878  cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
879  cpc_writeb(falcbase + F_REG(FMR1, ch),
880  cpc_readb(falcbase + F_REG(FMR1, ch)) |
881  FMR1_CRC | FMR1_EDL);
882  cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
883  cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
884  cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
885  cpc_writeb(falcbase + F_REG(FMR0, ch),
886  cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
887  cpc_writeb(falcbase + F_REG(FMR2, ch),
888  cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
889  break;
890 
891  case PC300_FR_D4:
892  pfalc->multiframe_mode = 1;
893  cpc_writeb(falcbase + F_REG(FMR4, ch),
894  cpc_readb(falcbase + F_REG(FMR4, ch)) &
895  ~(FMR4_FM1 | FMR4_FM0));
896  cpc_writeb(falcbase + F_REG(FMR0, ch),
897  cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
898  cpc_writeb(falcbase + F_REG(FMR2, ch),
899  cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
900  break;
901  }
902 
903  /* Enable Automatic Resynchronization */
904  cpc_writeb(falcbase + F_REG(FMR4, ch),
905  cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
906 
907  /* Transmit Automatic Remote Alarm */
908  cpc_writeb(falcbase + F_REG(FMR2, ch),
909  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
910 
911  /* Channel translation mode 1 : one to one */
912  cpc_writeb(falcbase + F_REG(FMR1, ch),
913  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
914 
915  /* No signaling */
916  cpc_writeb(falcbase + F_REG(FMR1, ch),
917  cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
918  cpc_writeb(falcbase + F_REG(FMR5, ch),
919  cpc_readb(falcbase + F_REG(FMR5, ch)) &
920  ~(FMR5_EIBR | FMR5_SRS));
921  cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
922 
923  cpc_writeb(falcbase + F_REG(LIM1, ch),
924  cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
925 
926  switch (conf->lbo) {
927  /* Provides proper Line Build Out */
928  case PC300_LBO_0_DB:
929  cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
930  cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
931  cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
932  cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
933  break;
934  case PC300_LBO_7_5_DB:
935  cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
936  cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
937  cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
938  cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
939  break;
940  case PC300_LBO_15_DB:
941  cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
942  cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
943  cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
944  cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
945  break;
946  case PC300_LBO_22_5_DB:
947  cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
948  cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
949  cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
950  cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
951  break;
952  }
953 
954  /* Transmit Clock-Slot Offset */
955  cpc_writeb(falcbase + F_REG(XC0, ch),
956  cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
957  /* Transmit Time-slot Offset */
958  cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
959  /* Receive Clock-Slot offset */
960  cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
961  /* Receive Time-slot offset */
962  cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
963 
964  /* LOS Detection after 176 consecutive 0s */
965  cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
966  /* LOS Recovery after 22 ones in the time window of PCD */
967  cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
968 
969  cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
970 
971  if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
972  cpc_writeb(falcbase + F_REG(RC1, ch),
973  cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
974  }
975 
976  falc_close_all_timeslots(card, ch);
977 }
978 
979 static void falc_init_e1(pc300_t * card, int ch)
980 {
981  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
982  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
983  falc_t *pfalc = (falc_t *) & chan->falc;
984  void __iomem *falcbase = card->hw.falcbase;
985  u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
986 
987  /* Switch to E1 mode (PCM 30) */
988  cpc_writeb(falcbase + F_REG(FMR1, ch),
989  cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
990 
991  /* Clock mode */
992  if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
993  cpc_writeb(falcbase + F_REG(LIM0, ch),
994  cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
995  } else { /* Slave mode */
996  cpc_writeb(falcbase + F_REG(LIM0, ch),
997  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
998  }
999  cpc_writeb(falcbase + F_REG(LOOP, ch),
1000  cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1001 
1002  cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1003  cpc_writeb(falcbase + F_REG(FMR0, ch),
1004  cpc_readb(falcbase + F_REG(FMR0, ch)) &
1005  ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1006 
1007  switch (conf->lcode) {
1008  case PC300_LC_AMI:
1009  cpc_writeb(falcbase + F_REG(FMR0, ch),
1010  cpc_readb(falcbase + F_REG(FMR0, ch)) |
1011  FMR0_XC1 | FMR0_RC1);
1012  break;
1013 
1014  case PC300_LC_HDB3:
1015  cpc_writeb(falcbase + F_REG(FMR0, ch),
1016  cpc_readb(falcbase + F_REG(FMR0, ch)) |
1017  FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1018  break;
1019 
1020  case PC300_LC_NRZ:
1021  break;
1022  }
1023 
1024  cpc_writeb(falcbase + F_REG(LIM0, ch),
1025  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1026  /* Set interface mode to 2 MBPS */
1027  cpc_writeb(falcbase + F_REG(FMR1, ch),
1028  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1029 
1030  cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1031  cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1032  cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1033 
1034  switch (conf->fr_mode) {
1035  case PC300_FR_MF_CRC4:
1036  pfalc->multiframe_mode = 1;
1037  cpc_writeb(falcbase + F_REG(FMR1, ch),
1038  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1039  cpc_writeb(falcbase + F_REG(FMR2, ch),
1040  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1041  cpc_writeb(falcbase + F_REG(FMR2, ch),
1042  cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1043  cpc_writeb(falcbase + F_REG(FMR3, ch),
1044  cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1045 
1046  /* MultiFrame Resynchronization */
1047  cpc_writeb(falcbase + F_REG(FMR1, ch),
1048  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1049 
1050  /* Automatic Loss of Multiframe > 914 CRC errors */
1051  cpc_writeb(falcbase + F_REG(FMR2, ch),
1052  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1053 
1054  /* S1 and SI1/SI2 spare Bits set to 1 */
1055  cpc_writeb(falcbase + F_REG(XSP, ch),
1056  cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1057  cpc_writeb(falcbase + F_REG(XSP, ch),
1058  cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1059  cpc_writeb(falcbase + F_REG(XSP, ch),
1060  cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1061 
1062  /* Automatic Force Resynchronization */
1063  cpc_writeb(falcbase + F_REG(FMR1, ch),
1064  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1065 
1066  /* Transmit Automatic Remote Alarm */
1067  cpc_writeb(falcbase + F_REG(FMR2, ch),
1068  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1069 
1070  /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1071  cpc_writeb(falcbase + F_REG(XSW, ch),
1072  cpc_readb(falcbase + F_REG(XSW, ch)) |
1073  XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1074  break;
1075 
1076  case PC300_FR_MF_NON_CRC4:
1077  case PC300_FR_D4:
1078  pfalc->multiframe_mode = 0;
1079  cpc_writeb(falcbase + F_REG(FMR1, ch),
1080  cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1081  cpc_writeb(falcbase + F_REG(FMR2, ch),
1082  cpc_readb(falcbase + F_REG(FMR2, ch)) &
1083  ~(FMR2_RFS1 | FMR2_RFS0));
1084  cpc_writeb(falcbase + F_REG(XSW, ch),
1085  cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1086  cpc_writeb(falcbase + F_REG(XSP, ch),
1087  cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1088 
1089  /* Automatic Force Resynchronization */
1090  cpc_writeb(falcbase + F_REG(FMR1, ch),
1091  cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1092 
1093  /* Transmit Automatic Remote Alarm */
1094  cpc_writeb(falcbase + F_REG(FMR2, ch),
1095  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1096 
1097  /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1098  cpc_writeb(falcbase + F_REG(XSW, ch),
1099  cpc_readb(falcbase + F_REG(XSW, ch)) |
1100  XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1101  break;
1102 
1103  case PC300_FR_UNFRAMED:
1104  pfalc->multiframe_mode = 0;
1105  cpc_writeb(falcbase + F_REG(FMR1, ch),
1106  cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1107  cpc_writeb(falcbase + F_REG(FMR2, ch),
1108  cpc_readb(falcbase + F_REG(FMR2, ch)) &
1109  ~(FMR2_RFS1 | FMR2_RFS0));
1110  cpc_writeb(falcbase + F_REG(XSP, ch),
1111  cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1112  cpc_writeb(falcbase + F_REG(XSW, ch),
1113  cpc_readb(falcbase + F_REG(XSW, ch)) &
1114  ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1115  cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1116  cpc_writeb(falcbase + F_REG(FMR2, ch),
1117  cpc_readb(falcbase + F_REG(FMR2, ch)) |
1118  (FMR2_RTM | FMR2_DAIS));
1119  cpc_writeb(falcbase + F_REG(FMR2, ch),
1120  cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1121  cpc_writeb(falcbase + F_REG(FMR1, ch),
1122  cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1123  pfalc->sync = 1;
1124  cpc_writeb(falcbase + card->hw.cpld_reg2,
1125  cpc_readb(falcbase + card->hw.cpld_reg2) |
1126  (CPLD_REG2_FALC_LED2 << (2 * ch)));
1127  break;
1128  }
1129 
1130  /* No signaling */
1131  cpc_writeb(falcbase + F_REG(XSP, ch),
1132  cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1133  cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1134 
1135  cpc_writeb(falcbase + F_REG(LIM1, ch),
1136  cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1137  cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1138 
1139  /* Transmit Clock-Slot Offset */
1140  cpc_writeb(falcbase + F_REG(XC0, ch),
1141  cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1142  /* Transmit Time-slot Offset */
1143  cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1144  /* Receive Clock-Slot offset */
1145  cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1146  /* Receive Time-slot offset */
1147  cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1148 
1149  /* LOS Detection after 176 consecutive 0s */
1150  cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1151  /* LOS Recovery after 22 ones in the time window of PCD */
1152  cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1153 
1154  cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1155 
1156  falc_close_all_timeslots(card, ch);
1157 }
1158 
1159 static void falc_init_hdlc(pc300_t * card, int ch)
1160 {
1161  void __iomem *falcbase = card->hw.falcbase;
1162  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1163  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1164 
1165  /* Enable transparent data transfer */
1166  if (conf->fr_mode == PC300_FR_UNFRAMED) {
1167  cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1168  } else {
1169  cpc_writeb(falcbase + F_REG(MODE, ch),
1170  cpc_readb(falcbase + F_REG(MODE, ch)) |
1171  (MODE_HRAC | MODE_MDS2));
1172  cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1173  cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1174  cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1175  cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1176  }
1177 
1178  /* Tx/Rx reset */
1179  falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1180 
1181  /* Enable interrupt sources */
1182  falc_intr_enable(card, ch);
1183 }
1184 
1185 static void te_config(pc300_t * card, int ch)
1186 {
1187  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1188  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1189  falc_t *pfalc = (falc_t *) & chan->falc;
1190  void __iomem *falcbase = card->hw.falcbase;
1191  u8 dummy;
1192  unsigned long flags;
1193 
1194  memset(pfalc, 0, sizeof(falc_t));
1195  switch (conf->media) {
1196  case IF_IFACE_T1:
1197  pfalc->num_channels = NUM_OF_T1_CHANNELS;
1198  pfalc->offset = 1;
1199  break;
1200  case IF_IFACE_E1:
1201  pfalc->num_channels = NUM_OF_E1_CHANNELS;
1202  pfalc->offset = 0;
1203  break;
1204  }
1205  if (conf->tslot_bitmap == 0xffffffffUL)
1206  pfalc->full_bandwidth = 1;
1207  else
1208  pfalc->full_bandwidth = 0;
1209 
1210  CPC_LOCK(card, flags);
1211  /* Reset the FALC chip */
1212  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1213  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1214  (CPLD_REG1_FALC_RESET << (2 * ch)));
1215  udelay(10000);
1216  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1217  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1218  ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1219 
1220  if (conf->media == IF_IFACE_T1) {
1221  falc_init_t1(card, ch);
1222  } else {
1223  falc_init_e1(card, ch);
1224  }
1225  falc_init_hdlc(card, ch);
1226  if (conf->rx_sens == PC300_RX_SENS_SH) {
1227  cpc_writeb(falcbase + F_REG(LIM0, ch),
1228  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1229  } else {
1230  cpc_writeb(falcbase + F_REG(LIM0, ch),
1231  cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1232  }
1233  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1234  cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1235  ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1236 
1237  /* Clear all interrupt registers */
1238  dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1239  cpc_readb(falcbase + F_REG(FISR1, ch)) +
1240  cpc_readb(falcbase + F_REG(FISR2, ch)) +
1241  cpc_readb(falcbase + F_REG(FISR3, ch));
1242  CPC_UNLOCK(card, flags);
1243 }
1244 
1245 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1246 {
1247  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1248  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1249  falc_t *pfalc = (falc_t *) & chan->falc;
1250  void __iomem *falcbase = card->hw.falcbase;
1251 
1252  /* Verify LOS */
1253  if (frs0 & FRS0_LOS) {
1254  if (!pfalc->red_alarm) {
1255  pfalc->red_alarm = 1;
1256  pfalc->los++;
1257  if (!pfalc->blue_alarm) {
1258  // EVENT_FALC_ABNORMAL
1259  if (conf->media == IF_IFACE_T1) {
1260  /* Disable this interrupt as it may otherwise interfere
1261  * with other working boards. */
1262  cpc_writeb(falcbase + F_REG(IMR0, ch),
1263  cpc_readb(falcbase + F_REG(IMR0, ch))
1264  | IMR0_PDEN);
1265  }
1266  falc_disable_comm(card, ch);
1267  // EVENT_FALC_ABNORMAL
1268  }
1269  }
1270  } else {
1271  if (pfalc->red_alarm) {
1272  pfalc->red_alarm = 0;
1273  pfalc->losr++;
1274  }
1275  }
1276 
1277  if (conf->fr_mode != PC300_FR_UNFRAMED) {
1278  /* Verify AIS alarm */
1279  if (frs0 & FRS0_AIS) {
1280  if (!pfalc->blue_alarm) {
1281  pfalc->blue_alarm = 1;
1282  pfalc->ais++;
1283  // EVENT_AIS
1284  if (conf->media == IF_IFACE_T1) {
1285  /* Disable this interrupt as it may otherwise interfere with other working boards. */
1286  cpc_writeb(falcbase + F_REG(IMR0, ch),
1287  cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1288  }
1289  falc_disable_comm(card, ch);
1290  // EVENT_AIS
1291  }
1292  } else {
1293  pfalc->blue_alarm = 0;
1294  }
1295 
1296  /* Verify LFA */
1297  if (frs0 & FRS0_LFA) {
1298  if (!pfalc->loss_fa) {
1299  pfalc->loss_fa = 1;
1300  pfalc->lfa++;
1301  if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1302  // EVENT_FALC_ABNORMAL
1303  if (conf->media == IF_IFACE_T1) {
1304  /* Disable this interrupt as it may otherwise
1305  * interfere with other working boards. */
1306  cpc_writeb(falcbase + F_REG(IMR0, ch),
1307  cpc_readb(falcbase + F_REG(IMR0, ch))
1308  | IMR0_PDEN);
1309  }
1310  falc_disable_comm(card, ch);
1311  // EVENT_FALC_ABNORMAL
1312  }
1313  }
1314  } else {
1315  if (pfalc->loss_fa) {
1316  pfalc->loss_fa = 0;
1317  pfalc->farec++;
1318  }
1319  }
1320 
1321  /* Verify LMFA */
1322  if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1323  /* D4 or CRC4 frame mode */
1324  if (!pfalc->loss_mfa) {
1325  pfalc->loss_mfa = 1;
1326  pfalc->lmfa++;
1327  if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1328  !pfalc->loss_fa) {
1329  // EVENT_FALC_ABNORMAL
1330  if (conf->media == IF_IFACE_T1) {
1331  /* Disable this interrupt as it may otherwise
1332  * interfere with other working boards. */
1333  cpc_writeb(falcbase + F_REG(IMR0, ch),
1334  cpc_readb(falcbase + F_REG(IMR0, ch))
1335  | IMR0_PDEN);
1336  }
1337  falc_disable_comm(card, ch);
1338  // EVENT_FALC_ABNORMAL
1339  }
1340  }
1341  } else {
1342  pfalc->loss_mfa = 0;
1343  }
1344 
1345  /* Verify Remote Alarm */
1346  if (frs0 & FRS0_RRA) {
1347  if (!pfalc->yellow_alarm) {
1348  pfalc->yellow_alarm = 1;
1349  pfalc->rai++;
1350  if (pfalc->sync) {
1351  // EVENT_RAI
1352  falc_disable_comm(card, ch);
1353  // EVENT_RAI
1354  }
1355  }
1356  } else {
1357  pfalc->yellow_alarm = 0;
1358  }
1359  } /* if !PC300_UNFRAMED */
1360 
1361  if (pfalc->red_alarm || pfalc->loss_fa ||
1362  pfalc->loss_mfa || pfalc->blue_alarm) {
1363  if (pfalc->sync) {
1364  pfalc->sync = 0;
1365  chan->d.line_off++;
1366  cpc_writeb(falcbase + card->hw.cpld_reg2,
1367  cpc_readb(falcbase + card->hw.cpld_reg2) &
1368  ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1369  }
1370  } else {
1371  if (!pfalc->sync) {
1372  pfalc->sync = 1;
1373  chan->d.line_on++;
1374  cpc_writeb(falcbase + card->hw.cpld_reg2,
1375  cpc_readb(falcbase + card->hw.cpld_reg2) |
1376  (CPLD_REG2_FALC_LED2 << (2 * ch)));
1377  }
1378  }
1379 
1380  if (pfalc->sync && !pfalc->yellow_alarm) {
1381  if (!pfalc->active) {
1382  // EVENT_FALC_NORMAL
1383  if (pfalc->loop_active) {
1384  return;
1385  }
1386  if (conf->media == IF_IFACE_T1) {
1387  cpc_writeb(falcbase + F_REG(IMR0, ch),
1388  cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1389  }
1390  falc_enable_comm(card, ch);
1391  // EVENT_FALC_NORMAL
1392  pfalc->active = 1;
1393  }
1394  } else {
1395  if (pfalc->active) {
1396  pfalc->active = 0;
1397  }
1398  }
1399 }
1400 
1401 static void falc_update_stats(pc300_t * card, int ch)
1402 {
1403  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1404  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1405  falc_t *pfalc = (falc_t *) & chan->falc;
1406  void __iomem *falcbase = card->hw.falcbase;
1407  u16 counter;
1408 
1409  counter = cpc_readb(falcbase + F_REG(FECL, ch));
1410  counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1411  pfalc->fec += counter;
1412 
1413  counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1414  counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1415  pfalc->cvc += counter;
1416 
1417  counter = cpc_readb(falcbase + F_REG(CECL, ch));
1418  counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1419  pfalc->cec += counter;
1420 
1421  counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1422  counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1423  pfalc->ebc += counter;
1424 
1425  if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1426  mdelay(10);
1427  counter = cpc_readb(falcbase + F_REG(BECL, ch));
1428  counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1429  pfalc->bec += counter;
1430 
1431  if (((conf->media == IF_IFACE_T1) &&
1432  (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1433  (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN))) ||
1434  ((conf->media == IF_IFACE_E1) &&
1435  (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1436  pfalc->prbs = 2;
1437  } else {
1438  pfalc->prbs = 1;
1439  }
1440  }
1441 }
1442 
1443 /*----------------------------------------------------------------------------
1444  * falc_remote_loop
1445  *----------------------------------------------------------------------------
1446  * Description: In the remote loopback mode the clock and data recovered
1447  * from the line inputs RL1/2 or RDIP/RDIN are routed back
1448  * to the line outputs XL1/2 or XDOP/XDON via the analog
1449  * transmitter. As in normal mode they are processed by
1450  * the synchronizer and then sent to the system interface.
1451  *----------------------------------------------------------------------------
1452  */
1453 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1454 {
1455  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1456  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1457  falc_t *pfalc = (falc_t *) & chan->falc;
1458  void __iomem *falcbase = card->hw.falcbase;
1459 
1460  if (loop_on) {
1461  // EVENT_FALC_ABNORMAL
1462  if (conf->media == IF_IFACE_T1) {
1463  /* Disable this interrupt as it may otherwise interfere with
1464  * other working boards. */
1465  cpc_writeb(falcbase + F_REG(IMR0, ch),
1466  cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1467  }
1468  falc_disable_comm(card, ch);
1469  // EVENT_FALC_ABNORMAL
1470  cpc_writeb(falcbase + F_REG(LIM1, ch),
1471  cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1472  pfalc->loop_active = 1;
1473  } else {
1474  cpc_writeb(falcbase + F_REG(LIM1, ch),
1475  cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1476  pfalc->sync = 0;
1477  cpc_writeb(falcbase + card->hw.cpld_reg2,
1478  cpc_readb(falcbase + card->hw.cpld_reg2) &
1479  ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1480  pfalc->active = 0;
1481  falc_issue_cmd(card, ch, CMDR_XRES);
1482  pfalc->loop_active = 0;
1483  }
1484 }
1485 
1486 /*----------------------------------------------------------------------------
1487  * falc_local_loop
1488  *----------------------------------------------------------------------------
1489  * Description: The local loopback mode disconnects the receive lines
1490  * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1491  * signals coming from the line the data provided by system
1492  * interface are routed through the analog receiver back to
1493  * the system interface. The unipolar bit stream will be
1494  * undisturbed transmitted on the line. Receiver and transmitter
1495  * coding must be identical.
1496  *----------------------------------------------------------------------------
1497  */
1498 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1499 {
1500  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1501  falc_t *pfalc = (falc_t *) & chan->falc;
1502  void __iomem *falcbase = card->hw.falcbase;
1503 
1504  if (loop_on) {
1505  cpc_writeb(falcbase + F_REG(LIM0, ch),
1506  cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1507  pfalc->loop_active = 1;
1508  } else {
1509  cpc_writeb(falcbase + F_REG(LIM0, ch),
1510  cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1511  pfalc->loop_active = 0;
1512  }
1513 }
1514 
1515 /*----------------------------------------------------------------------------
1516  * falc_payload_loop
1517  *----------------------------------------------------------------------------
1518  * Description: This routine allows to enable/disable payload loopback.
1519  * When the payload loop is activated, the received 192 bits
1520  * of payload data will be looped back to the transmit
1521  * direction. The framing bits, CRC6 and DL bits are not
1522  * looped. They are originated by the FALC-LH transmitter.
1523  *----------------------------------------------------------------------------
1524  */
1525 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1526 {
1527  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1528  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1529  falc_t *pfalc = (falc_t *) & chan->falc;
1530  void __iomem *falcbase = card->hw.falcbase;
1531 
1532  if (loop_on) {
1533  // EVENT_FALC_ABNORMAL
1534  if (conf->media == IF_IFACE_T1) {
1535  /* Disable this interrupt as it may otherwise interfere with
1536  * other working boards. */
1537  cpc_writeb(falcbase + F_REG(IMR0, ch),
1538  cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1539  }
1540  falc_disable_comm(card, ch);
1541  // EVENT_FALC_ABNORMAL
1542  cpc_writeb(falcbase + F_REG(FMR2, ch),
1543  cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1544  if (conf->media == IF_IFACE_T1) {
1545  cpc_writeb(falcbase + F_REG(FMR4, ch),
1546  cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1547  } else {
1548  cpc_writeb(falcbase + F_REG(FMR5, ch),
1549  cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1550  }
1551  falc_open_all_timeslots(card, ch);
1552  pfalc->loop_active = 2;
1553  } else {
1554  cpc_writeb(falcbase + F_REG(FMR2, ch),
1555  cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1556  if (conf->media == IF_IFACE_T1) {
1557  cpc_writeb(falcbase + F_REG(FMR4, ch),
1558  cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1559  } else {
1560  cpc_writeb(falcbase + F_REG(FMR5, ch),
1561  cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1562  }
1563  pfalc->sync = 0;
1564  cpc_writeb(falcbase + card->hw.cpld_reg2,
1565  cpc_readb(falcbase + card->hw.cpld_reg2) &
1566  ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1567  pfalc->active = 0;
1568  falc_issue_cmd(card, ch, CMDR_XRES);
1569  pfalc->loop_active = 0;
1570  }
1571 }
1572 
1573 /*----------------------------------------------------------------------------
1574  * turn_off_xlu
1575  *----------------------------------------------------------------------------
1576  * Description: Turns XLU bit off in the proper register
1577  *----------------------------------------------------------------------------
1578  */
1579 static void turn_off_xlu(pc300_t * card, int ch)
1580 {
1581  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1582  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1583  void __iomem *falcbase = card->hw.falcbase;
1584 
1585  if (conf->media == IF_IFACE_T1) {
1586  cpc_writeb(falcbase + F_REG(FMR5, ch),
1587  cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1588  } else {
1589  cpc_writeb(falcbase + F_REG(FMR3, ch),
1590  cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1591  }
1592 }
1593 
1594 /*----------------------------------------------------------------------------
1595  * turn_off_xld
1596  *----------------------------------------------------------------------------
1597  * Description: Turns XLD bit off in the proper register
1598  *----------------------------------------------------------------------------
1599  */
1600 static void turn_off_xld(pc300_t * card, int ch)
1601 {
1602  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1603  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1604  void __iomem *falcbase = card->hw.falcbase;
1605 
1606  if (conf->media == IF_IFACE_T1) {
1607  cpc_writeb(falcbase + F_REG(FMR5, ch),
1608  cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1609  } else {
1610  cpc_writeb(falcbase + F_REG(FMR3, ch),
1611  cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1612  }
1613 }
1614 
1615 /*----------------------------------------------------------------------------
1616  * falc_generate_loop_up_code
1617  *----------------------------------------------------------------------------
1618  * Description: This routine writes the proper FALC chip register in order
1619  * to generate a LOOP activation code over a T1/E1 line.
1620  *----------------------------------------------------------------------------
1621  */
1622 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1623 {
1624  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1625  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1626  falc_t *pfalc = (falc_t *) & chan->falc;
1627  void __iomem *falcbase = card->hw.falcbase;
1628 
1629  if (conf->media == IF_IFACE_T1) {
1630  cpc_writeb(falcbase + F_REG(FMR5, ch),
1631  cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1632  } else {
1633  cpc_writeb(falcbase + F_REG(FMR3, ch),
1634  cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1635  }
1636  // EVENT_FALC_ABNORMAL
1637  if (conf->media == IF_IFACE_T1) {
1638  /* Disable this interrupt as it may otherwise interfere with
1639  * other working boards. */
1640  cpc_writeb(falcbase + F_REG(IMR0, ch),
1641  cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1642  }
1643  falc_disable_comm(card, ch);
1644  // EVENT_FALC_ABNORMAL
1645  pfalc->loop_gen = 1;
1646 }
1647 
1648 /*----------------------------------------------------------------------------
1649  * falc_generate_loop_down_code
1650  *----------------------------------------------------------------------------
1651  * Description: This routine writes the proper FALC chip register in order
1652  * to generate a LOOP deactivation code over a T1/E1 line.
1653  *----------------------------------------------------------------------------
1654  */
1655 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1656 {
1657  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1658  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1659  falc_t *pfalc = (falc_t *) & chan->falc;
1660  void __iomem *falcbase = card->hw.falcbase;
1661 
1662  if (conf->media == IF_IFACE_T1) {
1663  cpc_writeb(falcbase + F_REG(FMR5, ch),
1664  cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1665  } else {
1666  cpc_writeb(falcbase + F_REG(FMR3, ch),
1667  cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1668  }
1669  pfalc->sync = 0;
1670  cpc_writeb(falcbase + card->hw.cpld_reg2,
1671  cpc_readb(falcbase + card->hw.cpld_reg2) &
1672  ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1673  pfalc->active = 0;
1674 //? falc_issue_cmd(card, ch, CMDR_XRES);
1675  pfalc->loop_gen = 0;
1676 }
1677 
1678 /*----------------------------------------------------------------------------
1679  * falc_pattern_test
1680  *----------------------------------------------------------------------------
1681  * Description: This routine generates a pattern code and checks
1682  * it on the reception side.
1683  *----------------------------------------------------------------------------
1684  */
1685 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1686 {
1687  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1688  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1689  falc_t *pfalc = (falc_t *) & chan->falc;
1690  void __iomem *falcbase = card->hw.falcbase;
1691 
1692  if (activate) {
1693  pfalc->prbs = 1;
1694  pfalc->bec = 0;
1695  if (conf->media == IF_IFACE_T1) {
1696  /* Disable local loop activation/deactivation detect */
1697  cpc_writeb(falcbase + F_REG(IMR3, ch),
1698  cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1699  } else {
1700  /* Disable local loop activation/deactivation detect */
1701  cpc_writeb(falcbase + F_REG(IMR1, ch),
1702  cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1703  }
1704  /* Activates generation and monitoring of PRBS
1705  * (Pseudo Random Bit Sequence) */
1706  cpc_writeb(falcbase + F_REG(LCR1, ch),
1707  cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1708  } else {
1709  pfalc->prbs = 0;
1710  /* Deactivates generation and monitoring of PRBS
1711  * (Pseudo Random Bit Sequence) */
1712  cpc_writeb(falcbase + F_REG(LCR1, ch),
1713  cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1714  if (conf->media == IF_IFACE_T1) {
1715  /* Enable local loop activation/deactivation detect */
1716  cpc_writeb(falcbase + F_REG(IMR3, ch),
1717  cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1718  } else {
1719  /* Enable local loop activation/deactivation detect */
1720  cpc_writeb(falcbase + F_REG(IMR1, ch),
1721  cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1722  }
1723  }
1724 }
1725 
1726 /*----------------------------------------------------------------------------
1727  * falc_pattern_test_error
1728  *----------------------------------------------------------------------------
1729  * Description: This routine returns the bit error counter value
1730  *----------------------------------------------------------------------------
1731  */
1732 static u16 falc_pattern_test_error(pc300_t * card, int ch)
1733 {
1734  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1735  falc_t *pfalc = (falc_t *) & chan->falc;
1736 
1737  return pfalc->bec;
1738 }
1739 
1740 /**********************************/
1741 /*** Net Interface Routines ***/
1742 /**********************************/
1743 
1744 static void
1745 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1746 {
1747  struct sk_buff *skb;
1748 
1749  if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1750  printk("%s: out of memory\n", dev->name);
1751  return;
1752  }
1753  skb_put(skb, 10 + skb_main->len);
1754 
1755  skb->dev = dev;
1756  skb->protocol = htons(ETH_P_CUST);
1757  skb_reset_mac_header(skb);
1758  skb->pkt_type = PACKET_HOST;
1759  skb->len = 10 + skb_main->len;
1760 
1761  skb_copy_to_linear_data(skb, dev->name, 5);
1762  skb->data[5] = '[';
1763  skb->data[6] = rx_tx;
1764  skb->data[7] = ']';
1765  skb->data[8] = ':';
1766  skb->data[9] = ' ';
1767  skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1768 
1769  netif_rx(skb);
1770 }
1771 
1772 static void cpc_tx_timeout(struct net_device *dev)
1773 {
1774  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1775  pc300ch_t *chan = (pc300ch_t *) d->chan;
1776  pc300_t *card = (pc300_t *) chan->card;
1777  int ch = chan->channel;
1778  unsigned long flags;
1779  u8 ilar;
1780 
1781  dev->stats.tx_errors++;
1782  dev->stats.tx_aborted_errors++;
1783  CPC_LOCK(card, flags);
1784  if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1785  printk("%s: ILAR=0x%x\n", dev->name, ilar);
1786  cpc_writeb(card->hw.scabase + ILAR, ilar);
1787  cpc_writeb(card->hw.scabase + DMER, 0x80);
1788  }
1789  if (card->hw.type == PC300_TE) {
1790  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1791  cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1792  ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1793  }
1794  dev->trans_start = jiffies; /* prevent tx timeout */
1795  CPC_UNLOCK(card, flags);
1796  netif_wake_queue(dev);
1797 }
1798 
1799 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1800 {
1801  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1802  pc300ch_t *chan = (pc300ch_t *) d->chan;
1803  pc300_t *card = (pc300_t *) chan->card;
1804  int ch = chan->channel;
1805  unsigned long flags;
1806 #ifdef PC300_DEBUG_TX
1807  int i;
1808 #endif
1809 
1810  if (!netif_carrier_ok(dev)) {
1811  /* DCD must be OFF: drop packet */
1812  dev_kfree_skb(skb);
1813  dev->stats.tx_errors++;
1814  dev->stats.tx_carrier_errors++;
1815  return 0;
1816  } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1817  printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1818  dev->stats.tx_errors++;
1819  dev->stats.tx_carrier_errors++;
1820  dev_kfree_skb(skb);
1821  netif_carrier_off(dev);
1822  CPC_LOCK(card, flags);
1823  cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1824  if (card->hw.type == PC300_TE) {
1825  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1826  cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1827  ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1828  }
1829  CPC_UNLOCK(card, flags);
1830  netif_wake_queue(dev);
1831  return 0;
1832  }
1833 
1834  /* Write buffer to DMA buffers */
1835  if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1836 // printk("%s: write error. Dropping TX packet.\n", dev->name);
1837  netif_stop_queue(dev);
1838  dev_kfree_skb(skb);
1839  dev->stats.tx_errors++;
1840  dev->stats.tx_dropped++;
1841  return 0;
1842  }
1843 #ifdef PC300_DEBUG_TX
1844  printk("%s T:", dev->name);
1845  for (i = 0; i < skb->len; i++)
1846  printk(" %02x", *(skb->data + i));
1847  printk("\n");
1848 #endif
1849 
1850  if (d->trace_on) {
1851  cpc_trace(dev, skb, 'T');
1852  }
1853 
1854  /* Start transmission */
1855  CPC_LOCK(card, flags);
1856  /* verify if it has more than one free descriptor */
1857  if (card->chan[ch].nfree_tx_bd <= 1) {
1858  /* don't have so stop the queue */
1859  netif_stop_queue(dev);
1860  }
1861  cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1862  TX_BD_ADDR(ch, chan->tx_next_bd));
1863  cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1864  cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1865  if (card->hw.type == PC300_TE) {
1866  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1867  cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1868  (CPLD_REG2_FALC_LED1 << (2 * ch)));
1869  }
1870  CPC_UNLOCK(card, flags);
1871  dev_kfree_skb(skb);
1872 
1873  return 0;
1874 }
1875 
1876 static void cpc_net_rx(struct net_device *dev)
1877 {
1878  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1879  pc300ch_t *chan = (pc300ch_t *) d->chan;
1880  pc300_t *card = (pc300_t *) chan->card;
1881  int ch = chan->channel;
1882 #ifdef PC300_DEBUG_RX
1883  int i;
1884 #endif
1885  int rxb;
1886  struct sk_buff *skb;
1887 
1888  while (1) {
1889  if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1890  return;
1891 
1892  if (!netif_carrier_ok(dev)) {
1893  /* DCD must be OFF: drop packet */
1894  printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1895  skb = NULL;
1896  } else {
1897  if (rxb > (dev->mtu + 40)) { /* add headers */
1898  printk("%s : MTU exceeded %d\n", dev->name, rxb);
1899  skb = NULL;
1900  } else {
1901  skb = dev_alloc_skb(rxb);
1902  if (skb == NULL) {
1903  printk("%s: Memory squeeze!!\n", dev->name);
1904  return;
1905  }
1906  skb->dev = dev;
1907  }
1908  }
1909 
1910  if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1911 #ifdef PC300_DEBUG_RX
1912  printk("%s: rxb = %x\n", dev->name, rxb);
1913 #endif
1914  if ((skb == NULL) && (rxb > 0)) {
1915  /* rxb > dev->mtu */
1916  dev->stats.rx_errors++;
1917  dev->stats.rx_length_errors++;
1918  continue;
1919  }
1920 
1921  if (rxb < 0) { /* Invalid frame */
1922  rxb = -rxb;
1923  if (rxb & DST_OVR) {
1924  dev->stats.rx_errors++;
1925  dev->stats.rx_fifo_errors++;
1926  }
1927  if (rxb & DST_CRC) {
1928  dev->stats.rx_errors++;
1929  dev->stats.rx_crc_errors++;
1930  }
1931  if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1932  dev->stats.rx_errors++;
1933  dev->stats.rx_frame_errors++;
1934  }
1935  }
1936  if (skb) {
1937  dev_kfree_skb_irq(skb);
1938  }
1939  continue;
1940  }
1941 
1942  dev->stats.rx_bytes += rxb;
1943 
1944 #ifdef PC300_DEBUG_RX
1945  printk("%s R:", dev->name);
1946  for (i = 0; i < skb->len; i++)
1947  printk(" %02x", *(skb->data + i));
1948  printk("\n");
1949 #endif
1950  if (d->trace_on) {
1951  cpc_trace(dev, skb, 'R');
1952  }
1953  dev->stats.rx_packets++;
1954  skb->protocol = hdlc_type_trans(skb, dev);
1955  netif_rx(skb);
1956  }
1957 }
1958 
1959 /************************************/
1960 /*** PC300 Interrupt Routines ***/
1961 /************************************/
1962 static void sca_tx_intr(pc300dev_t *dev)
1963 {
1964  pc300ch_t *chan = (pc300ch_t *)dev->chan;
1965  pc300_t *card = (pc300_t *)chan->card;
1966  int ch = chan->channel;
1967  volatile pcsca_bd_t __iomem * ptdescr;
1968 
1969  /* Clean up descriptors from previous transmission */
1970  ptdescr = (card->hw.rambase +
1971  TX_BD_ADDR(ch,chan->tx_first_bd));
1972  while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1973  TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1974  (cpc_readb(&ptdescr->status) & DST_OSB)) {
1975  dev->dev->stats.tx_packets++;
1976  dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1977  cpc_writeb(&ptdescr->status, DST_OSB);
1978  cpc_writew(&ptdescr->len, 0);
1979  chan->nfree_tx_bd++;
1980  chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1981  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1982  }
1983 
1984 #ifdef CONFIG_PC300_MLPPP
1985  if (chan->conf.proto == PC300_PROTO_MLPPP) {
1986  cpc_tty_trigger_poll(dev);
1987  } else {
1988 #endif
1989  /* Tell the upper layer we are ready to transmit more packets */
1990  netif_wake_queue(dev->dev);
1991 #ifdef CONFIG_PC300_MLPPP
1992  }
1993 #endif
1994 }
1995 
1996 static void sca_intr(pc300_t * card)
1997 {
1998  void __iomem *scabase = card->hw.scabase;
1999  volatile u32 status;
2000  int ch;
2001  int intr_count = 0;
2002  unsigned char dsr_rx;
2003 
2004  while ((status = cpc_readl(scabase + ISR0)) != 0) {
2005  for (ch = 0; ch < card->hw.nchan; ch++) {
2006  pc300ch_t *chan = &card->chan[ch];
2007  pc300dev_t *d = &chan->d;
2008  struct net_device *dev = d->dev;
2009 
2010  spin_lock(&card->card_lock);
2011 
2012  /**** Reception ****/
2013  if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2014  u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
2015 
2016  /* Clear RX interrupts */
2017  cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2018 
2019 #ifdef PC300_DEBUG_INTR
2020  printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2021  ch, status, drx_stat);
2022 #endif
2023  if (status & IR0_DRX(IR0_DMIA, ch)) {
2024  if (drx_stat & DSR_BOF) {
2025 #ifdef CONFIG_PC300_MLPPP
2026  if (chan->conf.proto == PC300_PROTO_MLPPP) {
2027  /* verify if driver is TTY */
2028  if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2029  rx_dma_stop(card, ch);
2030  }
2031  cpc_tty_receive(d);
2032  rx_dma_start(card, ch);
2033  } else
2034 #endif
2035  {
2036  if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2037  rx_dma_stop(card, ch);
2038  }
2039  cpc_net_rx(dev);
2040  /* Discard invalid frames */
2041  dev->stats.rx_errors++;
2042  dev->stats.rx_over_errors++;
2043  chan->rx_first_bd = 0;
2044  chan->rx_last_bd = N_DMA_RX_BUF - 1;
2045  rx_dma_start(card, ch);
2046  }
2047  }
2048  }
2049  if (status & IR0_DRX(IR0_DMIB, ch)) {
2050  if (drx_stat & DSR_EOM) {
2051  if (card->hw.type == PC300_TE) {
2052  cpc_writeb(card->hw.falcbase +
2053  card->hw.cpld_reg2,
2054  cpc_readb (card->hw.falcbase +
2055  card->hw.cpld_reg2) |
2056  (CPLD_REG2_FALC_LED1 << (2 * ch)));
2057  }
2058 #ifdef CONFIG_PC300_MLPPP
2059  if (chan->conf.proto == PC300_PROTO_MLPPP) {
2060  /* verify if driver is TTY */
2061  cpc_tty_receive(d);
2062  } else {
2063  cpc_net_rx(dev);
2064  }
2065 #else
2066  cpc_net_rx(dev);
2067 #endif
2068  if (card->hw.type == PC300_TE) {
2069  cpc_writeb(card->hw.falcbase +
2070  card->hw.cpld_reg2,
2071  cpc_readb (card->hw.falcbase +
2072  card->hw.cpld_reg2) &
2073  ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2074  }
2075  }
2076  }
2077  if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2078 #ifdef PC300_DEBUG_INTR
2079  printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2080  dev->name, ch, status, drx_stat, dsr_rx);
2081 #endif
2082  cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2083  }
2084  }
2085 
2086  /**** Transmission ****/
2087  if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2088  u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2089 
2090  /* Clear TX interrupts */
2091  cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2092 
2093 #ifdef PC300_DEBUG_INTR
2094  printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2095  ch, status, dtx_stat);
2096 #endif
2097  if (status & IR0_DTX(IR0_EFT, ch)) {
2098  if (dtx_stat & DSR_UDRF) {
2099  if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2100  cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2101  }
2102  if (card->hw.type == PC300_TE) {
2103  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2104  cpc_readb (card->hw.falcbase +
2105  card->hw.cpld_reg2) &
2106  ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2107  }
2108  dev->stats.tx_errors++;
2109  dev->stats.tx_fifo_errors++;
2110  sca_tx_intr(d);
2111  }
2112  }
2113  if (status & IR0_DTX(IR0_DMIA, ch)) {
2114  if (dtx_stat & DSR_BOF) {
2115  }
2116  }
2117  if (status & IR0_DTX(IR0_DMIB, ch)) {
2118  if (dtx_stat & DSR_EOM) {
2119  if (card->hw.type == PC300_TE) {
2120  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2121  cpc_readb (card->hw.falcbase +
2122  card->hw.cpld_reg2) &
2123  ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2124  }
2125  sca_tx_intr(d);
2126  }
2127  }
2128  }
2129 
2130  /**** MSCI ****/
2131  if (status & IR0_M(IR0_RXINTA, ch)) {
2132  u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
2133 
2134  /* Clear MSCI interrupts */
2135  cpc_writeb(scabase + M_REG(ST1, ch), st1);
2136 
2137 #ifdef PC300_DEBUG_INTR
2138  printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2139  ch, status, st1);
2140 #endif
2141  if (st1 & ST1_CDCD) { /* DCD changed */
2142  if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2143  printk ("%s: DCD is OFF. Going administrative down.\n",
2144  dev->name);
2145 #ifdef CONFIG_PC300_MLPPP
2146  if (chan->conf.proto != PC300_PROTO_MLPPP) {
2147  netif_carrier_off(dev);
2148  }
2149 #else
2150  netif_carrier_off(dev);
2151 
2152 #endif
2153  card->chan[ch].d.line_off++;
2154  } else { /* DCD = 1 */
2155  printk ("%s: DCD is ON. Going administrative up.\n",
2156  dev->name);
2157 #ifdef CONFIG_PC300_MLPPP
2158  if (chan->conf.proto != PC300_PROTO_MLPPP)
2159  /* verify if driver is not TTY */
2160 #endif
2161  netif_carrier_on(dev);
2162  card->chan[ch].d.line_on++;
2163  }
2164  }
2165  }
2166  spin_unlock(&card->card_lock);
2167  }
2168  if (++intr_count == 10)
2169  /* Too much work at this board. Force exit */
2170  break;
2171  }
2172 }
2173 
2174 static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
2175 {
2176  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2177  falc_t *pfalc = (falc_t *) & chan->falc;
2178  void __iomem *falcbase = card->hw.falcbase;
2179 
2180  if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2181  !pfalc->loop_gen) {
2182  if (frs1 & FRS1_LLBDD) {
2183  // A Line Loop Back Deactivation signal detected
2184  if (pfalc->loop_active) {
2185  falc_remote_loop(card, ch, 0);
2186  }
2187  } else {
2188  if ((frs1 & FRS1_LLBAD) &&
2189  ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2190  // A Line Loop Back Activation signal detected
2191  if (!pfalc->loop_active) {
2192  falc_remote_loop(card, ch, 1);
2193  }
2194  }
2195  }
2196  }
2197 }
2198 
2199 static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
2200 {
2201  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2202  falc_t *pfalc = (falc_t *) & chan->falc;
2203  void __iomem *falcbase = card->hw.falcbase;
2204 
2205  if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2206  !pfalc->loop_gen) {
2207  if (rsp & RSP_LLBDD) {
2208  // A Line Loop Back Deactivation signal detected
2209  if (pfalc->loop_active) {
2210  falc_remote_loop(card, ch, 0);
2211  }
2212  } else {
2213  if ((rsp & RSP_LLBAD) &&
2214  ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2215  // A Line Loop Back Activation signal detected
2216  if (!pfalc->loop_active) {
2217  falc_remote_loop(card, ch, 1);
2218  }
2219  }
2220  }
2221  }
2222 }
2223 
2224 static void falc_t1_intr(pc300_t * card, int ch)
2225 {
2226  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2227  falc_t *pfalc = (falc_t *) & chan->falc;
2228  void __iomem *falcbase = card->hw.falcbase;
2229  u8 isr0, isr3, gis;
2230  u8 dummy;
2231 
2232  while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2233  if (gis & GIS_ISR0) {
2234  isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2235  if (isr0 & FISR0_PDEN) {
2236  /* Read the bit to clear the situation */
2237  if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2238  FRS1_PDEN) {
2239  pfalc->pden++;
2240  }
2241  }
2242  }
2243 
2244  if (gis & GIS_ISR1) {
2245  dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2246  }
2247 
2248  if (gis & GIS_ISR2) {
2249  dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2250  }
2251 
2252  if (gis & GIS_ISR3) {
2253  isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2254  if (isr3 & FISR3_SEC) {
2255  pfalc->sec++;
2256  falc_update_stats(card, ch);
2257  falc_check_status(card, ch,
2258  cpc_readb(falcbase + F_REG(FRS0, ch)));
2259  }
2260  if (isr3 & FISR3_ES) {
2261  pfalc->es++;
2262  }
2263  if (isr3 & FISR3_LLBSC) {
2264  falc_t1_loop_detection(card, ch,
2265  cpc_readb(falcbase + F_REG(FRS1, ch)));
2266  }
2267  }
2268  }
2269 }
2270 
2271 static void falc_e1_intr(pc300_t * card, int ch)
2272 {
2273  pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2274  falc_t *pfalc = (falc_t *) & chan->falc;
2275  void __iomem *falcbase = card->hw.falcbase;
2276  u8 isr1, isr2, isr3, gis, rsp;
2277  u8 dummy;
2278 
2279  while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2280  rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2281 
2282  if (gis & GIS_ISR0) {
2283  dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2284  }
2285  if (gis & GIS_ISR1) {
2286  isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2287  if (isr1 & FISR1_XMB) {
2288  if ((pfalc->xmb_cause & 2) &&
2289  pfalc->multiframe_mode) {
2290  if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2291  (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2292  cpc_writeb(falcbase + F_REG(XSP, ch),
2293  cpc_readb(falcbase + F_REG(XSP, ch))
2294  & ~XSP_AXS);
2295  } else {
2296  cpc_writeb(falcbase + F_REG(XSP, ch),
2297  cpc_readb(falcbase + F_REG(XSP, ch))
2298  | XSP_AXS);
2299  }
2300  }
2301  pfalc->xmb_cause = 0;
2302  cpc_writeb(falcbase + F_REG(IMR1, ch),
2303  cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2304  }
2305  if (isr1 & FISR1_LLBSC) {
2306  falc_e1_loop_detection(card, ch, rsp);
2307  }
2308  }
2309  if (gis & GIS_ISR2) {
2310  isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2311  if (isr2 & FISR2_T400MS) {
2312  cpc_writeb(falcbase + F_REG(XSW, ch),
2313  cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2314  }
2315  if (isr2 & FISR2_MFAR) {
2316  cpc_writeb(falcbase + F_REG(XSW, ch),
2317  cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2318  }
2319  if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2320  pfalc->xmb_cause |= 2;
2321  cpc_writeb(falcbase + F_REG(IMR1, ch),
2322  cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2323  }
2324  }
2325  if (gis & GIS_ISR3) {
2326  isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2327  if (isr3 & FISR3_SEC) {
2328  pfalc->sec++;
2329  falc_update_stats(card, ch);
2330  falc_check_status(card, ch,
2331  cpc_readb(falcbase + F_REG(FRS0, ch)));
2332  }
2333  if (isr3 & FISR3_ES) {
2334  pfalc->es++;
2335  }
2336  }
2337  }
2338 }
2339 
2340 static void falc_intr(pc300_t * card)
2341 {
2342  int ch;
2343 
2344  for (ch = 0; ch < card->hw.nchan; ch++) {
2345  pc300ch_t *chan = &card->chan[ch];
2346  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2347 
2348  if (conf->media == IF_IFACE_T1) {
2349  falc_t1_intr(card, ch);
2350  } else {
2351  falc_e1_intr(card, ch);
2352  }
2353  }
2354 }
2355 
2356 static irqreturn_t cpc_intr(int irq, void *dev_id)
2357 {
2358  pc300_t *card = dev_id;
2359  volatile u8 plx_status;
2360 
2361  if (!card) {
2362 #ifdef PC300_DEBUG_INTR
2363  printk("cpc_intr: spurious intr %d\n", irq);
2364 #endif
2365  return IRQ_NONE; /* spurious intr */
2366  }
2367 
2368  if (!card->hw.rambase) {
2369 #ifdef PC300_DEBUG_INTR
2370  printk("cpc_intr: spurious intr2 %d\n", irq);
2371 #endif
2372  return IRQ_NONE; /* spurious intr */
2373  }
2374 
2375  switch (card->hw.type) {
2376  case PC300_RSV:
2377  case PC300_X21:
2378  sca_intr(card);
2379  break;
2380 
2381  case PC300_TE:
2382  while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2383  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2384  if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2385  sca_intr(card);
2386  }
2387  if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2388  falc_intr(card);
2389  }
2390  }
2391  break;
2392  }
2393  return IRQ_HANDLED;
2394 }
2395 
2396 static void cpc_sca_status(pc300_t * card, int ch)
2397 {
2398  u8 ilar;
2399  void __iomem *scabase = card->hw.scabase;
2400  unsigned long flags;
2401 
2402  tx_dma_buf_check(card, ch);
2403  rx_dma_buf_check(card, ch);
2404  ilar = cpc_readb(scabase + ILAR);
2405  printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2406  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2407  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2408  printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2409  cpc_readl(scabase + DTX_REG(CDAL, ch)),
2410  cpc_readl(scabase + DTX_REG(EDAL, ch)));
2411  printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2412  cpc_readl(scabase + DRX_REG(CDAL, ch)),
2413  cpc_readl(scabase + DRX_REG(EDAL, ch)),
2414  cpc_readw(scabase + DRX_REG(BFLL, ch)));
2415  printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2416  cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2417  cpc_readb(scabase + DSR_RX(ch)));
2418  printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2419  cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2420  cpc_readb(scabase + DIR_TX(ch)),
2421  cpc_readb(scabase + DIR_RX(ch)));
2422  printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2423  cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2424  cpc_readb(scabase + FCT_TX(ch)),
2425  cpc_readb(scabase + FCT_RX(ch)));
2426  printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2427  cpc_readb(scabase + M_REG(MD0, ch)),
2428  cpc_readb(scabase + M_REG(MD1, ch)),
2429  cpc_readb(scabase + M_REG(MD2, ch)),
2430  cpc_readb(scabase + M_REG(MD3, ch)),
2431  cpc_readb(scabase + M_REG(IDL, ch)));
2432  printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2433  cpc_readb(scabase + M_REG(CMD, ch)),
2434  cpc_readb(scabase + M_REG(SA0, ch)),
2435  cpc_readb(scabase + M_REG(SA1, ch)),
2436  cpc_readb(scabase + M_REG(TFN, ch)),
2437  cpc_readb(scabase + M_REG(CTL, ch)));
2438  printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2439  cpc_readb(scabase + M_REG(ST0, ch)),
2440  cpc_readb(scabase + M_REG(ST1, ch)),
2441  cpc_readb(scabase + M_REG(ST2, ch)),
2442  cpc_readb(scabase + M_REG(ST3, ch)),
2443  cpc_readb(scabase + M_REG(ST4, ch)));
2444  printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2445  cpc_readb(scabase + M_REG(CST0, ch)),
2446  cpc_readb(scabase + M_REG(CST1, ch)),
2447  cpc_readb(scabase + M_REG(CST2, ch)),
2448  cpc_readb(scabase + M_REG(CST3, ch)),
2449  cpc_readb(scabase + M_REG(FST, ch)));
2450  printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2451  cpc_readb(scabase + M_REG(TRC0, ch)),
2452  cpc_readb(scabase + M_REG(TRC1, ch)),
2453  cpc_readb(scabase + M_REG(RRC, ch)),
2454  cpc_readb(scabase + M_REG(TBN, ch)),
2455  cpc_readb(scabase + M_REG(RBN, ch)));
2456  printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2457  cpc_readb(scabase + M_REG(TFS, ch)),
2458  cpc_readb(scabase + M_REG(TNR0, ch)),
2459  cpc_readb(scabase + M_REG(TNR1, ch)),
2460  cpc_readb(scabase + M_REG(RNR, ch)));
2461  printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2462  cpc_readb(scabase + M_REG(TCR, ch)),
2463  cpc_readb(scabase + M_REG(RCR, ch)),
2464  cpc_readb(scabase + M_REG(TNR1, ch)),
2465  cpc_readb(scabase + M_REG(RNR, ch)));
2466  printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2467  cpc_readb(scabase + M_REG(TXS, ch)),
2468  cpc_readb(scabase + M_REG(RXS, ch)),
2469  cpc_readb(scabase + M_REG(EXS, ch)),
2470  cpc_readb(scabase + M_REG(TMCT, ch)),
2471  cpc_readb(scabase + M_REG(TMCR, ch)));
2472  printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2473  cpc_readb(scabase + M_REG(IE0, ch)),
2474  cpc_readb(scabase + M_REG(IE1, ch)),
2475  cpc_readb(scabase + M_REG(IE2, ch)),
2476  cpc_readb(scabase + M_REG(IE4, ch)),
2477  cpc_readb(scabase + M_REG(FIE, ch)));
2478  printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2479 
2480  if (ilar != 0) {
2481  CPC_LOCK(card, flags);
2482  cpc_writeb(scabase + ILAR, ilar);
2483  cpc_writeb(scabase + DMER, 0x80);
2484  CPC_UNLOCK(card, flags);
2485  }
2486 }
2487 
2488 static void cpc_falc_status(pc300_t * card, int ch)
2489 {
2490  pc300ch_t *chan = &card->chan[ch];
2491  falc_t *pfalc = (falc_t *) & chan->falc;
2492  unsigned long flags;
2493 
2494  CPC_LOCK(card, flags);
2495  printk("CH%d: %s %s %d channels\n",
2496  ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2497  pfalc->num_channels);
2498 
2499  printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2500  pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2501  printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2502  pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2503  printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2504  pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2505 
2506  printk("\n");
2507  printk(" STATUS: %s %s %s %s %s %s\n",
2508  (pfalc->red_alarm ? "RED" : ""),
2509  (pfalc->blue_alarm ? "BLU" : ""),
2510  (pfalc->yellow_alarm ? "YEL" : ""),
2511  (pfalc->loss_fa ? "LFA" : ""),
2512  (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2513  CPC_UNLOCK(card, flags);
2514 }
2515 
2516 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2517 {
2518  if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2519  return -EINVAL;
2520  dev->mtu = new_mtu;
2521  return 0;
2522 }
2523 
2524 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2525 {
2526  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
2527  pc300ch_t *chan = (pc300ch_t *) d->chan;
2528  pc300_t *card = (pc300_t *) chan->card;
2529  pc300conf_t conf_aux;
2530  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2531  int ch = chan->channel;
2532  void __user *arg = ifr->ifr_data;
2533  struct if_settings *settings = &ifr->ifr_settings;
2534  void __iomem *scabase = card->hw.scabase;
2535 
2536  if (!capable(CAP_NET_ADMIN))
2537  return -EPERM;
2538 
2539  switch (cmd) {
2540  case SIOCGPC300CONF:
2541 #ifdef CONFIG_PC300_MLPPP
2542  if (conf->proto != PC300_PROTO_MLPPP) {
2543  conf->proto = /* FIXME hdlc->proto.id */ 0;
2544  }
2545 #else
2546  conf->proto = /* FIXME hdlc->proto.id */ 0;
2547 #endif
2548  memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2549  memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2550  if (!arg ||
2551  copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2552  return -EINVAL;
2553  return 0;
2554  case SIOCSPC300CONF:
2555  if (!capable(CAP_NET_ADMIN))
2556  return -EPERM;
2557  if (!arg ||
2558  copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2559  return -EINVAL;
2560  if (card->hw.cpld_id < 0x02 &&
2561  conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2562  /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2563  return -EINVAL;
2564  }
2565 #ifdef CONFIG_PC300_MLPPP
2566  if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2567  if (conf->proto != PC300_PROTO_MLPPP) {
2568  memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2569  cpc_tty_init(d); /* init TTY driver */
2570  }
2571  } else {
2572  if (conf_aux.conf.proto == 0xffff) {
2573  if (conf->proto == PC300_PROTO_MLPPP){
2574  /* ifdown interface */
2575  cpc_close(dev);
2576  }
2577  } else {
2578  memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2579  /* FIXME hdlc->proto.id = conf->proto; */
2580  }
2581  }
2582 #else
2583  memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2584  /* FIXME hdlc->proto.id = conf->proto; */
2585 #endif
2586  return 0;
2587  case SIOCGPC300STATUS:
2588  cpc_sca_status(card, ch);
2589  return 0;
2590  case SIOCGPC300FALCSTATUS:
2591  cpc_falc_status(card, ch);
2592  return 0;
2593 
2594  case SIOCGPC300UTILSTATS:
2595  {
2596  if (!arg) { /* clear statistics */
2597  memset(&dev->stats, 0, sizeof(dev->stats));
2598  if (card->hw.type == PC300_TE) {
2599  memset(&chan->falc, 0, sizeof(falc_t));
2600  }
2601  } else {
2602  pc300stats_t pc300stats;
2603 
2604  memset(&pc300stats, 0, sizeof(pc300stats_t));
2605  pc300stats.hw_type = card->hw.type;
2606  pc300stats.line_on = card->chan[ch].d.line_on;
2607  pc300stats.line_off = card->chan[ch].d.line_off;
2608  memcpy(&pc300stats.gen_stats, &dev->stats,
2609  sizeof(dev->stats));
2610  if (card->hw.type == PC300_TE)
2611  memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2612  if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2613  return -EFAULT;
2614  }
2615  return 0;
2616  }
2617 
2618  case SIOCGPC300UTILSTATUS:
2619  {
2620  struct pc300status pc300status;
2621 
2622  pc300status.hw_type = card->hw.type;
2623  if (card->hw.type == PC300_TE) {
2624  pc300status.te_status.sync = chan->falc.sync;
2625  pc300status.te_status.red_alarm = chan->falc.red_alarm;
2626  pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2627  pc300status.te_status.loss_fa = chan->falc.loss_fa;
2628  pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2629  pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2630  pc300status.te_status.prbs = chan->falc.prbs;
2631  } else {
2632  pc300status.gen_status.dcd =
2633  !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2634  pc300status.gen_status.cts =
2635  !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2636  pc300status.gen_status.rts =
2637  !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2638  pc300status.gen_status.dtr =
2639  !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2640  /* There is no DSR in HD64572 */
2641  }
2642  if (!arg ||
2643  copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2644  return -EINVAL;
2645  return 0;
2646  }
2647 
2648  case SIOCSPC300TRACE:
2649  /* Sets/resets a trace_flag for the respective device */
2650  if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2651  return -EINVAL;
2652  return 0;
2653 
2654  case SIOCSPC300LOOPBACK:
2655  {
2656  struct pc300loopback pc300loop;
2657 
2658  /* TE boards only */
2659  if (card->hw.type != PC300_TE)
2660  return -EINVAL;
2661 
2662  if (!arg ||
2663  copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2664  return -EINVAL;
2665  switch (pc300loop.loop_type) {
2666  case PC300LOCLOOP: /* Turn the local loop on/off */
2667  falc_local_loop(card, ch, pc300loop.loop_on);
2668  return 0;
2669 
2670  case PC300REMLOOP: /* Turn the remote loop on/off */
2671  falc_remote_loop(card, ch, pc300loop.loop_on);
2672  return 0;
2673 
2674  case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2675  falc_payload_loop(card, ch, pc300loop.loop_on);
2676  return 0;
2677 
2678  case PC300GENLOOPUP: /* Generate loop UP */
2679  if (pc300loop.loop_on) {
2680  falc_generate_loop_up_code (card, ch);
2681  } else {
2682  turn_off_xlu(card, ch);
2683  }
2684  return 0;
2685 
2686  case PC300GENLOOPDOWN: /* Generate loop DOWN */
2687  if (pc300loop.loop_on) {
2688  falc_generate_loop_down_code (card, ch);
2689  } else {
2690  turn_off_xld(card, ch);
2691  }
2692  return 0;
2693 
2694  default:
2695  return -EINVAL;
2696  }
2697  }
2698 
2699  case SIOCSPC300PATTERNTEST:
2700  /* Turn the pattern test on/off and show the errors counter */
2701  {
2702  struct pc300patterntst pc300patrntst;
2703 
2704  /* TE boards only */
2705  if (card->hw.type != PC300_TE)
2706  return -EINVAL;
2707 
2708  if (card->hw.cpld_id < 0x02) {
2709  /* CPLD_ID < 0x02 doesn't support pattern test */
2710  return -EINVAL;
2711  }
2712 
2713  if (!arg ||
2714  copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2715  return -EINVAL;
2716  if (pc300patrntst.patrntst_on == 2) {
2717  if (chan->falc.prbs == 0) {
2718  falc_pattern_test(card, ch, 1);
2719  }
2720  pc300patrntst.num_errors =
2721  falc_pattern_test_error(card, ch);
2722  if (copy_to_user(arg, &pc300patrntst,
2723  sizeof(pc300patterntst_t)))
2724  return -EINVAL;
2725  } else {
2726  falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2727  }
2728  return 0;
2729  }
2730 
2731  case SIOCWANDEV:
2732  switch (ifr->ifr_settings.type) {
2733  case IF_GET_IFACE:
2734  {
2735  const size_t size = sizeof(sync_serial_settings);
2736  ifr->ifr_settings.type = conf->media;
2737  if (ifr->ifr_settings.size < size) {
2738  /* data size wanted */
2739  ifr->ifr_settings.size = size;
2740  return -ENOBUFS;
2741  }
2742 
2743  if (copy_to_user(settings->ifs_ifsu.sync,
2744  &conf->phys_settings, size)) {
2745  return -EFAULT;
2746  }
2747  return 0;
2748  }
2749 
2750  case IF_IFACE_V35:
2751  case IF_IFACE_V24:
2752  case IF_IFACE_X21:
2753  {
2754  const size_t size = sizeof(sync_serial_settings);
2755 
2756  if (!capable(CAP_NET_ADMIN)) {
2757  return -EPERM;
2758  }
2759  /* incorrect data len? */
2760  if (ifr->ifr_settings.size != size) {
2761  return -ENOBUFS;
2762  }
2763 
2764  if (copy_from_user(&conf->phys_settings,
2765  settings->ifs_ifsu.sync, size)) {
2766  return -EFAULT;
2767  }
2768 
2769  if (conf->phys_settings.loopback) {
2770  cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2771  cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2772  MD2_LOOP_MIR);
2773  }
2774  conf->media = ifr->ifr_settings.type;
2775  return 0;
2776  }
2777 
2778  case IF_IFACE_T1:
2779  case IF_IFACE_E1:
2780  {
2781  const size_t te_size = sizeof(te1_settings);
2782  const size_t size = sizeof(sync_serial_settings);
2783 
2784  if (!capable(CAP_NET_ADMIN)) {
2785  return -EPERM;
2786  }
2787 
2788  /* incorrect data len? */
2789  if (ifr->ifr_settings.size != te_size) {
2790  return -ENOBUFS;
2791  }
2792 
2793  if (copy_from_user(&conf->phys_settings,
2794  settings->ifs_ifsu.te1, size)) {
2795  return -EFAULT;
2796  }/* Ignoring HDLC slot_map for a while */
2797 
2798  if (conf->phys_settings.loopback) {
2799  cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2800  cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2801  MD2_LOOP_MIR);
2802  }
2803  conf->media = ifr->ifr_settings.type;
2804  return 0;
2805  }
2806  default:
2807  return hdlc_ioctl(dev, ifr, cmd);
2808  }
2809 
2810  default:
2811  return hdlc_ioctl(dev, ifr, cmd);
2812  }
2813 }
2814 
2815 static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
2816 {
2817  int br, tc;
2818  int br_pwr, error;
2819 
2820  *br_io = 0;
2821 
2822  if (rate == 0)
2823  return 0;
2824 
2825  for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2826  if ((tc = clock / br_pwr / rate) <= 0xff) {
2827  *br_io = br;
2828  break;
2829  }
2830  }
2831 
2832  if (tc <= 0xff) {
2833  error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2834  /* Errors bigger than +/- 1% won't be tolerated */
2835  if (error < -10 || error > 10)
2836  return -1;
2837  else
2838  return tc;
2839  } else {
2840  return -1;
2841  }
2842 }
2843 
2844 static int ch_config(pc300dev_t * d)
2845 {
2846  pc300ch_t *chan = (pc300ch_t *) d->chan;
2847  pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2848  pc300_t *card = (pc300_t *) chan->card;
2849  void __iomem *scabase = card->hw.scabase;
2850  void __iomem *plxbase = card->hw.plxbase;
2851  int ch = chan->channel;
2852  u32 clkrate = chan->conf.phys_settings.clock_rate;
2853  u32 clktype = chan->conf.phys_settings.clock_type;
2854  u16 encoding = chan->conf.proto_settings.encoding;
2855  u16 parity = chan->conf.proto_settings.parity;
2856  u8 md0, md2;
2857 
2858  /* Reset the channel */
2859  cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2860 
2861  /* Configure the SCA registers */
2862  switch (parity) {
2863  case PARITY_NONE:
2864  md0 = MD0_BIT_SYNC;
2865  break;
2866  case PARITY_CRC16_PR0:
2867  md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2868  break;
2869  case PARITY_CRC16_PR1:
2870  md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2871  break;
2872  case PARITY_CRC32_PR1_CCITT:
2873  md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2874  break;
2875  case PARITY_CRC16_PR1_CCITT:
2876  default:
2877  md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2878  break;
2879  }
2880  switch (encoding) {
2881  case ENCODING_NRZI:
2882  md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2883  break;
2884  case ENCODING_FM_MARK: /* FM1 */
2885  md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2886  break;
2887  case ENCODING_FM_SPACE: /* FM0 */
2888  md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2889  break;
2890  case ENCODING_MANCHESTER: /* It's not working... */
2891  md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2892  break;
2893  case ENCODING_NRZ:
2894  default:
2895  md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2896  break;
2897  }
2898  cpc_writeb(scabase + M_REG(MD0, ch), md0);
2899  cpc_writeb(scabase + M_REG(MD1, ch), 0);
2900  cpc_writeb(scabase + M_REG(MD2, ch), md2);
2901  cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2902  cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2903 
2904  /* Configure HW media */
2905  switch (card->hw.type) {
2906  case PC300_RSV:
2907  if (conf->media == IF_IFACE_V35) {
2908  cpc_writel((plxbase + card->hw.gpioc_reg),
2909  cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2910  } else {
2911  cpc_writel((plxbase + card->hw.gpioc_reg),
2912  cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2913  }
2914  break;
2915 
2916  case PC300_X21:
2917  break;
2918 
2919  case PC300_TE:
2920  te_config(card, ch);
2921  break;
2922  }
2923 
2924  switch (card->hw.type) {
2925  case PC300_RSV:
2926  case PC300_X21:
2927  if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2928  int tmc, br;
2929 
2930  /* Calculate the clkrate parameters */
2931  tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2932  if (tmc < 0)
2933  return -EIO;
2934  cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2935  cpc_writeb(scabase + M_REG(TXS, ch),
2936  (TXS_DTRXC | TXS_IBRG | br));
2937  if (clktype == CLOCK_INT) {
2938  cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2939  cpc_writeb(scabase + M_REG(RXS, ch),
2940  (RXS_IBRG | br));
2941  } else {
2942  cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2943  cpc_writeb(scabase + M_REG(RXS, ch), 0);
2944  }
2945  if (card->hw.type == PC300_X21) {
2946  cpc_writeb(scabase + M_REG(GPO, ch), 1);
2947  cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2948  } else {
2949  cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2950  }
2951  } else {
2952  cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2953  if (clktype == CLOCK_EXT) {
2954  cpc_writeb(scabase + M_REG(TXS, ch),
2955  TXS_DTRXC);
2956  } else {
2957  cpc_writeb(scabase + M_REG(TXS, ch),
2958  TXS_DTRXC|TXS_RCLK);
2959  }
2960  cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2961  cpc_writeb(scabase + M_REG(RXS, ch), 0);
2962  if (card->hw.type == PC300_X21) {
2963  cpc_writeb(scabase + M_REG(GPO, ch), 0);
2964  cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2965  } else {
2966  cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2967  }
2968  }
2969  break;
2970 
2971  case PC300_TE:
2972  /* SCA always receives clock from the FALC chip */
2973  cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2974  cpc_writeb(scabase + M_REG(TXS, ch), 0);
2975  cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2976  cpc_writeb(scabase + M_REG(RXS, ch), 0);
2977  cpc_writeb(scabase + M_REG(EXS, ch), 0);
2978  break;
2979  }
2980 
2981  /* Enable Interrupts */
2982  cpc_writel(scabase + IER0,
2983  cpc_readl(scabase + IER0) |
2984  IR0_M(IR0_RXINTA, ch) |
2985  IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2986  IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2987  cpc_writeb(scabase + M_REG(IE0, ch),
2988  cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2989  cpc_writeb(scabase + M_REG(IE1, ch),
2990  cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2991 
2992  return 0;
2993 }
2994 
2995 static int rx_config(pc300dev_t * d)
2996 {
2997  pc300ch_t *chan = (pc300ch_t *) d->chan;
2998  pc300_t *card = (pc300_t *) chan->card;
2999  void __iomem *scabase = card->hw.scabase;
3000  int ch = chan->channel;
3001 
3002  cpc_writeb(scabase + DSR_RX(ch), 0);
3003 
3004  /* General RX settings */
3005  cpc_writeb(scabase + M_REG(RRC, ch), 0);
3006  cpc_writeb(scabase + M_REG(RNR, ch), 16);
3007 
3008  /* Enable reception */
3009  cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3010  cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3011 
3012  /* Initialize DMA stuff */
3013  chan->rx_first_bd = 0;
3014  chan->rx_last_bd = N_DMA_RX_BUF - 1;
3015  rx_dma_buf_init(card, ch);
3016  cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3017  cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3018  cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3019 
3020  /* Start DMA */
3021  rx_dma_start(card, ch);
3022 
3023  return 0;
3024 }
3025 
3026 static int tx_config(pc300dev_t * d)
3027 {
3028  pc300ch_t *chan = (pc300ch_t *) d->chan;
3029  pc300_t *card = (pc300_t *) chan->card;
3030  void __iomem *scabase = card->hw.scabase;
3031  int ch = chan->channel;
3032 
3033  cpc_writeb(scabase + DSR_TX(ch), 0);
3034 
3035  /* General TX settings */
3036  cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3037  cpc_writeb(scabase + M_REG(TFS, ch), 32);
3038  cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3039  cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3040  cpc_writeb(scabase + M_REG(TCR, ch), 8);
3041 
3042  /* Enable transmission */
3043  cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3044 
3045  /* Initialize DMA stuff */
3046  chan->tx_first_bd = 0;
3047  chan->tx_next_bd = 0;
3048  tx_dma_buf_init(card, ch);
3049  cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3050  cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3051  cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3052  cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3053  cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3054 
3055  return 0;
3056 }
3057 
3058 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3059  unsigned short parity)
3060 {
3061  pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
3062  pc300ch_t *chan = (pc300ch_t *)d->chan;
3063  pc300_t *card = (pc300_t *)chan->card;
3064  pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3065 
3066  if (card->hw.type == PC300_TE) {
3067  if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3068  return -EINVAL;
3069  }
3070  } else {
3071  if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3072  encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3073  /* Driver doesn't support ENCODING_MANCHESTER yet */
3074  return -EINVAL;
3075  }
3076  }
3077 
3078  if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3079  parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3080  parity != PARITY_CRC16_PR1_CCITT) {
3081  return -EINVAL;
3082  }
3083 
3084  conf->proto_settings.encoding = encoding;
3085  conf->proto_settings.parity = parity;
3086  return 0;
3087 }
3088 
3089 static int cpc_opench(pc300dev_t * d)
3090 {
3091  pc300ch_t *chan = (pc300ch_t *) d->chan;
3092  pc300_t *card = (pc300_t *) chan->card;
3093  int ch = chan->channel, rc;
3094  void __iomem *scabase = card->hw.scabase;
3095 
3096  rc = ch_config(d);
3097  if (rc)
3098  return rc;
3099 
3100  rx_config(d);
3101 
3102  tx_config(d);
3103 
3104  /* Assert RTS and DTR */
3105  cpc_writeb(scabase + M_REG(CTL, ch),
3106  cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3107 
3108  return 0;
3109 }
3110 
3111 static void cpc_closech(pc300dev_t * d)
3112 {
3113  pc300ch_t *chan = (pc300ch_t *) d->chan;
3114  pc300_t *card = (pc300_t *) chan->card;
3115  falc_t *pfalc = (falc_t *) & chan->falc;
3116  int ch = chan->channel;
3117 
3118  cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3119  rx_dma_stop(card, ch);
3120  tx_dma_stop(card, ch);
3121 
3122  if (card->hw.type == PC300_TE) {
3123  memset(pfalc, 0, sizeof(falc_t));
3124  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3125  cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3126  ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3127  CPLD_REG2_FALC_LED2) << (2 * ch)));
3128  /* Reset the FALC chip */
3129  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3130  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3131  (CPLD_REG1_FALC_RESET << (2 * ch)));
3132  udelay(10000);
3133  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3134  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3135  ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3136  }
3137 }
3138 
3139 int cpc_open(struct net_device *dev)
3140 {
3141  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3142  struct ifreq ifr;
3143  int result;
3144 
3145 #ifdef PC300_DEBUG_OTHER
3146  printk("pc300: cpc_open");
3147 #endif
3148 
3149  result = hdlc_open(dev);
3150 
3151  if (result)
3152  return result;
3153 
3154  sprintf(ifr.ifr_name, "%s", dev->name);
3155  result = cpc_opench(d);
3156  if (result)
3157  goto err_out;
3158 
3159  netif_start_queue(dev);
3160  return 0;
3161 
3162 err_out:
3163  hdlc_close(dev);
3164  return result;
3165 }
3166 
3167 static int cpc_close(struct net_device *dev)
3168 {
3169  pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3170  pc300ch_t *chan = (pc300ch_t *) d->chan;
3171  pc300_t *card = (pc300_t *) chan->card;
3172  unsigned long flags;
3173 
3174 #ifdef PC300_DEBUG_OTHER
3175  printk("pc300: cpc_close");
3176 #endif
3177 
3178  netif_stop_queue(dev);
3179 
3180  CPC_LOCK(card, flags);
3181  cpc_closech(d);
3182  CPC_UNLOCK(card, flags);
3183 
3184  hdlc_close(dev);
3185 
3186 #ifdef CONFIG_PC300_MLPPP
3187  if (chan->conf.proto == PC300_PROTO_MLPPP) {
3188  cpc_tty_unregister_service(d);
3189  chan->conf.proto = 0xffff;
3190  }
3191 #endif
3192 
3193  return 0;
3194 }
3195 
3196 static u32 detect_ram(pc300_t * card)
3197 {
3198  u32 i;
3199  u8 data;
3200  void __iomem *rambase = card->hw.rambase;
3201 
3202  card->hw.ramsize = PC300_RAMSIZE;
3203  /* Let's find out how much RAM is present on this board */
3204  for (i = 0; i < card->hw.ramsize; i++) {
3205  data = (u8)(i & 0xff);
3206  cpc_writeb(rambase + i, data);
3207  if (cpc_readb(rambase + i) != data) {
3208  break;
3209  }
3210  }
3211  return i;
3212 }
3213 
3214 static void plx_init(pc300_t * card)
3215 {
3216  struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3217 
3218  /* Reset PLX */
3219  cpc_writel(&plx_ctl->init_ctrl,
3220  cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3221  udelay(10000L);
3222  cpc_writel(&plx_ctl->init_ctrl,
3223  cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3224 
3225  /* Reload Config. Registers from EEPROM */
3226  cpc_writel(&plx_ctl->init_ctrl,
3227  cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3228  udelay(10000L);
3229  cpc_writel(&plx_ctl->init_ctrl,
3230  cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3231 
3232 }
3233 
3234 static void show_version(void)
3235 {
3236  char *rcsvers, *rcsdate, *tmp;
3237 
3238  rcsvers = strchr(rcsid, ' ');
3239  rcsvers++;
3240  tmp = strchr(rcsvers, ' ');
3241  *tmp++ = '\0';
3242  rcsdate = strchr(tmp, ' ');
3243  rcsdate++;
3244  tmp = strrchr(rcsdate, ' ');
3245  *tmp = '\0';
3246  pr_info("Cyclades-PC300 driver %s %s\n", rcsvers, rcsdate);
3247 } /* show_version */
3248 
3249 static const struct net_device_ops cpc_netdev_ops = {
3250  .ndo_open = cpc_open,
3251  .ndo_stop = cpc_close,
3252  .ndo_tx_timeout = cpc_tx_timeout,
3253  .ndo_set_mac_address = NULL,
3254  .ndo_change_mtu = cpc_change_mtu,
3255  .ndo_do_ioctl = cpc_ioctl,
3256  .ndo_validate_addr = eth_validate_addr,
3257 };
3258 
3259 static void cpc_init_card(pc300_t * card)
3260 {
3261  int i, devcount = 0;
3262  static int board_nbr = 1;
3263 
3264  /* Enable interrupts on the PCI bridge */
3265  plx_init(card);
3266  cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3267  cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3268 
3269 #ifdef USE_PCI_CLOCK
3270  /* Set board clock to PCI clock */
3271  cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3272  cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3273  card->hw.clock = PC300_PCI_CLOCK;
3274 #else
3275  /* Set board clock to internal oscillator clock */
3276  cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3277  cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3278  card->hw.clock = PC300_OSC_CLOCK;
3279 #endif
3280 
3281  /* Detect actual on-board RAM size */
3282  card->hw.ramsize = detect_ram(card);
3283 
3284  /* Set Global SCA-II registers */
3285  cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3286  cpc_writeb(card->hw.scabase + BTCR, 0x10);
3287  cpc_writeb(card->hw.scabase + WCRL, 0);
3288  cpc_writeb(card->hw.scabase + DMER, 0x80);
3289 
3290  if (card->hw.type == PC300_TE) {
3291  u8 reg1;
3292 
3293  /* Check CPLD version */
3294  reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3295  cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3296  if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3297  /* New CPLD */
3298  card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3299  card->hw.cpld_reg1 = CPLD_V2_REG1;
3300  card->hw.cpld_reg2 = CPLD_V2_REG2;
3301  } else {
3302  /* old CPLD */
3303  card->hw.cpld_id = 0;
3304  card->hw.cpld_reg1 = CPLD_REG1;
3305  card->hw.cpld_reg2 = CPLD_REG2;
3306  cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3307  }
3308 
3309  /* Enable the board's global clock */
3310  cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3311  cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3312  CPLD_REG1_GLOBAL_CLK);
3313 
3314  }
3315 
3316  for (i = 0; i < card->hw.nchan; i++) {
3317  pc300ch_t *chan = &card->chan[i];
3318  pc300dev_t *d = &chan->d;
3319  hdlc_device *hdlc;
3320  struct net_device *dev;
3321 
3322  chan->card = card;
3323  chan->channel = i;
3324  chan->conf.phys_settings.clock_rate = 0;
3325  chan->conf.phys_settings.clock_type = CLOCK_EXT;
3326  chan->conf.proto_settings.encoding = ENCODING_NRZ;
3327  chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3328  switch (card->hw.type) {
3329  case PC300_TE:
3330  chan->conf.media = IF_IFACE_T1;
3331  chan->conf.lcode = PC300_LC_B8ZS;
3332  chan->conf.fr_mode = PC300_FR_ESF;
3333  chan->conf.lbo = PC300_LBO_0_DB;
3334  chan->conf.rx_sens = PC300_RX_SENS_SH;
3335  chan->conf.tslot_bitmap = 0xffffffffUL;
3336  break;
3337 
3338  case PC300_X21:
3339  chan->conf.media = IF_IFACE_X21;
3340  break;
3341 
3342  case PC300_RSV:
3343  default:
3344  chan->conf.media = IF_IFACE_V35;
3345  break;
3346  }
3347  chan->conf.proto = IF_PROTO_PPP;
3348  chan->tx_first_bd = 0;
3349  chan->tx_next_bd = 0;
3350  chan->rx_first_bd = 0;
3351  chan->rx_last_bd = N_DMA_RX_BUF - 1;
3352  chan->nfree_tx_bd = N_DMA_TX_BUF;
3353 
3354  d->chan = chan;
3355  d->trace_on = 0;
3356  d->line_on = 0;
3357  d->line_off = 0;
3358 
3359  dev = alloc_hdlcdev(d);
3360  if (dev == NULL)
3361  continue;
3362 
3363  hdlc = dev_to_hdlc(dev);
3364  hdlc->xmit = cpc_queue_xmit;
3365  hdlc->attach = cpc_attach;
3366  d->dev = dev;
3367  dev->mem_start = card->hw.ramphys;
3368  dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3369  dev->irq = card->hw.irq;
3370  dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3371  dev->mtu = PC300_DEF_MTU;
3372 
3373  dev->netdev_ops = &cpc_netdev_ops;
3374  dev->watchdog_timeo = PC300_TX_TIMEOUT;
3375 
3376  if (register_hdlc_device(dev) == 0) {
3377  printk("%s: Cyclades-PC300/", dev->name);
3378  switch (card->hw.type) {
3379  case PC300_TE:
3380  if (card->hw.bus == PC300_PMC) {
3381  printk("TE-M");
3382  } else {
3383  printk("TE ");
3384  }
3385  break;
3386 
3387  case PC300_X21:
3388  printk("X21 ");
3389  break;
3390 
3391  case PC300_RSV:
3392  default:
3393  printk("RSV ");
3394  break;
3395  }
3396  printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3397  board_nbr, card->hw.ramsize / 1024,
3398  card->hw.ramphys, card->hw.irq, i + 1);
3399  devcount++;
3400  } else {
3401  printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3402  i + 1, card->hw.ramphys);
3403  free_netdev(dev);
3404  continue;
3405  }
3406  }
3407  spin_lock_init(&card->card_lock);
3408 
3409  board_nbr++;
3410 }
3411 
3412 static int __devinit
3413 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3414 {
3415  int err, eeprom_outdated = 0;
3416  u16 device_id;
3417  pc300_t *card;
3418 
3419  if ((err = pci_enable_device(pdev)) < 0)
3420  return err;
3421 
3422  card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3423  if (card == NULL) {
3424  printk("PC300 found at RAM 0x%016llx, "
3425  "but could not allocate card structure.\n",
3426  (unsigned long long)pci_resource_start(pdev, 3));
3427  err = -ENOMEM;
3428  goto err_disable_dev;
3429  }
3430 
3431  err = -ENODEV;
3432 
3433  /* read PCI configuration area */
3434  device_id = ent->device;
3435  card->hw.irq = pdev->irq;
3436  card->hw.iophys = pci_resource_start(pdev, 1);
3437  card->hw.iosize = pci_resource_len(pdev, 1);
3438  card->hw.scaphys = pci_resource_start(pdev, 2);
3439  card->hw.scasize = pci_resource_len(pdev, 2);
3440  card->hw.ramphys = pci_resource_start(pdev, 3);
3441  card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3442  card->hw.falcphys = pci_resource_start(pdev, 4);
3443  card->hw.falcsize = pci_resource_len(pdev, 4);
3444  card->hw.plxphys = pci_resource_start(pdev, 5);
3445  card->hw.plxsize = pci_resource_len(pdev, 5);
3446 
3447  switch (device_id) {
3448  case PCI_DEVICE_ID_PC300_RX_1:
3449  case PCI_DEVICE_ID_PC300_TE_1:
3450  case PCI_DEVICE_ID_PC300_TE_M_1:
3451  card->hw.nchan = 1;
3452  break;
3453 
3454  case PCI_DEVICE_ID_PC300_RX_2:
3455  case PCI_DEVICE_ID_PC300_TE_2:
3456  case PCI_DEVICE_ID_PC300_TE_M_2:
3457  default:
3458  card->hw.nchan = PC300_MAXCHAN;
3459  break;
3460  }
3461 #ifdef PC300_DEBUG_PCI
3462  printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3463  printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3464  printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3465  "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3466  card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3467  card->hw.falcphys);
3468 #endif
3469  /* Although we don't use this I/O region, we should
3470  * request it from the kernel anyway, to avoid problems
3471  * with other drivers accessing it. */
3472  if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3473  /* In case we can't allocate it, warn user */
3474  printk("WARNING: couldn't allocate I/O region for PC300 board "
3475  "at 0x%08x!\n", card->hw.ramphys);
3476  }
3477 
3478  if (card->hw.plxphys) {
3479  pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3480  } else {
3481  eeprom_outdated = 1;
3482  card->hw.plxphys = pci_resource_start(pdev, 0);
3483  card->hw.plxsize = pci_resource_len(pdev, 0);
3484  }
3485 
3486  if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3487  "PLX Registers")) {
3488  printk("PC300 found at RAM 0x%08x, "
3489  "but could not allocate PLX mem region.\n",
3490  card->hw.ramphys);
3491  goto err_release_io;
3492  }
3493  if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3494  "On-board RAM")) {
3495  printk("PC300 found at RAM 0x%08x, "
3496  "but could not allocate RAM mem region.\n",
3497  card->hw.ramphys);
3498  goto err_release_plx;
3499  }
3500  if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3501  "SCA-II Registers")) {
3502  printk("PC300 found at RAM 0x%08x, "
3503  "but could not allocate SCA mem region.\n",
3504  card->hw.ramphys);
3505  goto err_release_ram;
3506  }
3507 
3508  card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3509  card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3510  card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3511  switch (device_id) {
3512  case PCI_DEVICE_ID_PC300_TE_1:
3513  case PCI_DEVICE_ID_PC300_TE_2:
3514  case PCI_DEVICE_ID_PC300_TE_M_1:
3515  case PCI_DEVICE_ID_PC300_TE_M_2:
3516  request_mem_region(card->hw.falcphys, card->hw.falcsize,
3517  "FALC Registers");
3518  card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3519  break;
3520 
3521  case PCI_DEVICE_ID_PC300_RX_1:
3522  case PCI_DEVICE_ID_PC300_RX_2:
3523  default:
3524  card->hw.falcbase = NULL;
3525  break;
3526  }
3527 
3528 #ifdef PC300_DEBUG_PCI
3529  printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3530  "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3531  card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3532  card->hw.falcbase);
3533 #endif
3534 
3535  /* Set PCI drv pointer to the card structure */
3536  pci_set_drvdata(pdev, card);
3537 
3538  /* Set board type */
3539  switch (device_id) {
3540  case PCI_DEVICE_ID_PC300_TE_1:
3541  case PCI_DEVICE_ID_PC300_TE_2:
3542  case PCI_DEVICE_ID_PC300_TE_M_1:
3543  case PCI_DEVICE_ID_PC300_TE_M_2:
3544  card->hw.type = PC300_TE;
3545 
3546  if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3547  (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3548  card->hw.bus = PC300_PMC;
3549  /* Set PLX register offsets */
3550  card->hw.gpioc_reg = 0x54;
3551  card->hw.intctl_reg = 0x4c;
3552  } else {
3553  card->hw.bus = PC300_PCI;
3554  /* Set PLX register offsets */
3555  card->hw.gpioc_reg = 0x50;
3556  card->hw.intctl_reg = 0x4c;
3557  }
3558  break;
3559 
3560  case PCI_DEVICE_ID_PC300_RX_1:
3561  case PCI_DEVICE_ID_PC300_RX_2:
3562  default:
3563  card->hw.bus = PC300_PCI;
3564  /* Set PLX register offsets */
3565  card->hw.gpioc_reg = 0x50;
3566  card->hw.intctl_reg = 0x4c;
3567 
3568  if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3569  card->hw.type = PC300_X21;
3570  } else {
3571  card->hw.type = PC300_RSV;
3572  }
3573  break;
3574  }
3575 
3576  /* Allocate IRQ */
3577  if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3578  printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3579  card->hw.ramphys, card->hw.irq);
3580  goto err_io_unmap;
3581  }
3582 
3583  cpc_init_card(card);
3584 
3585  if (eeprom_outdated)
3586  printk("WARNING: PC300 with outdated EEPROM.\n");
3587  return 0;
3588 
3589 err_io_unmap:
3590  iounmap(card->hw.plxbase);
3591  iounmap(card->hw.scabase);
3592  iounmap(card->hw.rambase);
3593  if (card->hw.type == PC300_TE) {
3594  iounmap(card->hw.falcbase);
3595  release_mem_region(card->hw.falcphys, card->hw.falcsize);
3596  }
3597  release_mem_region(card->hw.scaphys, card->hw.scasize);
3598 err_release_ram:
3599  release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3600 err_release_plx:
3601  release_mem_region(card->hw.plxphys, card->hw.plxsize);
3602 err_release_io:
3603  release_region(card->hw.iophys, card->hw.iosize);
3604  kfree(card);
3605 err_disable_dev:
3606  pci_disable_device(pdev);
3607  return err;
3608 }
3609 
3610 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3611 {
3612  pc300_t *card = pci_get_drvdata(pdev);
3613 
3614  if (card->hw.rambase) {
3615  int i;
3616 
3617  /* Disable interrupts on the PCI bridge */
3618  cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3619  cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3620 
3621  for (i = 0; i < card->hw.nchan; i++) {
3622  unregister_hdlc_device(card->chan[i].d.dev);
3623  }
3624  iounmap(card->hw.plxbase);
3625  iounmap(card->hw.scabase);
3626  iounmap(card->hw.rambase);
3627  release_mem_region(card->hw.plxphys, card->hw.plxsize);
3628  release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3629  release_mem_region(card->hw.scaphys, card->hw.scasize);
3630  release_region(card->hw.iophys, card->hw.iosize);
3631  if (card->hw.type == PC300_TE) {
3632  iounmap(card->hw.falcbase);
3633  release_mem_region(card->hw.falcphys, card->hw.falcsize);
3634  }
3635  for (i = 0; i < card->hw.nchan; i++)
3636  if (card->chan[i].d.dev)
3637  free_netdev(card->chan[i].d.dev);
3638  if (card->hw.irq)
3639  free_irq(card->hw.irq, card);
3640  kfree(card);
3641  pci_disable_device(pdev);
3642  }
3643 }
3644 
3645 static struct pci_driver cpc_driver = {
3646  .name = "pc300",
3647  .id_table = cpc_pci_dev_id,
3648  .probe = cpc_init_one,
3649  .remove = __devexit_p(cpc_remove_one),
3650 };
3651 
3652 static int __init cpc_init(void)
3653 {
3654  show_version();
3655  return pci_register_driver(&cpc_driver);
3656 }
3657 
3658 static void __exit cpc_cleanup_module(void)
3659 {
3660  pci_unregister_driver(&cpc_driver);
3661 }
3662 
3663 module_init(cpc_init);
3664 module_exit(cpc_cleanup_module);
3665 
3666 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3667 MODULE_AUTHOR( "Author: Ivan Passos <[email protected]>\r\n"
3668  "Maintainer: PC300 Maintainer <[email protected]");
3669 MODULE_LICENSE("GPL");
3670 
Generated on Thu Jan 10 2013 14:29:45 for Linux Kernel by   doxygen 1.8.2