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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/mii.h>#include <linux/delay.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/ethtool.h>#include <linux/vmalloc.h>#include <net/ip.h>#include <net/tcp.h>#include <net/udp.h>Go to the source code of this file.
Data Structures | |
| struct | pch_gbe_regs_mac_adr |
| struct | pch_gbe_regs |
| struct | pch_gbe_functions |
| struct | pch_gbe_mac_info |
| struct | pch_gbe_phy_info |
| struct | pch_gbe_bus_info |
| Bus information. More... | |
| struct | pch_gbe_hw |
| Hardware information. More... | |
| struct | pch_gbe_rx_desc |
| struct | pch_gbe_tx_desc |
| struct | pch_gbe_buffer |
| struct | pch_gbe_tx_ring |
| struct | pch_gbe_rx_ring |
| struct | pch_gbe_hw_stats |
| struct | pch_gbe_adapter |
Macros | |
| #define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| #define | PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */ |
| #define | PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */ |
| #define | PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */ |
| #define | PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */ |
| #define | PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */ |
| #define | PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */ |
| #define | PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */ |
| #define | PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */ |
| #define | PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */ |
| #define | PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */ |
| #define | PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */ |
| #define | PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */ |
| #define | PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */ |
| #define | PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */ |
| #define | PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */ |
| #define | PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */ |
| #define | PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */ |
| #define | PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */ |
| #define | PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */ |
| #define | PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */ |
| #define | PCH_GBE_ALL_RST 0x80000000 /* All reset */ |
| #define | PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */ |
| #define | PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */ |
| #define | PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ |
| #define | PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */ |
| #define | PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */ |
| #define | PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */ |
| #define | PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */ |
| #define | PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */ |
| #define | PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */ |
| #define | PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */ |
| #define | PCH_GBE_MLT_FIL_EN 0x40000000 |
| #define | PCH_GBE_RH_ALM_EMP_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_RH_ALM_EMP_8 0x00004000 /* 8 words */ |
| #define | PCH_GBE_RH_ALM_EMP_16 0x00008000 /* 16 words */ |
| #define | PCH_GBE_RH_ALM_EMP_32 0x0000C000 /* 32 words */ |
| #define | PCH_GBE_RH_ALM_FULL_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_RH_ALM_FULL_8 0x00001000 /* 8 words */ |
| #define | PCH_GBE_RH_ALM_FULL_16 0x00002000 /* 16 words */ |
| #define | PCH_GBE_RH_ALM_FULL_32 0x00003000 /* 32 words */ |
| #define | PCH_GBE_RH_RD_TRG_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_RH_RD_TRG_8 0x00000200 /* 8 words */ |
| #define | PCH_GBE_RH_RD_TRG_16 0x00000400 /* 16 words */ |
| #define | PCH_GBE_RH_RD_TRG_32 0x00000600 /* 32 words */ |
| #define | PCH_GBE_RH_RD_TRG_64 0x00000800 /* 64 words */ |
| #define | PCH_GBE_RH_RD_TRG_128 0x00000A00 /* 128 words */ |
| #define | PCH_GBE_RH_RD_TRG_256 0x00000C00 /* 256 words */ |
| #define | PCH_GBE_RH_RD_TRG_512 0x00000E00 /* 512 words */ |
| #define | PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 |
| #define | PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 |
| #define | PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 |
| #define | PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0 |
| #define | PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 |
| #define | PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 |
| #define | PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 |
| #define | PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 |
| #define | PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 |
| #define | PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 |
| #define | PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 |
| #define | PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 |
| #define | PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 |
| #define | PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 |
| #define | PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 |
| #define | PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 |
| #define | PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 |
| #define | PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 |
| #define | PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 |
| #define | PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 |
| #define | PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 |
| #define | PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 |
| #define | PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 |
| #define | PCH_GBE_TXD_CTRL_ITAG 0x0004 |
| #define | PCH_GBE_TXD_CTRL_ICRC 0x0002 |
| #define | PCH_GBE_TXD_CTRL_APAD 0x0001 |
| #define | PCH_GBE_TXD_WORDS_SHIFT 2 |
| #define | PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 |
| #define | PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 |
| #define | PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 |
| #define | PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 |
| #define | PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 |
| #define | PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 |
| #define | PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 |
| #define | PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 |
| #define | PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 |
| #define | PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 |
| #define | PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F |
| #define | PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */ |
| #define | PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */ |
| #define | PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */ |
| #define | PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */ |
| #define | PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */ |
| #define | PCH_GBE_TM_TH_TX_STRT_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_TM_TH_TX_STRT_8 0x00004000 /* 8 words */ |
| #define | PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */ |
| #define | PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 /* 8 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */ |
| #define | PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */ |
| #define | PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 /* 4 words */ |
| #define | PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 /* 8 words */ |
| #define | PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */ |
| #define | PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */ |
| #define | PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */ |
| #define | PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */ |
| #define | PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */ |
| #define | PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */ |
| #define | PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */ |
| #define | PCH_GBE_BUSY 0x80000000 |
| #define | PCH_GBE_MIIM_OPER_WRITE 0x04000000 |
| #define | PCH_GBE_MIIM_OPER_READ 0x00000000 |
| #define | PCH_GBE_MIIM_OPER_READY 0x04000000 |
| #define | PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 |
| #define | PCH_GBE_MIIM_REG_ADDR_SHIFT 16 |
| #define | PCH_GBE_LINK_UP 0x80000008 |
| #define | PCH_GBE_RXC_SPEED_MSK 0x00000006 |
| #define | PCH_GBE_RXC_SPEED_2_5M 0x00000000 /* 2.5MHz */ |
| #define | PCH_GBE_RXC_SPEED_25M 0x00000002 /* 25MHz */ |
| #define | PCH_GBE_RXC_SPEED_125M 0x00000004 /* 100MHz */ |
| #define | PCH_GBE_DUPLEX_FULL 0x00000001 |
| #define | PCH_GBE_CRS_SEL 0x00000010 |
| #define | PCH_GBE_RGMII_RATE_125M 0x00000000 |
| #define | PCH_GBE_RGMII_RATE_25M 0x00000008 |
| #define | PCH_GBE_RGMII_RATE_2_5M 0x0000000C |
| #define | PCH_GBE_RGMII_MODE_GMII 0x00000000 |
| #define | PCH_GBE_RGMII_MODE_RGMII 0x00000002 |
| #define | PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 |
| #define | PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 |
| #define | PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ |
| #define | PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ |
| #define | PCH_GBE_IDLE_CHECK 0xFFFFFFFE |
| #define | PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ |
| #define | PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ |
| #define | PCH_GBE_WLS_IND 0x00000002 |
| #define | PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */ |
| #define | PCH_GBE_WLC_WOL_MODE 0x00010000 |
| #define | PCH_GBE_WLC_IGN_TLONG 0x00000100 |
| #define | PCH_GBE_WLC_IGN_TSHRT 0x00000080 |
| #define | PCH_GBE_WLC_IGN_OCTER 0x00000040 |
| #define | PCH_GBE_WLC_IGN_NBLER 0x00000020 |
| #define | PCH_GBE_WLC_IGN_CRCER 0x00000010 |
| #define | PCH_GBE_WLC_BR 0x00000008 |
| #define | PCH_GBE_WLC_MLT 0x00000004 |
| #define | PCH_GBE_WLC_IND 0x00000002 |
| #define | PCH_GBE_WLC_MP 0x00000001 |
| #define | PCH_GBE_WLA_BUSY 0x80000000 |
| #define | PCH_GBE_MAX_TXD 4096 |
| #define | PCH_GBE_DEFAULT_TXD 256 |
| #define | PCH_GBE_MIN_TXD 8 |
| #define | PCH_GBE_MAX_RXD 4096 |
| #define | PCH_GBE_DEFAULT_RXD 256 |
| #define | PCH_GBE_MIN_RXD 8 |
| #define | PCH_GBE_TX_DESC_MULTIPLE 8 |
| #define | PCH_GBE_RX_DESC_MULTIPLE 8 |
| #define | PCH_GBE_HAL_MIIM_READ ((u32)0x00000000) |
| #define | PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000) |
| #define | PCH_GBE_FC_NONE 0 |
| #define | PCH_GBE_FC_RX_PAUSE 1 |
| #define | PCH_GBE_FC_TX_PAUSE 2 |
| #define | PCH_GBE_FC_FULL 3 |
| #define | PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL |
Variables | |
| const char | pch_driver_version [] |
| #define PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */ |
| #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ |
| #define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL |
| #define PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */ |
| #define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */ |
| #define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */ |
| #define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */ |
| #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */ |
| #define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */ |
| #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */ |
| #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */ |
| #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */ |
| #define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */ |
| #define PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */ |
| #define PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */ |
| #define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */ |
| #define PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */ |
| #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */ |
| #define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */ |
| #define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */ |
| #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */ |
| #define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */ |
| #define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */ |
| #define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */ |
| #define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */ |
| #define PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */ |
| #define PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */ |
| #define PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */ |
| #define PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */ |
| #define PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */ |
| #define PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */ |
| #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ |
| #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */ |
| #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */ |
| #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */ |
| #define PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */ |
| #define PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */ |
| #define PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */ |
| #define PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */ |
| #define PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */ |
| #define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */ |
| #define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */ |
| #define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */ |
| #define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */ |
| #define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */ |
| #define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */ |
| #define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */ |
| #define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */ |
| #define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */ |
| #define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */ |
| #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ |
| #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */ |
| #define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */ |
| #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ |
| #define PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */ |
| void pch_gbe_check_options | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_check_options - Range Checking for Command Line Parameters : Board private structure
Definition at line 427 of file pch_gbe_param.c.
| void pch_gbe_down | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_down - Down GbE network device : Board private structure
Definition at line 1983 of file pch_gbe_main.c.
| void pch_gbe_free_rx_resources | ( | struct pch_gbe_adapter * | adapter, |
| struct pch_gbe_rx_ring * | rx_ring | ||
| ) |
pch_gbe_free_rx_resources - Free Rx Resources : Board private structure : Ring to clean the resources from
Definition at line 1876 of file pch_gbe_main.c.
| void pch_gbe_free_tx_resources | ( | struct pch_gbe_adapter * | adapter, |
| struct pch_gbe_tx_ring * | tx_ring | ||
| ) |
pch_gbe_free_tx_resources - Free Tx Resources : Board private structure : Tx descriptor ring for a specific queue
Definition at line 1859 of file pch_gbe_main.c.
Definition at line 552 of file pch_gbe_main.c.
| s32 pch_gbe_mac_force_mac_fc | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings : Pointer to the HW structure Returns: 0: Successful. Negative value: Failed.
Definition at line 475 of file pch_gbe_main.c.
| s32 pch_gbe_mac_read_mac_addr | ( | struct pch_gbe_hw * | hw | ) |
pch_gbe_mac_read_mac_addr - Read MAC address : Pointer to the HW structure Returns: 0: Successful.
Definition at line 307 of file pch_gbe_main.c.
| void pch_gbe_reinit_locked | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_reinit_locked- Re-initialization : Board private structure
Definition at line 755 of file pch_gbe_main.c.
| void pch_gbe_reset | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_reset - Reset GbE : Board private structure
Definition at line 765 of file pch_gbe_main.c.
| void pch_gbe_set_ethtool_ops | ( | struct net_device * | netdev | ) |
Definition at line 509 of file pch_gbe_ethtool.c.
| int pch_gbe_setup_rx_resources | ( | struct pch_gbe_adapter * | adapter, |
| struct pch_gbe_rx_ring * | rx_ring | ||
| ) |
pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors) : Board private structure : Rx descriptor ring (for a specific queue) to setup Returns: 0: Successfully Negative value: Failed
Definition at line 1818 of file pch_gbe_main.c.
| int pch_gbe_setup_tx_resources | ( | struct pch_gbe_adapter * | adapter, |
| struct pch_gbe_tx_ring * | tx_ring | ||
| ) |
pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors) : Board private structure : Tx descriptor ring (for a specific queue) to setup Returns: 0: Successfully Negative value: Failed
Definition at line 1771 of file pch_gbe_main.c.
| int pch_gbe_up | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_up - Up GbE network device : Board private structure Returns: 0: Successfully Negative value: Failed
Definition at line 1928 of file pch_gbe_main.c.
| void pch_gbe_update_stats | ( | struct pch_gbe_adapter * | adapter | ) |
pch_gbe_update_stats - Update the board statistics counters : Board private structure
Definition at line 1258 of file pch_gbe_main.c.
Definition at line 30 of file pch_gbe_main.c.
1.8.2