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pci_x86.h
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1 /*
2  * Low-Level PCI Access for i386 machines.
3  *
4  * (c) 1999 Martin Mares <[email protected]>
5  */
6 
7 #undef DEBUG
8 
9 #ifdef DEBUG
10 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
11 #else
12 #define DBG(fmt, ...) \
13 do { \
14  if (0) \
15  printk(fmt, ##__VA_ARGS__); \
16 } while (0)
17 #endif
18 
19 #define PCI_PROBE_BIOS 0x0001
20 #define PCI_PROBE_CONF1 0x0002
21 #define PCI_PROBE_CONF2 0x0004
22 #define PCI_PROBE_MMCONF 0x0008
23 #define PCI_PROBE_MASK 0x000f
24 #define PCI_PROBE_NOEARLY 0x0010
25 
26 #define PCI_NO_CHECKS 0x0400
27 #define PCI_USE_PIRQ_MASK 0x0800
28 #define PCI_ASSIGN_ROMS 0x1000
29 #define PCI_BIOS_IRQ_SCAN 0x2000
30 #define PCI_ASSIGN_ALL_BUSSES 0x4000
31 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
32 #define PCI_USE__CRS 0x10000
33 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
34 #define PCI_HAS_IO_ECS 0x40000
35 #define PCI_NOASSIGN_ROMS 0x80000
36 #define PCI_ROOT_NO_CRS 0x100000
37 #define PCI_NOASSIGN_BARS 0x200000
38 
39 extern unsigned int pci_probe;
40 extern unsigned long pirq_table_addr;
41 
47 };
48 
49 /* pci-i386.c */
50 
51 void pcibios_resource_survey(void);
53 
54 /* pci-pc.c */
55 
56 extern int pcibios_last_bus;
57 extern struct pci_bus *pci_root_bus;
58 extern struct pci_ops pci_root_ops;
59 
60 void pcibios_scan_specific_bus(int busn);
61 
62 /* pci-irq.c */
63 
64 struct irq_info {
65  u8 bus, devfn; /* Bus, device and function */
66  struct {
67  u8 link; /* IRQ line ID, chipset dependent,
68  0 = not routed */
69  u16 bitmap; /* Available IRQs */
70  } __attribute__((packed)) irq[4];
71  u8 slot; /* Slot number, 0=onboard */
72  u8 rfu;
73 } __attribute__((packed));
74 
76  u32 signature; /* PIRQ_SIGNATURE should be here */
77  u16 version; /* PIRQ_VERSION */
78  u16 size; /* Table size in bytes */
79  u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
80  u16 exclusive_irqs; /* IRQs devoted exclusively to
81  PCI usage */
82  u16 rtr_vendor, rtr_device; /* Vendor and device ID of
83  interrupt router */
84  u32 miniport_data; /* Crap */
85  u8 rfu[11];
86  u8 checksum; /* Modulo 256 checksum must give 0 */
87  struct irq_info slots[0];
88 } __attribute__((packed));
89 
90 extern unsigned int pcibios_irq_mask;
91 
93 
94 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
95 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
96 
97 struct pci_raw_ops {
98  int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
99  int reg, int len, u32 *val);
100  int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
101  int reg, int len, u32 val);
102 };
103 
104 extern const struct pci_raw_ops *raw_pci_ops;
105 extern const struct pci_raw_ops *raw_pci_ext_ops;
106 
107 extern const struct pci_raw_ops pci_mmcfg;
108 extern const struct pci_raw_ops pci_direct_conf1;
109 extern bool port_cf9_safe;
110 
111 /* arch_initcall level */
112 extern int pci_direct_probe(void);
113 extern void pci_direct_init(int type);
114 extern void pci_pcbios_init(void);
115 extern void __init dmi_check_pciprobe(void);
116 extern void __init dmi_check_skip_isa_align(void);
117 
118 /* some common used subsys_initcalls */
119 extern int __init pci_acpi_init(void);
120 extern void __init pcibios_irq_init(void);
121 extern int __init pcibios_init(void);
122 extern int pci_legacy_init(void);
123 extern void pcibios_fixup_irqs(void);
124 
125 /* pci-mmconfig.c */
126 
127 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
128 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
129 
131  struct list_head list;
132  struct resource res;
134  char __iomem *virt;
139 };
140 
141 extern int __init pci_mmcfg_arch_init(void);
142 extern void __init pci_mmcfg_arch_free(void);
144 extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
145 extern int __devinit pci_mmconfig_insert(struct device *dev,
146  u16 seg, u8 start,
148 extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
149 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
150 
151 extern struct list_head pci_mmcfg_list;
152 
153 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
154 
155 /*
156  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
157  * on their northbrige except through the * %eax register. As such, you MUST
158  * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
159  * accessor functions.
160  * In fact just use pci_config_*, nothing else please.
161  */
162 static inline unsigned char mmio_config_readb(void __iomem *pos)
163 {
164  u8 val;
165  asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
166  return val;
167 }
168 
169 static inline unsigned short mmio_config_readw(void __iomem *pos)
170 {
171  u16 val;
172  asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
173  return val;
174 }
175 
176 static inline unsigned int mmio_config_readl(void __iomem *pos)
177 {
178  u32 val;
179  asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
180  return val;
181 }
182 
183 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
184 {
185  asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
186 }
187 
188 static inline void mmio_config_writew(void __iomem *pos, u16 val)
189 {
190  asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
191 }
192 
193 static inline void mmio_config_writel(void __iomem *pos, u32 val)
194 {
195  asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
196 }
197 
198 #ifdef CONFIG_PCI
199 # ifdef CONFIG_ACPI
200 # define x86_default_pci_init pci_acpi_init
201 # else
202 # define x86_default_pci_init pci_legacy_init
203 # endif
204 # define x86_default_pci_init_irq pcibios_irq_init
205 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
206 #else
207 # define x86_default_pci_init NULL
208 # define x86_default_pci_init_irq NULL
209 # define x86_default_pci_fixup_irqs NULL
210 #endif